| commit | 3bb0b03897abb634231366ce4e6651b56f16aa26 | |
| author | Luc Michel <luc.michel@greensocs.com> | |
| Tue, 14 Aug 2018 16:17:19 +0000 (14 17:17 +0100) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Tue, 14 Aug 2018 16:17:19 +0000 (14 17:17 +0100) | ||
| tree | 3add5315c37b2029e5dae5b33783e4f8b27ca40c | treesnapshot (tar.gz zip) |
| parent | 67ce697ac84bd7f44348830df43f05195d5987e6 | commitdiff |
intc/arm_gic: Implement GICD_ISACTIVERn and GICD_ICACTIVERn registers
Implement GICD_ISACTIVERn and GICD_ICACTIVERn registers in the GICv2.
Those registers allow to set or clear the active state of an IRQ in the
distributor.
Signed-off-by: Luc Michel <luc.michel@greensocs.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20180727095421.386-3-luc.michel@greensocs.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Implement GICD_ISACTIVERn and GICD_ICACTIVERn registers in the GICv2.
Those registers allow to set or clear the active state of an IRQ in the
distributor.
Signed-off-by: Luc Michel <luc.michel@greensocs.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20180727095421.386-3-luc.michel@greensocs.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| hw/intc/arm_gic.c | diffblobblamehistory |