target/ppc: Honor fpscr_ze semantics and tidy fre, fresqrt
commit384347175588912a75e3b9d14d868fd3d646c9db
authorRichard Henderson <richard.henderson@linaro.org>
Tue, 3 Jul 2018 15:17:31 +0000 (3 08:17 -0700)
committerDavid Gibson <david@gibson.dropbear.id.au>
Tue, 21 Aug 2018 04:28:45 +0000 (21 14:28 +1000)
treea38ecfea1c6c55e1f23c7a2ee66c9bbdb2ad0787
parent49ab52ef69c804264fd2c61a9a61678a23d4fb33
target/ppc: Honor fpscr_ze semantics and tidy fre, fresqrt

Divide by zero, exception taken, leaves the destination register
unmodified.  Therefore we must raise the exception before returning
from the respective helpers.

>From helper_fre, divide by zero exception not taken, return the
documented +/- 0.5.

At the same time, tidy the invalid exception checking so that we
rely on softfloat for initial argument validation, and select the
kind of invalid operand exception only when we know we must.

At the same time, pass and return float64 values directly rather
than bounce through the CPU_DoubleU union.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
target/ppc/fpu_helper.c