| commit | 334e8dad7a109d15cb20b090131374ae98682a50 | |
| author | Peter Maydell <peter.maydell@linaro.org> | |
| Thu, 7 Sep 2017 12:54:54 +0000 (7 13:54 +0100) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Thu, 7 Sep 2017 12:54:54 +0000 (7 13:54 +0100) | ||
| tree | 2fba32a173c5a786c993ff609098e4403cd405e9 | treesnapshot (tar.gz zip) |
| parent | c51a5cfc9fae82099028eb12cb1d064ee07f348e | commitdiff |
target/arm: Make CFSR register banked for v8M
Make the CFSR register banked if v8M security extensions are enabled.
Not all the bits in this register are banked: the BFSR
bits [15:8] are shared between S and NS, and we store them
in the NS copy of the register.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1503414539-28762-19-git-send-email-peter.maydell@linaro.org
Make the CFSR register banked if v8M security extensions are enabled.
Not all the bits in this register are banked: the BFSR
bits [15:8] are shared between S and NS, and we store them
in the NS copy of the register.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1503414539-28762-19-git-send-email-peter.maydell@linaro.org
| hw/intc/armv7m_nvic.c | diffblobblamehistory | |
| target/arm/cpu.h | diffblobblamehistory | |
| target/arm/helper.c | diffblobblamehistory | |
| target/arm/machine.c | diffblobblamehistory |