| commit | 2d9177588bde9881c6602284d1b0b08e4dfe361e | |
| author | Peter Maydell <peter.maydell@linaro.org> | |
| Mon, 10 Nov 2014 13:56:47 +0000 (10 13:56 +0000) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Mon, 10 Nov 2014 13:56:47 +0000 (10 13:56 +0000) | ||
| tree | 047fad0a24365ed125454953746daa7a4b88ca67 | treesnapshot (tar.gz zip) |
| parent | 7b4b7c5fc7f25a161839802ca7d23f50f99e5174 | commitdiff |
| parent | cb269f273fdbdb26ddb1cba4a0fe2249418a8e77 | commitdiff |
Merge remote-tracking branch 'remotes/lalrae/tags/mips-20141107' into staging
* remotes/lalrae/tags/mips-20141107:
target-mips: fix multiple TCG registers covering same data
mips: Ensure PC update with MTC0 single-stepping
target-mips: fix for missing delay slot in BC1EQZ and BC1NEZ
mips: Set the CP0.Config3.DSP and CP0.Config3.DSP2P bits
mips: Add macros for CP0.Config3 and CP0.Config4 bits
mips: Respect CP0.Status.CU1 for microMIPS FP branches
mips: Remove CONFIG_VT82C686 from non-Fulong configs
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* remotes/lalrae/tags/mips-20141107:
target-mips: fix multiple TCG registers covering same data
mips: Ensure PC update with MTC0 single-stepping
target-mips: fix for missing delay slot in BC1EQZ and BC1NEZ
mips: Set the CP0.Config3.DSP and CP0.Config3.DSP2P bits
mips: Add macros for CP0.Config3 and CP0.Config4 bits
mips: Respect CP0.Status.CU1 for microMIPS FP branches
mips: Remove CONFIG_VT82C686 from non-Fulong configs
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>