| commit | 2133a5f6b8f8941a6a3734c6c1990656553de76c | |
| author | Peter Crosthwaite <peter.crosthwaite@xilinx.com> | |
| Mon, 3 Jun 2013 16:17:43 +0000 (3 17:17 +0100) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Mon, 3 Jun 2013 16:17:43 +0000 (3 17:17 +0100) | ||
| tree | 886e8997b1b0625734040b6765b129736d59aeed | treesnapshot (tar.gz zip) |
| parent | 15408b428f5b4db56da555fbda4f1aaf40d77f4b | commitdiff |
xilinx_spips: Fix CTRL register RW bits
The CTRL register was RAZ/WI on some of the RW bits. Even though the
function behind these bits is invalid in QEMU, they should still be
guest accessible. Fix.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Message-id: b7aaad93163ce4af0c428635804ac7b77a567b25.1369117359.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
The CTRL register was RAZ/WI on some of the RW bits. Even though the
function behind these bits is invalid in QEMU, they should still be
guest accessible. Fix.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Message-id: b7aaad93163ce4af0c428635804ac7b77a567b25.1369117359.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| hw/ssi/xilinx_spips.c | diffblobblamehistory |