| commit | 1f1a7b226923c655530d6bbe7d85d87e3df2d6f1 | |
| author | Francisco Iglesias <frasse.iglesias@gmail.com> | |
| Mon, 11 Apr 2022 22:18:36 +0000 (12 00:18 +0200) | ||
| committer | Michael S. Tsirkin <mst@redhat.com> | |
| Mon, 16 May 2022 20:15:40 +0000 (16 16:15 -0400) | ||
| tree | c35a8f2cea78fd3e457094912e696b654bd7d0c0 | treesnapshot (tar.gz zip) |
| parent | 8e58f6ec24f64b7d88f2b01d39049011f5097fae | commitdiff |
include/hw/pci/pcie_host: Correct PCIE_MMCFG_SIZE_MAX
According to 7.2.2 in [1] bit 27 is the last bit that can be part of the
bus number, this makes the ECAM max size equal to '1 << 28'. This patch
restores back this value into the PCIE_MMCFG_SIZE_MAX define (which was
changed in commit 58d5b22bbd5 ("ppc4xx: Add device models found in PPC440
core SoCs")).
[1] PCI Express® Base Specification Revision 5.0 Version 1.0
Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-Id: <20220411221836.17699-3-frasse.iglesias@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
According to 7.2.2 in [1] bit 27 is the last bit that can be part of the
bus number, this makes the ECAM max size equal to '1 << 28'. This patch
restores back this value into the PCIE_MMCFG_SIZE_MAX define (which was
changed in commit 58d5b22bbd5 ("ppc4xx: Add device models found in PPC440
core SoCs")).
[1] PCI Express® Base Specification Revision 5.0 Version 1.0
Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-Id: <20220411221836.17699-3-frasse.iglesias@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| include/hw/pci/pcie_host.h | diffblobblamehistory |