| commit | 1db3632a14f44e243068bcf89bcf0739b657972b | |
| author | Matheus Ferst <matheus.ferst@eldorado.org.br> | |
| Fri, 17 Sep 2021 11:47:50 +0000 (17 08:47 -0300) | ||
| committer | David Gibson <david@gibson.dropbear.id.au> | |
| Thu, 30 Sep 2021 02:26:06 +0000 (30 12:26 +1000) | ||
| tree | 0251623fa0ed95cf4cd431dfbb0f0dff32918604 | treesnapshot (tar.gz zip) |
| parent | 7279810b67b6ea16f9b6060693a286dc6deb3036 | commitdiff |
target/ppc: add LPCR[HR] to DisasContext and hflags
Add a Host Radix field (hr) in DisasContext with LPCR[HR] value to allow
us to decide between Radix and HPT while validating instructions
arguments. Note that PowerISA v3.1 does not require LPCR[HR] and PATE.HR
to match if the thread is in ultravisor/hypervisor real addressing mode,
so ctx->hr may be invalid if ctx->hv and ctx->dr are set.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20210917114751.206845-2-matheus.ferst@eldorado.org.br>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Add a Host Radix field (hr) in DisasContext with LPCR[HR] value to allow
us to decide between Radix and HPT while validating instructions
arguments. Note that PowerISA v3.1 does not require LPCR[HR] and PATE.HR
to match if the thread is in ultravisor/hypervisor real addressing mode,
so ctx->hr may be invalid if ctx->hv and ctx->dr are set.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20210917114751.206845-2-matheus.ferst@eldorado.org.br>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| target/ppc/cpu.h | diffblobblamehistory | |
| target/ppc/helper_regs.c | diffblobblamehistory | |
| target/ppc/translate.c | diffblobblamehistory |