| commit | 1090b9c6ccfe837f1c76dafb7e56031bd7844075 | |
| author | Peter Maydell <peter.maydell@linaro.org> | |
| Tue, 15 Apr 2014 18:18:46 +0000 (15 19:18 +0100) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Thu, 17 Apr 2014 20:34:05 +0000 (17 21:34 +0100) | ||
| tree | dcefb350ea9e9d53f395d506c55dd8b2ed14d717 | treesnapshot (tar.gz zip) |
| parent | 2eef0bf82146034f756d39cb02c8c8dd561a8942 | commitdiff |
target-arm: Implement ISR_EL1 register
Implement the ISR_EL1 register. This is actually present in
ARMv7 as well but was previously unimplemented. It is a
read-only register that indicates whether interrupts are
currently pending.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Implement the ISR_EL1 register. This is actually present in
ARMv7 as well but was previously unimplemented. It is a
read-only register that indicates whether interrupts are
currently pending.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
| target-arm/helper.c | diffblobblamehistory |