target/riscv: FP extension requirements
commit1086504c6f46a2b3be90e887dddb4741bf8c500d
authorTsukasa OI <research_trasio@irq.a4lg.com>
Sun, 15 May 2022 02:56:10 +0000 (15 11:56 +0900)
committerAlistair Francis <alistair.francis@wdc.com>
Tue, 24 May 2022 00:38:50 +0000 (24 10:38 +1000)
tree61bcaffe39421638518cac51d5b4321a4f918181
parent9f6b7da5d27b744ddbdba98ba8b89c710dd3c1b7
target/riscv: FP extension requirements

QEMU allowed inconsistent configurations that made floating point
arithmetic effectively unusable.

This commit adds certain checks for consistent FP arithmetic:

-   F requires Zicsr
-   Zfinx requires Zicsr
-   Zfh/Zfhmin require F
-   D requires F
-   V requires D

Because F/D/Zicsr are enabled by default (and an error will not occur unless
we manually disable one or more of prerequisites), this commit just enforces
the user to give consistent combinations.

Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <00e7b1c6060dab32ac7d49813b1ca84d3eb63298.1652583332.git.research_trasio@irq.a4lg.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.c