| commit | 0b572c8131998e7bcd048dbbbe78f95e6101d68d | |
| author | Weiwei Li <liweiwei@iscas.ac.cn> | |
| Mon, 18 Jul 2022 13:09:50 +0000 (18 21:09 +0800) | ||
| committer | Alistair Francis <alistair.francis@wdc.com> | |
| Wed, 7 Sep 2022 07:18:32 +0000 (7 09:18 +0200) | ||
| tree | 012c0dc378cf2409a38328fb0237daadc2737b7b | treesnapshot (tar.gz zip) |
| parent | e4b4f0b71ccbeb0157489c0904ba4957761528ff | commitdiff |
target/riscv: Add check for supported privilege mode combinations
There are 3 suggested privilege mode combinations listed in section 1.2
of the riscv-privileged spec(draft-20220717):
1) M, 2) M, U 3) M, S, U
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-Id: <20220718130955.11899-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
There are 3 suggested privilege mode combinations listed in section 1.2
of the riscv-privileged spec(draft-20220717):
1) M, 2) M, U 3) M, S, U
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-Id: <20220718130955.11899-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| target/riscv/cpu.c | diffblobblamehistory |