| commit | 0b2ff2ceb8a45cbe51ca13a1a32fc5bdeec71815 | |
| author | Victor CLEMENT <victor.clement@openwide.fr> | |
| Tue, 2 Jun 2015 13:56:23 +0000 (2 14:56 +0100) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Tue, 2 Jun 2015 13:56:25 +0000 (2 14:56 +0100) | ||
| tree | 916e23e70af189de62e8ec74e4559a32234a8202 | treesnapshot (tar.gz zip) |
| parent | bd204e63a7ce9d1b5c5903c9033863b179194989 | commitdiff |
pl061: fix wrong calculation of GPIOMIS register
The masked interrupt status register should be the state of the interrupt
after masking.
There should be a logical AND instead of a logical OR between the
interrupt status and the interrupt mask.
Signed-off-by: Victor CLEMENT <victor.clement@openwide.fr>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 1433154824-6927-1-git-send-email-victor.clement@openwide.fr
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
The masked interrupt status register should be the state of the interrupt
after masking.
There should be a logical AND instead of a logical OR between the
interrupt status and the interrupt mask.
Signed-off-by: Victor CLEMENT <victor.clement@openwide.fr>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 1433154824-6927-1-git-send-email-victor.clement@openwide.fr
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| hw/gpio/pl061.c | diffblobblamehistory |