| commit | 0631aaae31cccf5ae61e8c67c198e064bfaafc66 | |
| author | Anup Patel <anup.patel@wdc.com> | |
| Sun, 20 Feb 2022 08:55:26 +0000 (20 14:25 +0530) | ||
| committer | Alistair Francis <alistair.francis@wdc.com> | |
| Thu, 3 Mar 2022 03:14:50 +0000 (3 13:14 +1000) | ||
| tree | ec2a60aac36861b8aa015c4e68bfdeb7803e4f3d | treesnapshot (tar.gz zip) |
| parent | c65bc383edc7aa7c12afcdad3be30521b3280203 | commitdiff |
hw/riscv: virt: Increase maximum number of allowed CPUs
To facilitate software development of RISC-V systems with large number
of HARTs, we increase the maximum number of allowed CPUs to 512 (2^9).
We also add a detailed source level comments about limit defines which
impact the physical address space utilization.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-Id: <20220220085526.808674-6-anup@brainfault.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
To facilitate software development of RISC-V systems with large number
of HARTs, we increase the maximum number of allowed CPUs to 512 (2^9).
We also add a detailed source level comments about limit defines which
impact the physical address space utilization.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-Id: <20220220085526.808674-6-anup@brainfault.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| hw/riscv/virt.c | diffblobblamehistory | |
| include/hw/riscv/virt.h | diffblobblamehistory |