4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "exec/exec-all.h"
23 #include "tcg/tcg-op.h"
24 #include "tcg/tcg-op-gvec.h"
27 #include "translate.h"
28 #include "internals.h"
29 #include "qemu/host-utils.h"
31 #include "hw/semihosting/semihost.h"
32 #include "exec/gen-icount.h"
34 #include "exec/helper-proto.h"
35 #include "exec/helper-gen.h"
38 #include "trace-tcg.h"
39 #include "translate-a64.h"
40 #include "qemu/atomic128.h"
42 static TCGv_i64 cpu_X
[32];
43 static TCGv_i64 cpu_pc
;
45 /* Load/store exclusive handling */
46 static TCGv_i64 cpu_exclusive_high
;
48 static const char *regnames
[] = {
49 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
50 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
51 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
52 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
56 A64_SHIFT_TYPE_LSL
= 0,
57 A64_SHIFT_TYPE_LSR
= 1,
58 A64_SHIFT_TYPE_ASR
= 2,
59 A64_SHIFT_TYPE_ROR
= 3
62 /* Table based decoder typedefs - used when the relevant bits for decode
63 * are too awkwardly scattered across the instruction (eg SIMD).
65 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
67 typedef struct AArch64DecodeTable
{
70 AArch64DecodeFn
*disas_fn
;
73 /* Function prototype for gen_ functions for calling Neon helpers */
74 typedef void NeonGenOneOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
);
75 typedef void NeonGenTwoOpFn(TCGv_i32
, TCGv_i32
, TCGv_i32
);
76 typedef void NeonGenTwoOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
, TCGv_i32
);
77 typedef void NeonGenTwo64OpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
);
78 typedef void NeonGenTwo64OpEnvFn(TCGv_i64
, TCGv_ptr
, TCGv_i64
, TCGv_i64
);
79 typedef void NeonGenNarrowFn(TCGv_i32
, TCGv_i64
);
80 typedef void NeonGenNarrowEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i64
);
81 typedef void NeonGenWidenFn(TCGv_i64
, TCGv_i32
);
82 typedef void NeonGenTwoSingleOPFn(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
83 typedef void NeonGenTwoDoubleOPFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGv_ptr
);
84 typedef void NeonGenOneOpFn(TCGv_i64
, TCGv_i64
);
85 typedef void CryptoTwoOpFn(TCGv_ptr
, TCGv_ptr
);
86 typedef void CryptoThreeOpIntFn(TCGv_ptr
, TCGv_ptr
, TCGv_i32
);
87 typedef void CryptoThreeOpFn(TCGv_ptr
, TCGv_ptr
, TCGv_ptr
);
88 typedef void AtomicThreeOpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGArg
, MemOp
);
90 /* initialize TCG globals. */
91 void a64_translate_init(void)
95 cpu_pc
= tcg_global_mem_new_i64(cpu_env
,
96 offsetof(CPUARMState
, pc
),
98 for (i
= 0; i
< 32; i
++) {
99 cpu_X
[i
] = tcg_global_mem_new_i64(cpu_env
,
100 offsetof(CPUARMState
, xregs
[i
]),
104 cpu_exclusive_high
= tcg_global_mem_new_i64(cpu_env
,
105 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
109 * Return the core mmu_idx to use for A64 "unprivileged load/store" insns
111 static int get_a64_user_mem_index(DisasContext
*s
)
114 * If AccType_UNPRIV is not used, the insn uses AccType_NORMAL,
115 * which is the usual mmu_idx for this cpu state.
117 ARMMMUIdx useridx
= s
->mmu_idx
;
121 * We have pre-computed the condition for AccType_UNPRIV.
122 * Therefore we should never get here with a mmu_idx for
123 * which we do not know the corresponding user mmu_idx.
126 case ARMMMUIdx_E10_1
:
127 case ARMMMUIdx_E10_1_PAN
:
128 useridx
= ARMMMUIdx_E10_0
;
130 case ARMMMUIdx_E20_2
:
131 case ARMMMUIdx_E20_2_PAN
:
132 useridx
= ARMMMUIdx_E20_0
;
134 case ARMMMUIdx_SE10_1
:
135 case ARMMMUIdx_SE10_1_PAN
:
136 useridx
= ARMMMUIdx_SE10_0
;
139 g_assert_not_reached();
142 return arm_to_core_mmu_idx(useridx
);
145 static void reset_btype(DisasContext
*s
)
148 TCGv_i32 zero
= tcg_const_i32(0);
149 tcg_gen_st_i32(zero
, cpu_env
, offsetof(CPUARMState
, btype
));
150 tcg_temp_free_i32(zero
);
155 static void set_btype(DisasContext
*s
, int val
)
159 /* BTYPE is a 2-bit field, and 0 should be done with reset_btype. */
160 tcg_debug_assert(val
>= 1 && val
<= 3);
162 tcg_val
= tcg_const_i32(val
);
163 tcg_gen_st_i32(tcg_val
, cpu_env
, offsetof(CPUARMState
, btype
));
164 tcg_temp_free_i32(tcg_val
);
168 void gen_a64_set_pc_im(uint64_t val
)
170 tcg_gen_movi_i64(cpu_pc
, val
);
174 * Handle Top Byte Ignore (TBI) bits.
176 * If address tagging is enabled via the TCR TBI bits:
177 * + for EL2 and EL3 there is only one TBI bit, and if it is set
178 * then the address is zero-extended, clearing bits [63:56]
179 * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
180 * and TBI1 controls addressses with bit 55 == 1.
181 * If the appropriate TBI bit is set for the address then
182 * the address is sign-extended from bit 55 into bits [63:56]
184 * Here We have concatenated TBI{1,0} into tbi.
186 static void gen_top_byte_ignore(DisasContext
*s
, TCGv_i64 dst
,
187 TCGv_i64 src
, int tbi
)
190 /* Load unmodified address */
191 tcg_gen_mov_i64(dst
, src
);
192 } else if (!regime_has_2_ranges(s
->mmu_idx
)) {
193 /* Force tag byte to all zero */
194 tcg_gen_extract_i64(dst
, src
, 0, 56);
196 /* Sign-extend from bit 55. */
197 tcg_gen_sextract_i64(dst
, src
, 0, 56);
200 TCGv_i64 tcg_zero
= tcg_const_i64(0);
203 * The two TBI bits differ.
204 * If tbi0, then !tbi1: only use the extension if positive.
205 * if !tbi0, then tbi1: only use the extension if negative.
207 tcg_gen_movcond_i64(tbi
== 1 ? TCG_COND_GE
: TCG_COND_LT
,
208 dst
, dst
, tcg_zero
, dst
, src
);
209 tcg_temp_free_i64(tcg_zero
);
214 static void gen_a64_set_pc(DisasContext
*s
, TCGv_i64 src
)
217 * If address tagging is enabled for instructions via the TCR TBI bits,
218 * then loading an address into the PC will clear out any tag.
220 gen_top_byte_ignore(s
, cpu_pc
, src
, s
->tbii
);
224 * Return a "clean" address for ADDR according to TBID.
225 * This is always a fresh temporary, as we need to be able to
226 * increment this independently of a dirty write-back address.
228 static TCGv_i64
clean_data_tbi(DisasContext
*s
, TCGv_i64 addr
)
230 TCGv_i64 clean
= new_tmp_a64(s
);
231 gen_top_byte_ignore(s
, clean
, addr
, s
->tbid
);
235 typedef struct DisasCompare64
{
240 static void a64_test_cc(DisasCompare64
*c64
, int cc
)
244 arm_test_cc(&c32
, cc
);
246 /* Sign-extend the 32-bit value so that the GE/LT comparisons work
247 * properly. The NE/EQ comparisons are also fine with this choice. */
248 c64
->cond
= c32
.cond
;
249 c64
->value
= tcg_temp_new_i64();
250 tcg_gen_ext_i32_i64(c64
->value
, c32
.value
);
255 static void a64_free_cc(DisasCompare64
*c64
)
257 tcg_temp_free_i64(c64
->value
);
260 static void gen_exception_internal(int excp
)
262 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
264 assert(excp_is_internal(excp
));
265 gen_helper_exception_internal(cpu_env
, tcg_excp
);
266 tcg_temp_free_i32(tcg_excp
);
269 static void gen_exception_internal_insn(DisasContext
*s
, uint64_t pc
, int excp
)
271 gen_a64_set_pc_im(pc
);
272 gen_exception_internal(excp
);
273 s
->base
.is_jmp
= DISAS_NORETURN
;
276 static void gen_exception_insn(DisasContext
*s
, uint64_t pc
, int excp
,
277 uint32_t syndrome
, uint32_t target_el
)
279 gen_a64_set_pc_im(pc
);
280 gen_exception(excp
, syndrome
, target_el
);
281 s
->base
.is_jmp
= DISAS_NORETURN
;
284 static void gen_exception_bkpt_insn(DisasContext
*s
, uint32_t syndrome
)
288 gen_a64_set_pc_im(s
->pc_curr
);
289 tcg_syn
= tcg_const_i32(syndrome
);
290 gen_helper_exception_bkpt_insn(cpu_env
, tcg_syn
);
291 tcg_temp_free_i32(tcg_syn
);
292 s
->base
.is_jmp
= DISAS_NORETURN
;
295 static void gen_step_complete_exception(DisasContext
*s
)
297 /* We just completed step of an insn. Move from Active-not-pending
298 * to Active-pending, and then also take the swstep exception.
299 * This corresponds to making the (IMPDEF) choice to prioritize
300 * swstep exceptions over asynchronous exceptions taken to an exception
301 * level where debug is disabled. This choice has the advantage that
302 * we do not need to maintain internal state corresponding to the
303 * ISV/EX syndrome bits between completion of the step and generation
304 * of the exception, and our syndrome information is always correct.
307 gen_swstep_exception(s
, 1, s
->is_ldex
);
308 s
->base
.is_jmp
= DISAS_NORETURN
;
311 static inline bool use_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
313 /* No direct tb linking with singlestep (either QEMU's or the ARM
314 * debug architecture kind) or deterministic io
316 if (s
->base
.singlestep_enabled
|| s
->ss_active
||
317 (tb_cflags(s
->base
.tb
) & CF_LAST_IO
)) {
321 #ifndef CONFIG_USER_ONLY
322 /* Only link tbs from inside the same guest page */
323 if ((s
->base
.tb
->pc
& TARGET_PAGE_MASK
) != (dest
& TARGET_PAGE_MASK
)) {
331 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
333 TranslationBlock
*tb
;
336 if (use_goto_tb(s
, n
, dest
)) {
338 gen_a64_set_pc_im(dest
);
339 tcg_gen_exit_tb(tb
, n
);
340 s
->base
.is_jmp
= DISAS_NORETURN
;
342 gen_a64_set_pc_im(dest
);
344 gen_step_complete_exception(s
);
345 } else if (s
->base
.singlestep_enabled
) {
346 gen_exception_internal(EXCP_DEBUG
);
348 tcg_gen_lookup_and_goto_ptr();
349 s
->base
.is_jmp
= DISAS_NORETURN
;
354 void unallocated_encoding(DisasContext
*s
)
356 /* Unallocated and reserved encodings are uncategorized */
357 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
, syn_uncategorized(),
358 default_exception_el(s
));
361 static void init_tmp_a64_array(DisasContext
*s
)
363 #ifdef CONFIG_DEBUG_TCG
364 memset(s
->tmp_a64
, 0, sizeof(s
->tmp_a64
));
366 s
->tmp_a64_count
= 0;
369 static void free_tmp_a64(DisasContext
*s
)
372 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
373 tcg_temp_free_i64(s
->tmp_a64
[i
]);
375 init_tmp_a64_array(s
);
378 TCGv_i64
new_tmp_a64(DisasContext
*s
)
380 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
381 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
384 TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
386 TCGv_i64 t
= new_tmp_a64(s
);
387 tcg_gen_movi_i64(t
, 0);
392 * Register access functions
394 * These functions are used for directly accessing a register in where
395 * changes to the final register value are likely to be made. If you
396 * need to use a register for temporary calculation (e.g. index type
397 * operations) use the read_* form.
399 * B1.2.1 Register mappings
401 * In instruction register encoding 31 can refer to ZR (zero register) or
402 * the SP (stack pointer) depending on context. In QEMU's case we map SP
403 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
404 * This is the point of the _sp forms.
406 TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
409 return new_tmp_a64_zero(s
);
415 /* register access for when 31 == SP */
416 TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
421 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
422 * representing the register contents. This TCGv is an auto-freed
423 * temporary so it need not be explicitly freed, and may be modified.
425 TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
427 TCGv_i64 v
= new_tmp_a64(s
);
430 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
432 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
435 tcg_gen_movi_i64(v
, 0);
440 TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
442 TCGv_i64 v
= new_tmp_a64(s
);
444 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
446 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
451 /* Return the offset into CPUARMState of a slice (from
452 * the least significant end) of FP register Qn (ie
454 * (Note that this is not the same mapping as for A32; see cpu.h)
456 static inline int fp_reg_offset(DisasContext
*s
, int regno
, MemOp size
)
458 return vec_reg_offset(s
, regno
, 0, size
);
461 /* Offset of the high half of the 128 bit vector Qn */
462 static inline int fp_reg_hi_offset(DisasContext
*s
, int regno
)
464 return vec_reg_offset(s
, regno
, 1, MO_64
);
467 /* Convenience accessors for reading and writing single and double
468 * FP registers. Writing clears the upper parts of the associated
469 * 128 bit vector register, as required by the architecture.
470 * Note that unlike the GP register accessors, the values returned
471 * by the read functions must be manually freed.
473 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
475 TCGv_i64 v
= tcg_temp_new_i64();
477 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
481 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
483 TCGv_i32 v
= tcg_temp_new_i32();
485 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_32
));
489 static TCGv_i32
read_fp_hreg(DisasContext
*s
, int reg
)
491 TCGv_i32 v
= tcg_temp_new_i32();
493 tcg_gen_ld16u_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_16
));
497 /* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
498 * If SVE is not enabled, then there are only 128 bits in the vector.
500 static void clear_vec_high(DisasContext
*s
, bool is_q
, int rd
)
502 unsigned ofs
= fp_reg_offset(s
, rd
, MO_64
);
503 unsigned vsz
= vec_full_reg_size(s
);
506 TCGv_i64 tcg_zero
= tcg_const_i64(0);
507 tcg_gen_st_i64(tcg_zero
, cpu_env
, ofs
+ 8);
508 tcg_temp_free_i64(tcg_zero
);
511 tcg_gen_gvec_dup8i(ofs
+ 16, vsz
- 16, vsz
- 16, 0);
515 void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
517 unsigned ofs
= fp_reg_offset(s
, reg
, MO_64
);
519 tcg_gen_st_i64(v
, cpu_env
, ofs
);
520 clear_vec_high(s
, false, reg
);
523 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
525 TCGv_i64 tmp
= tcg_temp_new_i64();
527 tcg_gen_extu_i32_i64(tmp
, v
);
528 write_fp_dreg(s
, reg
, tmp
);
529 tcg_temp_free_i64(tmp
);
532 TCGv_ptr
get_fpstatus_ptr(bool is_f16
)
534 TCGv_ptr statusptr
= tcg_temp_new_ptr();
537 /* In A64 all instructions (both FP and Neon) use the FPCR; there
538 * is no equivalent of the A32 Neon "standard FPSCR value".
539 * However half-precision operations operate under a different
540 * FZ16 flag and use vfp.fp_status_f16 instead of vfp.fp_status.
543 offset
= offsetof(CPUARMState
, vfp
.fp_status_f16
);
545 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
547 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
551 /* Expand a 2-operand AdvSIMD vector operation using an expander function. */
552 static void gen_gvec_fn2(DisasContext
*s
, bool is_q
, int rd
, int rn
,
553 GVecGen2Fn
*gvec_fn
, int vece
)
555 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
556 is_q
? 16 : 8, vec_full_reg_size(s
));
559 /* Expand a 2-operand + immediate AdvSIMD vector operation using
560 * an expander function.
562 static void gen_gvec_fn2i(DisasContext
*s
, bool is_q
, int rd
, int rn
,
563 int64_t imm
, GVecGen2iFn
*gvec_fn
, int vece
)
565 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
566 imm
, is_q
? 16 : 8, vec_full_reg_size(s
));
569 /* Expand a 3-operand AdvSIMD vector operation using an expander function. */
570 static void gen_gvec_fn3(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
571 GVecGen3Fn
*gvec_fn
, int vece
)
573 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
574 vec_full_reg_offset(s
, rm
), is_q
? 16 : 8, vec_full_reg_size(s
));
577 /* Expand a 4-operand AdvSIMD vector operation using an expander function. */
578 static void gen_gvec_fn4(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
579 int rx
, GVecGen4Fn
*gvec_fn
, int vece
)
581 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
582 vec_full_reg_offset(s
, rm
), vec_full_reg_offset(s
, rx
),
583 is_q
? 16 : 8, vec_full_reg_size(s
));
586 /* Expand a 2-operand + immediate AdvSIMD vector operation using
589 static void gen_gvec_op2i(DisasContext
*s
, bool is_q
, int rd
,
590 int rn
, int64_t imm
, const GVecGen2i
*gvec_op
)
592 tcg_gen_gvec_2i(vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
593 is_q
? 16 : 8, vec_full_reg_size(s
), imm
, gvec_op
);
596 /* Expand a 3-operand AdvSIMD vector operation using an op descriptor. */
597 static void gen_gvec_op3(DisasContext
*s
, bool is_q
, int rd
,
598 int rn
, int rm
, const GVecGen3
*gvec_op
)
600 tcg_gen_gvec_3(vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
601 vec_full_reg_offset(s
, rm
), is_q
? 16 : 8,
602 vec_full_reg_size(s
), gvec_op
);
605 /* Expand a 3-operand operation using an out-of-line helper. */
606 static void gen_gvec_op3_ool(DisasContext
*s
, bool is_q
, int rd
,
607 int rn
, int rm
, int data
, gen_helper_gvec_3
*fn
)
609 tcg_gen_gvec_3_ool(vec_full_reg_offset(s
, rd
),
610 vec_full_reg_offset(s
, rn
),
611 vec_full_reg_offset(s
, rm
),
612 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
615 /* Expand a 3-operand + env pointer operation using
616 * an out-of-line helper.
618 static void gen_gvec_op3_env(DisasContext
*s
, bool is_q
, int rd
,
619 int rn
, int rm
, gen_helper_gvec_3_ptr
*fn
)
621 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
622 vec_full_reg_offset(s
, rn
),
623 vec_full_reg_offset(s
, rm
), cpu_env
,
624 is_q
? 16 : 8, vec_full_reg_size(s
), 0, fn
);
627 /* Expand a 3-operand + fpstatus pointer + simd data value operation using
628 * an out-of-line helper.
630 static void gen_gvec_op3_fpst(DisasContext
*s
, bool is_q
, int rd
, int rn
,
631 int rm
, bool is_fp16
, int data
,
632 gen_helper_gvec_3_ptr
*fn
)
634 TCGv_ptr fpst
= get_fpstatus_ptr(is_fp16
);
635 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
636 vec_full_reg_offset(s
, rn
),
637 vec_full_reg_offset(s
, rm
), fpst
,
638 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
639 tcg_temp_free_ptr(fpst
);
642 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
643 * than the 32 bit equivalent.
645 static inline void gen_set_NZ64(TCGv_i64 result
)
647 tcg_gen_extr_i64_i32(cpu_ZF
, cpu_NF
, result
);
648 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, cpu_NF
);
651 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
652 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
655 gen_set_NZ64(result
);
657 tcg_gen_extrl_i64_i32(cpu_ZF
, result
);
658 tcg_gen_mov_i32(cpu_NF
, cpu_ZF
);
660 tcg_gen_movi_i32(cpu_CF
, 0);
661 tcg_gen_movi_i32(cpu_VF
, 0);
664 /* dest = T0 + T1; compute C, N, V and Z flags */
665 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
668 TCGv_i64 result
, flag
, tmp
;
669 result
= tcg_temp_new_i64();
670 flag
= tcg_temp_new_i64();
671 tmp
= tcg_temp_new_i64();
673 tcg_gen_movi_i64(tmp
, 0);
674 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
676 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
678 gen_set_NZ64(result
);
680 tcg_gen_xor_i64(flag
, result
, t0
);
681 tcg_gen_xor_i64(tmp
, t0
, t1
);
682 tcg_gen_andc_i64(flag
, flag
, tmp
);
683 tcg_temp_free_i64(tmp
);
684 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
686 tcg_gen_mov_i64(dest
, result
);
687 tcg_temp_free_i64(result
);
688 tcg_temp_free_i64(flag
);
690 /* 32 bit arithmetic */
691 TCGv_i32 t0_32
= tcg_temp_new_i32();
692 TCGv_i32 t1_32
= tcg_temp_new_i32();
693 TCGv_i32 tmp
= tcg_temp_new_i32();
695 tcg_gen_movi_i32(tmp
, 0);
696 tcg_gen_extrl_i64_i32(t0_32
, t0
);
697 tcg_gen_extrl_i64_i32(t1_32
, t1
);
698 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
699 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
700 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
701 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
702 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
703 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
705 tcg_temp_free_i32(tmp
);
706 tcg_temp_free_i32(t0_32
);
707 tcg_temp_free_i32(t1_32
);
711 /* dest = T0 - T1; compute C, N, V and Z flags */
712 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
715 /* 64 bit arithmetic */
716 TCGv_i64 result
, flag
, tmp
;
718 result
= tcg_temp_new_i64();
719 flag
= tcg_temp_new_i64();
720 tcg_gen_sub_i64(result
, t0
, t1
);
722 gen_set_NZ64(result
);
724 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
725 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
727 tcg_gen_xor_i64(flag
, result
, t0
);
728 tmp
= tcg_temp_new_i64();
729 tcg_gen_xor_i64(tmp
, t0
, t1
);
730 tcg_gen_and_i64(flag
, flag
, tmp
);
731 tcg_temp_free_i64(tmp
);
732 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
733 tcg_gen_mov_i64(dest
, result
);
734 tcg_temp_free_i64(flag
);
735 tcg_temp_free_i64(result
);
737 /* 32 bit arithmetic */
738 TCGv_i32 t0_32
= tcg_temp_new_i32();
739 TCGv_i32 t1_32
= tcg_temp_new_i32();
742 tcg_gen_extrl_i64_i32(t0_32
, t0
);
743 tcg_gen_extrl_i64_i32(t1_32
, t1
);
744 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
745 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
746 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
747 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
748 tmp
= tcg_temp_new_i32();
749 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
750 tcg_temp_free_i32(t0_32
);
751 tcg_temp_free_i32(t1_32
);
752 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
753 tcg_temp_free_i32(tmp
);
754 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
758 /* dest = T0 + T1 + CF; do not compute flags. */
759 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
761 TCGv_i64 flag
= tcg_temp_new_i64();
762 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
763 tcg_gen_add_i64(dest
, t0
, t1
);
764 tcg_gen_add_i64(dest
, dest
, flag
);
765 tcg_temp_free_i64(flag
);
768 tcg_gen_ext32u_i64(dest
, dest
);
772 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
773 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
776 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
777 result
= tcg_temp_new_i64();
778 cf_64
= tcg_temp_new_i64();
779 vf_64
= tcg_temp_new_i64();
780 tmp
= tcg_const_i64(0);
782 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
783 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
784 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
785 tcg_gen_extrl_i64_i32(cpu_CF
, cf_64
);
786 gen_set_NZ64(result
);
788 tcg_gen_xor_i64(vf_64
, result
, t0
);
789 tcg_gen_xor_i64(tmp
, t0
, t1
);
790 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
791 tcg_gen_extrh_i64_i32(cpu_VF
, vf_64
);
793 tcg_gen_mov_i64(dest
, result
);
795 tcg_temp_free_i64(tmp
);
796 tcg_temp_free_i64(vf_64
);
797 tcg_temp_free_i64(cf_64
);
798 tcg_temp_free_i64(result
);
800 TCGv_i32 t0_32
, t1_32
, tmp
;
801 t0_32
= tcg_temp_new_i32();
802 t1_32
= tcg_temp_new_i32();
803 tmp
= tcg_const_i32(0);
805 tcg_gen_extrl_i64_i32(t0_32
, t0
);
806 tcg_gen_extrl_i64_i32(t1_32
, t1
);
807 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
808 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
810 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
811 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
812 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
813 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
814 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
816 tcg_temp_free_i32(tmp
);
817 tcg_temp_free_i32(t1_32
);
818 tcg_temp_free_i32(t0_32
);
823 * Load/Store generators
827 * Store from GPR register to memory.
829 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
830 TCGv_i64 tcg_addr
, int size
, int memidx
,
832 unsigned int iss_srt
,
833 bool iss_sf
, bool iss_ar
)
836 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, s
->be_data
+ size
);
841 syn
= syn_data_abort_with_iss(0,
847 0, 0, 0, 0, 0, false);
848 disas_set_insn_syndrome(s
, syn
);
852 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
853 TCGv_i64 tcg_addr
, int size
,
855 unsigned int iss_srt
,
856 bool iss_sf
, bool iss_ar
)
858 do_gpr_st_memidx(s
, source
, tcg_addr
, size
, get_mem_index(s
),
859 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
863 * Load from memory to GPR register
865 static void do_gpr_ld_memidx(DisasContext
*s
,
866 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
867 int size
, bool is_signed
,
868 bool extend
, int memidx
,
869 bool iss_valid
, unsigned int iss_srt
,
870 bool iss_sf
, bool iss_ar
)
872 MemOp memop
= s
->be_data
+ size
;
880 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
882 if (extend
&& is_signed
) {
884 tcg_gen_ext32u_i64(dest
, dest
);
890 syn
= syn_data_abort_with_iss(0,
896 0, 0, 0, 0, 0, false);
897 disas_set_insn_syndrome(s
, syn
);
901 static void do_gpr_ld(DisasContext
*s
,
902 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
903 int size
, bool is_signed
, bool extend
,
904 bool iss_valid
, unsigned int iss_srt
,
905 bool iss_sf
, bool iss_ar
)
907 do_gpr_ld_memidx(s
, dest
, tcg_addr
, size
, is_signed
, extend
,
909 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
913 * Store from FP register to memory
915 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
917 /* This writes the bottom N bits of a 128 bit wide vector to memory */
918 TCGv_i64 tmp
= tcg_temp_new_i64();
919 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_offset(s
, srcidx
, MO_64
));
921 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
),
924 bool be
= s
->be_data
== MO_BE
;
925 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
927 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
928 tcg_gen_qemu_st_i64(tmp
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
930 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, srcidx
));
931 tcg_gen_qemu_st_i64(tmp
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
933 tcg_temp_free_i64(tcg_hiaddr
);
936 tcg_temp_free_i64(tmp
);
940 * Load from memory to FP register
942 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
944 /* This always zero-extends and writes to a full 128 bit wide vector */
945 TCGv_i64 tmplo
= tcg_temp_new_i64();
949 MemOp memop
= s
->be_data
+ size
;
950 tmphi
= tcg_const_i64(0);
951 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), memop
);
953 bool be
= s
->be_data
== MO_BE
;
956 tmphi
= tcg_temp_new_i64();
957 tcg_hiaddr
= tcg_temp_new_i64();
959 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
960 tcg_gen_qemu_ld_i64(tmplo
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
962 tcg_gen_qemu_ld_i64(tmphi
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
964 tcg_temp_free_i64(tcg_hiaddr
);
967 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(s
, destidx
, MO_64
));
968 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, destidx
));
970 tcg_temp_free_i64(tmplo
);
971 tcg_temp_free_i64(tmphi
);
973 clear_vec_high(s
, true, destidx
);
977 * Vector load/store helpers.
979 * The principal difference between this and a FP load is that we don't
980 * zero extend as we are filling a partial chunk of the vector register.
981 * These functions don't support 128 bit loads/stores, which would be
982 * normal load/store operations.
984 * The _i32 versions are useful when operating on 32 bit quantities
985 * (eg for floating point single or using Neon helper functions).
988 /* Get value of an element within a vector register */
989 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
990 int element
, MemOp memop
)
992 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
995 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
998 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
1001 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
1004 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
1007 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
1010 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
1014 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
1017 g_assert_not_reached();
1021 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
1022 int element
, MemOp memop
)
1024 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1027 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
1030 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
1033 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
1036 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
1040 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
1043 g_assert_not_reached();
1047 /* Set value of an element within a vector register */
1048 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
1049 int element
, MemOp memop
)
1051 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1054 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
1057 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
1060 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
1063 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
1066 g_assert_not_reached();
1070 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
1071 int destidx
, int element
, MemOp memop
)
1073 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1076 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
1079 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
1082 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
1085 g_assert_not_reached();
1089 /* Store from vector register to memory */
1090 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
1091 TCGv_i64 tcg_addr
, int size
, MemOp endian
)
1093 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1095 read_vec_element(s
, tcg_tmp
, srcidx
, element
, size
);
1096 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), endian
| size
);
1098 tcg_temp_free_i64(tcg_tmp
);
1101 /* Load from memory to vector register */
1102 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
1103 TCGv_i64 tcg_addr
, int size
, MemOp endian
)
1105 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1107 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), endian
| size
);
1108 write_vec_element(s
, tcg_tmp
, destidx
, element
, size
);
1110 tcg_temp_free_i64(tcg_tmp
);
1113 /* Check that FP/Neon access is enabled. If it is, return
1114 * true. If not, emit code to generate an appropriate exception,
1115 * and return false; the caller should not emit any code for
1116 * the instruction. Note that this check must happen after all
1117 * unallocated-encoding checks (otherwise the syndrome information
1118 * for the resulting exception will be incorrect).
1120 static inline bool fp_access_check(DisasContext
*s
)
1122 assert(!s
->fp_access_checked
);
1123 s
->fp_access_checked
= true;
1125 if (!s
->fp_excp_el
) {
1129 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
,
1130 syn_fp_access_trap(1, 0xe, false), s
->fp_excp_el
);
1134 /* Check that SVE access is enabled. If it is, return true.
1135 * If not, emit code to generate an appropriate exception and return false.
1137 bool sve_access_check(DisasContext
*s
)
1139 if (s
->sve_excp_el
) {
1140 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
, syn_sve_access_trap(),
1144 return fp_access_check(s
);
1148 * This utility function is for doing register extension with an
1149 * optional shift. You will likely want to pass a temporary for the
1150 * destination register. See DecodeRegExtend() in the ARM ARM.
1152 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
1153 int option
, unsigned int shift
)
1155 int extsize
= extract32(option
, 0, 2);
1156 bool is_signed
= extract32(option
, 2, 1);
1161 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
1164 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
1167 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
1170 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1176 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
1179 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
1182 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
1185 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1191 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
1195 static inline void gen_check_sp_alignment(DisasContext
*s
)
1197 /* The AArch64 architecture mandates that (if enabled via PSTATE
1198 * or SCTLR bits) there is a check that SP is 16-aligned on every
1199 * SP-relative load or store (with an exception generated if it is not).
1200 * In line with general QEMU practice regarding misaligned accesses,
1201 * we omit these checks for the sake of guest program performance.
1202 * This function is provided as a hook so we can more easily add these
1203 * checks in future (possibly as a "favour catching guest program bugs
1204 * over speed" user selectable option).
1209 * This provides a simple table based table lookup decoder. It is
1210 * intended to be used when the relevant bits for decode are too
1211 * awkwardly placed and switch/if based logic would be confusing and
1212 * deeply nested. Since it's a linear search through the table, tables
1213 * should be kept small.
1215 * It returns the first handler where insn & mask == pattern, or
1216 * NULL if there is no match.
1217 * The table is terminated by an empty mask (i.e. 0)
1219 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
1222 const AArch64DecodeTable
*tptr
= table
;
1224 while (tptr
->mask
) {
1225 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
1226 return tptr
->disas_fn
;
1234 * The instruction disassembly implemented here matches
1235 * the instruction encoding classifications in chapter C4
1236 * of the ARM Architecture Reference Manual (DDI0487B_a);
1237 * classification names and decode diagrams here should generally
1238 * match up with those in the manual.
1241 /* Unconditional branch (immediate)
1243 * +----+-----------+-------------------------------------+
1244 * | op | 0 0 1 0 1 | imm26 |
1245 * +----+-----------+-------------------------------------+
1247 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
1249 uint64_t addr
= s
->pc_curr
+ sextract32(insn
, 0, 26) * 4;
1251 if (insn
& (1U << 31)) {
1252 /* BL Branch with link */
1253 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->base
.pc_next
);
1256 /* B Branch / BL Branch with link */
1258 gen_goto_tb(s
, 0, addr
);
1261 /* Compare and branch (immediate)
1262 * 31 30 25 24 23 5 4 0
1263 * +----+-------------+----+---------------------+--------+
1264 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1265 * +----+-------------+----+---------------------+--------+
1267 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
1269 unsigned int sf
, op
, rt
;
1271 TCGLabel
*label_match
;
1274 sf
= extract32(insn
, 31, 1);
1275 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
1276 rt
= extract32(insn
, 0, 5);
1277 addr
= s
->pc_curr
+ sextract32(insn
, 5, 19) * 4;
1279 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
1280 label_match
= gen_new_label();
1283 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1284 tcg_cmp
, 0, label_match
);
1286 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1287 gen_set_label(label_match
);
1288 gen_goto_tb(s
, 1, addr
);
1291 /* Test and branch (immediate)
1292 * 31 30 25 24 23 19 18 5 4 0
1293 * +----+-------------+----+-------+-------------+------+
1294 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1295 * +----+-------------+----+-------+-------------+------+
1297 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1299 unsigned int bit_pos
, op
, rt
;
1301 TCGLabel
*label_match
;
1304 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1305 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1306 addr
= s
->pc_curr
+ sextract32(insn
, 5, 14) * 4;
1307 rt
= extract32(insn
, 0, 5);
1309 tcg_cmp
= tcg_temp_new_i64();
1310 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1311 label_match
= gen_new_label();
1314 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1315 tcg_cmp
, 0, label_match
);
1316 tcg_temp_free_i64(tcg_cmp
);
1317 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1318 gen_set_label(label_match
);
1319 gen_goto_tb(s
, 1, addr
);
1322 /* Conditional branch (immediate)
1323 * 31 25 24 23 5 4 3 0
1324 * +---------------+----+---------------------+----+------+
1325 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1326 * +---------------+----+---------------------+----+------+
1328 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1333 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1334 unallocated_encoding(s
);
1337 addr
= s
->pc_curr
+ sextract32(insn
, 5, 19) * 4;
1338 cond
= extract32(insn
, 0, 4);
1342 /* genuinely conditional branches */
1343 TCGLabel
*label_match
= gen_new_label();
1344 arm_gen_test_cc(cond
, label_match
);
1345 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1346 gen_set_label(label_match
);
1347 gen_goto_tb(s
, 1, addr
);
1349 /* 0xe and 0xf are both "always" conditions */
1350 gen_goto_tb(s
, 0, addr
);
1354 /* HINT instruction group, including various allocated HINTs */
1355 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1356 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1358 unsigned int selector
= crm
<< 3 | op2
;
1361 unallocated_encoding(s
);
1366 case 0b00000: /* NOP */
1368 case 0b00011: /* WFI */
1369 s
->base
.is_jmp
= DISAS_WFI
;
1371 case 0b00001: /* YIELD */
1372 /* When running in MTTCG we don't generate jumps to the yield and
1373 * WFE helpers as it won't affect the scheduling of other vCPUs.
1374 * If we wanted to more completely model WFE/SEV so we don't busy
1375 * spin unnecessarily we would need to do something more involved.
1377 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1378 s
->base
.is_jmp
= DISAS_YIELD
;
1381 case 0b00010: /* WFE */
1382 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1383 s
->base
.is_jmp
= DISAS_WFE
;
1386 case 0b00100: /* SEV */
1387 case 0b00101: /* SEVL */
1388 /* we treat all as NOP at least for now */
1390 case 0b00111: /* XPACLRI */
1391 if (s
->pauth_active
) {
1392 gen_helper_xpaci(cpu_X
[30], cpu_env
, cpu_X
[30]);
1395 case 0b01000: /* PACIA1716 */
1396 if (s
->pauth_active
) {
1397 gen_helper_pacia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1400 case 0b01010: /* PACIB1716 */
1401 if (s
->pauth_active
) {
1402 gen_helper_pacib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1405 case 0b01100: /* AUTIA1716 */
1406 if (s
->pauth_active
) {
1407 gen_helper_autia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1410 case 0b01110: /* AUTIB1716 */
1411 if (s
->pauth_active
) {
1412 gen_helper_autib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1415 case 0b11000: /* PACIAZ */
1416 if (s
->pauth_active
) {
1417 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30],
1418 new_tmp_a64_zero(s
));
1421 case 0b11001: /* PACIASP */
1422 if (s
->pauth_active
) {
1423 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1426 case 0b11010: /* PACIBZ */
1427 if (s
->pauth_active
) {
1428 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30],
1429 new_tmp_a64_zero(s
));
1432 case 0b11011: /* PACIBSP */
1433 if (s
->pauth_active
) {
1434 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1437 case 0b11100: /* AUTIAZ */
1438 if (s
->pauth_active
) {
1439 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30],
1440 new_tmp_a64_zero(s
));
1443 case 0b11101: /* AUTIASP */
1444 if (s
->pauth_active
) {
1445 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1448 case 0b11110: /* AUTIBZ */
1449 if (s
->pauth_active
) {
1450 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30],
1451 new_tmp_a64_zero(s
));
1454 case 0b11111: /* AUTIBSP */
1455 if (s
->pauth_active
) {
1456 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1460 /* default specified as NOP equivalent */
1465 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1467 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1470 /* CLREX, DSB, DMB, ISB */
1471 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1472 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1477 unallocated_encoding(s
);
1488 case 1: /* MBReqTypes_Reads */
1489 bar
= TCG_BAR_SC
| TCG_MO_LD_LD
| TCG_MO_LD_ST
;
1491 case 2: /* MBReqTypes_Writes */
1492 bar
= TCG_BAR_SC
| TCG_MO_ST_ST
;
1494 default: /* MBReqTypes_All */
1495 bar
= TCG_BAR_SC
| TCG_MO_ALL
;
1501 /* We need to break the TB after this insn to execute
1502 * a self-modified code correctly and also to take
1503 * any pending interrupts immediately.
1506 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1510 if (crm
!= 0 || !dc_isar_feature(aa64_sb
, s
)) {
1511 goto do_unallocated
;
1514 * TODO: There is no speculation barrier opcode for TCG;
1515 * MB and end the TB instead.
1517 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
1518 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1523 unallocated_encoding(s
);
1528 static void gen_xaflag(void)
1530 TCGv_i32 z
= tcg_temp_new_i32();
1532 tcg_gen_setcondi_i32(TCG_COND_EQ
, z
, cpu_ZF
, 0);
1541 tcg_gen_or_i32(cpu_NF
, cpu_CF
, z
);
1542 tcg_gen_subi_i32(cpu_NF
, cpu_NF
, 1);
1545 tcg_gen_and_i32(cpu_ZF
, z
, cpu_CF
);
1546 tcg_gen_xori_i32(cpu_ZF
, cpu_ZF
, 1);
1548 /* (!C & Z) << 31 -> -(Z & ~C) */
1549 tcg_gen_andc_i32(cpu_VF
, z
, cpu_CF
);
1550 tcg_gen_neg_i32(cpu_VF
, cpu_VF
);
1553 tcg_gen_or_i32(cpu_CF
, cpu_CF
, z
);
1555 tcg_temp_free_i32(z
);
1558 static void gen_axflag(void)
1560 tcg_gen_sari_i32(cpu_VF
, cpu_VF
, 31); /* V ? -1 : 0 */
1561 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, cpu_VF
); /* C & !V */
1563 /* !(Z | V) -> !(!ZF | V) -> ZF & !V -> ZF & ~VF */
1564 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, cpu_VF
);
1566 tcg_gen_movi_i32(cpu_NF
, 0);
1567 tcg_gen_movi_i32(cpu_VF
, 0);
1570 /* MSR (immediate) - move immediate to processor state field */
1571 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1572 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1575 int op
= op1
<< 3 | op2
;
1577 /* End the TB by default, chaining is ok. */
1578 s
->base
.is_jmp
= DISAS_TOO_MANY
;
1581 case 0x00: /* CFINV */
1582 if (crm
!= 0 || !dc_isar_feature(aa64_condm_4
, s
)) {
1583 goto do_unallocated
;
1585 tcg_gen_xori_i32(cpu_CF
, cpu_CF
, 1);
1586 s
->base
.is_jmp
= DISAS_NEXT
;
1589 case 0x01: /* XAFlag */
1590 if (crm
!= 0 || !dc_isar_feature(aa64_condm_5
, s
)) {
1591 goto do_unallocated
;
1594 s
->base
.is_jmp
= DISAS_NEXT
;
1597 case 0x02: /* AXFlag */
1598 if (crm
!= 0 || !dc_isar_feature(aa64_condm_5
, s
)) {
1599 goto do_unallocated
;
1602 s
->base
.is_jmp
= DISAS_NEXT
;
1605 case 0x03: /* UAO */
1606 if (!dc_isar_feature(aa64_uao
, s
) || s
->current_el
== 0) {
1607 goto do_unallocated
;
1610 set_pstate_bits(PSTATE_UAO
);
1612 clear_pstate_bits(PSTATE_UAO
);
1614 t1
= tcg_const_i32(s
->current_el
);
1615 gen_helper_rebuild_hflags_a64(cpu_env
, t1
);
1616 tcg_temp_free_i32(t1
);
1619 case 0x04: /* PAN */
1620 if (!dc_isar_feature(aa64_pan
, s
) || s
->current_el
== 0) {
1621 goto do_unallocated
;
1624 set_pstate_bits(PSTATE_PAN
);
1626 clear_pstate_bits(PSTATE_PAN
);
1628 t1
= tcg_const_i32(s
->current_el
);
1629 gen_helper_rebuild_hflags_a64(cpu_env
, t1
);
1630 tcg_temp_free_i32(t1
);
1633 case 0x05: /* SPSel */
1634 if (s
->current_el
== 0) {
1635 goto do_unallocated
;
1637 t1
= tcg_const_i32(crm
& PSTATE_SP
);
1638 gen_helper_msr_i_spsel(cpu_env
, t1
);
1639 tcg_temp_free_i32(t1
);
1642 case 0x1e: /* DAIFSet */
1643 t1
= tcg_const_i32(crm
);
1644 gen_helper_msr_i_daifset(cpu_env
, t1
);
1645 tcg_temp_free_i32(t1
);
1648 case 0x1f: /* DAIFClear */
1649 t1
= tcg_const_i32(crm
);
1650 gen_helper_msr_i_daifclear(cpu_env
, t1
);
1651 tcg_temp_free_i32(t1
);
1652 /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */
1653 s
->base
.is_jmp
= DISAS_UPDATE
;
1658 unallocated_encoding(s
);
1663 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1665 TCGv_i32 tmp
= tcg_temp_new_i32();
1666 TCGv_i32 nzcv
= tcg_temp_new_i32();
1668 /* build bit 31, N */
1669 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1U << 31));
1670 /* build bit 30, Z */
1671 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1672 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1673 /* build bit 29, C */
1674 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1675 /* build bit 28, V */
1676 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1677 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1678 /* generate result */
1679 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1681 tcg_temp_free_i32(nzcv
);
1682 tcg_temp_free_i32(tmp
);
1685 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1687 TCGv_i32 nzcv
= tcg_temp_new_i32();
1689 /* take NZCV from R[t] */
1690 tcg_gen_extrl_i64_i32(nzcv
, tcg_rt
);
1693 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1U << 31));
1695 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1696 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1698 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1699 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1701 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1702 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1703 tcg_temp_free_i32(nzcv
);
1706 /* MRS - move from system register
1707 * MSR (register) - move to system register
1710 * These are all essentially the same insn in 'read' and 'write'
1711 * versions, with varying op0 fields.
1713 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1714 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1715 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1717 const ARMCPRegInfo
*ri
;
1720 ri
= get_arm_cp_reginfo(s
->cp_regs
,
1721 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1722 crn
, crm
, op0
, op1
, op2
));
1725 /* Unknown register; this might be a guest error or a QEMU
1726 * unimplemented feature.
1728 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1729 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1730 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1731 unallocated_encoding(s
);
1735 /* Check access permissions */
1736 if (!cp_access_ok(s
->current_el
, ri
, isread
)) {
1737 unallocated_encoding(s
);
1742 /* Emit code to perform further access permissions checks at
1743 * runtime; this may result in an exception.
1746 TCGv_i32 tcg_syn
, tcg_isread
;
1749 gen_a64_set_pc_im(s
->pc_curr
);
1750 tmpptr
= tcg_const_ptr(ri
);
1751 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
1752 tcg_syn
= tcg_const_i32(syndrome
);
1753 tcg_isread
= tcg_const_i32(isread
);
1754 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
, tcg_isread
);
1755 tcg_temp_free_ptr(tmpptr
);
1756 tcg_temp_free_i32(tcg_syn
);
1757 tcg_temp_free_i32(tcg_isread
);
1758 } else if (ri
->type
& ARM_CP_RAISES_EXC
) {
1760 * The readfn or writefn might raise an exception;
1761 * synchronize the CPU state in case it does.
1763 gen_a64_set_pc_im(s
->pc_curr
);
1766 /* Handle special cases first */
1767 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
1771 tcg_rt
= cpu_reg(s
, rt
);
1773 gen_get_nzcv(tcg_rt
);
1775 gen_set_nzcv(tcg_rt
);
1778 case ARM_CP_CURRENTEL
:
1779 /* Reads as current EL value from pstate, which is
1780 * guaranteed to be constant by the tb flags.
1782 tcg_rt
= cpu_reg(s
, rt
);
1783 tcg_gen_movi_i64(tcg_rt
, s
->current_el
<< 2);
1786 /* Writes clear the aligned block of memory which rt points into. */
1787 tcg_rt
= cpu_reg(s
, rt
);
1788 gen_helper_dc_zva(cpu_env
, tcg_rt
);
1793 if ((ri
->type
& ARM_CP_FPU
) && !fp_access_check(s
)) {
1795 } else if ((ri
->type
& ARM_CP_SVE
) && !sve_access_check(s
)) {
1799 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1803 tcg_rt
= cpu_reg(s
, rt
);
1806 if (ri
->type
& ARM_CP_CONST
) {
1807 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1808 } else if (ri
->readfn
) {
1810 tmpptr
= tcg_const_ptr(ri
);
1811 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
1812 tcg_temp_free_ptr(tmpptr
);
1814 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1817 if (ri
->type
& ARM_CP_CONST
) {
1818 /* If not forbidden by access permissions, treat as WI */
1820 } else if (ri
->writefn
) {
1822 tmpptr
= tcg_const_ptr(ri
);
1823 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
1824 tcg_temp_free_ptr(tmpptr
);
1826 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1830 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1831 /* I/O operations must end the TB here (whether read or write) */
1832 s
->base
.is_jmp
= DISAS_UPDATE
;
1834 if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
1836 * A write to any coprocessor regiser that ends a TB
1837 * must rebuild the hflags for the next TB.
1839 TCGv_i32 tcg_el
= tcg_const_i32(s
->current_el
);
1840 gen_helper_rebuild_hflags_a64(cpu_env
, tcg_el
);
1841 tcg_temp_free_i32(tcg_el
);
1843 * We default to ending the TB on a coprocessor register write,
1844 * but allow this to be suppressed by the register definition
1845 * (usually only necessary to work around guest bugs).
1847 s
->base
.is_jmp
= DISAS_UPDATE
;
1852 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1853 * +---------------------+---+-----+-----+-------+-------+-----+------+
1854 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1855 * +---------------------+---+-----+-----+-------+-------+-----+------+
1857 static void disas_system(DisasContext
*s
, uint32_t insn
)
1859 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
1860 l
= extract32(insn
, 21, 1);
1861 op0
= extract32(insn
, 19, 2);
1862 op1
= extract32(insn
, 16, 3);
1863 crn
= extract32(insn
, 12, 4);
1864 crm
= extract32(insn
, 8, 4);
1865 op2
= extract32(insn
, 5, 3);
1866 rt
= extract32(insn
, 0, 5);
1869 if (l
|| rt
!= 31) {
1870 unallocated_encoding(s
);
1874 case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */
1875 handle_hint(s
, insn
, op1
, op2
, crm
);
1877 case 3: /* CLREX, DSB, DMB, ISB */
1878 handle_sync(s
, insn
, op1
, op2
, crm
);
1880 case 4: /* MSR (immediate) */
1881 handle_msr_i(s
, insn
, op1
, op2
, crm
);
1884 unallocated_encoding(s
);
1889 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
1892 /* Exception generation
1894 * 31 24 23 21 20 5 4 2 1 0
1895 * +-----------------+-----+------------------------+-----+----+
1896 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
1897 * +-----------------------+------------------------+----------+
1899 static void disas_exc(DisasContext
*s
, uint32_t insn
)
1901 int opc
= extract32(insn
, 21, 3);
1902 int op2_ll
= extract32(insn
, 0, 5);
1903 int imm16
= extract32(insn
, 5, 16);
1908 /* For SVC, HVC and SMC we advance the single-step state
1909 * machine before taking the exception. This is architecturally
1910 * mandated, to ensure that single-stepping a system call
1911 * instruction works properly.
1916 gen_exception_insn(s
, s
->base
.pc_next
, EXCP_SWI
,
1917 syn_aa64_svc(imm16
), default_exception_el(s
));
1920 if (s
->current_el
== 0) {
1921 unallocated_encoding(s
);
1924 /* The pre HVC helper handles cases when HVC gets trapped
1925 * as an undefined insn by runtime configuration.
1927 gen_a64_set_pc_im(s
->pc_curr
);
1928 gen_helper_pre_hvc(cpu_env
);
1930 gen_exception_insn(s
, s
->base
.pc_next
, EXCP_HVC
,
1931 syn_aa64_hvc(imm16
), 2);
1934 if (s
->current_el
== 0) {
1935 unallocated_encoding(s
);
1938 gen_a64_set_pc_im(s
->pc_curr
);
1939 tmp
= tcg_const_i32(syn_aa64_smc(imm16
));
1940 gen_helper_pre_smc(cpu_env
, tmp
);
1941 tcg_temp_free_i32(tmp
);
1943 gen_exception_insn(s
, s
->base
.pc_next
, EXCP_SMC
,
1944 syn_aa64_smc(imm16
), 3);
1947 unallocated_encoding(s
);
1953 unallocated_encoding(s
);
1957 gen_exception_bkpt_insn(s
, syn_aa64_bkpt(imm16
));
1961 unallocated_encoding(s
);
1964 /* HLT. This has two purposes.
1965 * Architecturally, it is an external halting debug instruction.
1966 * Since QEMU doesn't implement external debug, we treat this as
1967 * it is required for halting debug disabled: it will UNDEF.
1968 * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
1970 if (semihosting_enabled() && imm16
== 0xf000) {
1971 #ifndef CONFIG_USER_ONLY
1972 /* In system mode, don't allow userspace access to semihosting,
1973 * to provide some semblance of security (and for consistency
1974 * with our 32-bit semihosting).
1976 if (s
->current_el
== 0) {
1977 unsupported_encoding(s
, insn
);
1981 gen_exception_internal_insn(s
, s
->pc_curr
, EXCP_SEMIHOST
);
1983 unsupported_encoding(s
, insn
);
1987 if (op2_ll
< 1 || op2_ll
> 3) {
1988 unallocated_encoding(s
);
1991 /* DCPS1, DCPS2, DCPS3 */
1992 unsupported_encoding(s
, insn
);
1995 unallocated_encoding(s
);
2000 /* Unconditional branch (register)
2001 * 31 25 24 21 20 16 15 10 9 5 4 0
2002 * +---------------+-------+-------+-------+------+-------+
2003 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
2004 * +---------------+-------+-------+-------+------+-------+
2006 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
2008 unsigned int opc
, op2
, op3
, rn
, op4
;
2009 unsigned btype_mod
= 2; /* 0: BR, 1: BLR, 2: other */
2013 opc
= extract32(insn
, 21, 4);
2014 op2
= extract32(insn
, 16, 5);
2015 op3
= extract32(insn
, 10, 6);
2016 rn
= extract32(insn
, 5, 5);
2017 op4
= extract32(insn
, 0, 5);
2020 goto do_unallocated
;
2032 goto do_unallocated
;
2034 dst
= cpu_reg(s
, rn
);
2039 if (!dc_isar_feature(aa64_pauth
, s
)) {
2040 goto do_unallocated
;
2044 if (rn
!= 0x1f || op4
!= 0x1f) {
2045 goto do_unallocated
;
2048 modifier
= cpu_X
[31];
2050 /* BRAAZ, BRABZ, BLRAAZ, BLRABZ */
2052 goto do_unallocated
;
2054 modifier
= new_tmp_a64_zero(s
);
2056 if (s
->pauth_active
) {
2057 dst
= new_tmp_a64(s
);
2059 gen_helper_autia(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2061 gen_helper_autib(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2064 dst
= cpu_reg(s
, rn
);
2069 goto do_unallocated
;
2071 gen_a64_set_pc(s
, dst
);
2072 /* BLR also needs to load return address */
2074 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->base
.pc_next
);
2080 if (!dc_isar_feature(aa64_pauth
, s
)) {
2081 goto do_unallocated
;
2083 if ((op3
& ~1) != 2) {
2084 goto do_unallocated
;
2086 btype_mod
= opc
& 1;
2087 if (s
->pauth_active
) {
2088 dst
= new_tmp_a64(s
);
2089 modifier
= cpu_reg_sp(s
, op4
);
2091 gen_helper_autia(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2093 gen_helper_autib(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2096 dst
= cpu_reg(s
, rn
);
2098 gen_a64_set_pc(s
, dst
);
2099 /* BLRAA also needs to load return address */
2101 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->base
.pc_next
);
2106 if (s
->current_el
== 0) {
2107 goto do_unallocated
;
2112 goto do_unallocated
;
2114 dst
= tcg_temp_new_i64();
2115 tcg_gen_ld_i64(dst
, cpu_env
,
2116 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
2119 case 2: /* ERETAA */
2120 case 3: /* ERETAB */
2121 if (!dc_isar_feature(aa64_pauth
, s
)) {
2122 goto do_unallocated
;
2124 if (rn
!= 0x1f || op4
!= 0x1f) {
2125 goto do_unallocated
;
2127 dst
= tcg_temp_new_i64();
2128 tcg_gen_ld_i64(dst
, cpu_env
,
2129 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
2130 if (s
->pauth_active
) {
2131 modifier
= cpu_X
[31];
2133 gen_helper_autia(dst
, cpu_env
, dst
, modifier
);
2135 gen_helper_autib(dst
, cpu_env
, dst
, modifier
);
2141 goto do_unallocated
;
2143 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
2147 gen_helper_exception_return(cpu_env
, dst
);
2148 tcg_temp_free_i64(dst
);
2149 /* Must exit loop to check un-masked IRQs */
2150 s
->base
.is_jmp
= DISAS_EXIT
;
2154 if (op3
!= 0 || op4
!= 0 || rn
!= 0x1f) {
2155 goto do_unallocated
;
2157 unsupported_encoding(s
, insn
);
2163 unallocated_encoding(s
);
2167 switch (btype_mod
) {
2169 if (dc_isar_feature(aa64_bti
, s
)) {
2170 /* BR to {x16,x17} or !guard -> 1, else 3. */
2171 set_btype(s
, rn
== 16 || rn
== 17 || !s
->guarded_page
? 1 : 3);
2176 if (dc_isar_feature(aa64_bti
, s
)) {
2177 /* BLR sets BTYPE to 2, regardless of source guarded page. */
2182 default: /* RET or none of the above. */
2183 /* BTYPE will be set to 0 by normal end-of-insn processing. */
2187 s
->base
.is_jmp
= DISAS_JUMP
;
2190 /* Branches, exception generating and system instructions */
2191 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
2193 switch (extract32(insn
, 25, 7)) {
2194 case 0x0a: case 0x0b:
2195 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
2196 disas_uncond_b_imm(s
, insn
);
2198 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
2199 disas_comp_b_imm(s
, insn
);
2201 case 0x1b: case 0x5b: /* Test & branch (immediate) */
2202 disas_test_b_imm(s
, insn
);
2204 case 0x2a: /* Conditional branch (immediate) */
2205 disas_cond_b_imm(s
, insn
);
2207 case 0x6a: /* Exception generation / System */
2208 if (insn
& (1 << 24)) {
2209 if (extract32(insn
, 22, 2) == 0) {
2210 disas_system(s
, insn
);
2212 unallocated_encoding(s
);
2218 case 0x6b: /* Unconditional branch (register) */
2219 disas_uncond_b_reg(s
, insn
);
2222 unallocated_encoding(s
);
2228 * Load/Store exclusive instructions are implemented by remembering
2229 * the value/address loaded, and seeing if these are the same
2230 * when the store is performed. This is not actually the architecturally
2231 * mandated semantics, but it works for typical guest code sequences
2232 * and avoids having to monitor regular stores.
2234 * The store exclusive uses the atomic cmpxchg primitives to avoid
2235 * races in multi-threaded linux-user and when MTTCG softmmu is
2238 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
2239 TCGv_i64 addr
, int size
, bool is_pair
)
2241 int idx
= get_mem_index(s
);
2242 MemOp memop
= s
->be_data
;
2244 g_assert(size
<= 3);
2246 g_assert(size
>= 2);
2248 /* The pair must be single-copy atomic for the doubleword. */
2249 memop
|= MO_64
| MO_ALIGN
;
2250 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2251 if (s
->be_data
== MO_LE
) {
2252 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 0, 32);
2253 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 32, 32);
2255 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 32, 32);
2256 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 0, 32);
2259 /* The pair must be single-copy atomic for *each* doubleword, not
2260 the entire quadword, however it must be quadword aligned. */
2262 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
,
2263 memop
| MO_ALIGN_16
);
2265 TCGv_i64 addr2
= tcg_temp_new_i64();
2266 tcg_gen_addi_i64(addr2
, addr
, 8);
2267 tcg_gen_qemu_ld_i64(cpu_exclusive_high
, addr2
, idx
, memop
);
2268 tcg_temp_free_i64(addr2
);
2270 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2271 tcg_gen_mov_i64(cpu_reg(s
, rt2
), cpu_exclusive_high
);
2274 memop
|= size
| MO_ALIGN
;
2275 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2276 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2278 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
2281 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
2282 TCGv_i64 addr
, int size
, int is_pair
)
2284 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
2285 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
2288 * [addr + datasize] = {Rt2};
2294 * env->exclusive_addr = -1;
2296 TCGLabel
*fail_label
= gen_new_label();
2297 TCGLabel
*done_label
= gen_new_label();
2300 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
2302 tmp
= tcg_temp_new_i64();
2305 if (s
->be_data
== MO_LE
) {
2306 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2308 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt2
), cpu_reg(s
, rt
));
2310 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
,
2311 cpu_exclusive_val
, tmp
,
2313 MO_64
| MO_ALIGN
| s
->be_data
);
2314 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2315 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2316 if (!HAVE_CMPXCHG128
) {
2317 gen_helper_exit_atomic(cpu_env
);
2318 s
->base
.is_jmp
= DISAS_NORETURN
;
2319 } else if (s
->be_data
== MO_LE
) {
2320 gen_helper_paired_cmpxchg64_le_parallel(tmp
, cpu_env
,
2325 gen_helper_paired_cmpxchg64_be_parallel(tmp
, cpu_env
,
2330 } else if (s
->be_data
== MO_LE
) {
2331 gen_helper_paired_cmpxchg64_le(tmp
, cpu_env
, cpu_exclusive_addr
,
2332 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2334 gen_helper_paired_cmpxchg64_be(tmp
, cpu_env
, cpu_exclusive_addr
,
2335 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2338 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
, cpu_exclusive_val
,
2339 cpu_reg(s
, rt
), get_mem_index(s
),
2340 size
| MO_ALIGN
| s
->be_data
);
2341 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2343 tcg_gen_mov_i64(cpu_reg(s
, rd
), tmp
);
2344 tcg_temp_free_i64(tmp
);
2345 tcg_gen_br(done_label
);
2347 gen_set_label(fail_label
);
2348 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
2349 gen_set_label(done_label
);
2350 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
2353 static void gen_compare_and_swap(DisasContext
*s
, int rs
, int rt
,
2356 TCGv_i64 tcg_rs
= cpu_reg(s
, rs
);
2357 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2358 int memidx
= get_mem_index(s
);
2359 TCGv_i64 clean_addr
;
2362 gen_check_sp_alignment(s
);
2364 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2365 tcg_gen_atomic_cmpxchg_i64(tcg_rs
, clean_addr
, tcg_rs
, tcg_rt
, memidx
,
2366 size
| MO_ALIGN
| s
->be_data
);
2369 static void gen_compare_and_swap_pair(DisasContext
*s
, int rs
, int rt
,
2372 TCGv_i64 s1
= cpu_reg(s
, rs
);
2373 TCGv_i64 s2
= cpu_reg(s
, rs
+ 1);
2374 TCGv_i64 t1
= cpu_reg(s
, rt
);
2375 TCGv_i64 t2
= cpu_reg(s
, rt
+ 1);
2376 TCGv_i64 clean_addr
;
2377 int memidx
= get_mem_index(s
);
2380 gen_check_sp_alignment(s
);
2382 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2385 TCGv_i64 cmp
= tcg_temp_new_i64();
2386 TCGv_i64 val
= tcg_temp_new_i64();
2388 if (s
->be_data
== MO_LE
) {
2389 tcg_gen_concat32_i64(val
, t1
, t2
);
2390 tcg_gen_concat32_i64(cmp
, s1
, s2
);
2392 tcg_gen_concat32_i64(val
, t2
, t1
);
2393 tcg_gen_concat32_i64(cmp
, s2
, s1
);
2396 tcg_gen_atomic_cmpxchg_i64(cmp
, clean_addr
, cmp
, val
, memidx
,
2397 MO_64
| MO_ALIGN
| s
->be_data
);
2398 tcg_temp_free_i64(val
);
2400 if (s
->be_data
== MO_LE
) {
2401 tcg_gen_extr32_i64(s1
, s2
, cmp
);
2403 tcg_gen_extr32_i64(s2
, s1
, cmp
);
2405 tcg_temp_free_i64(cmp
);
2406 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2407 if (HAVE_CMPXCHG128
) {
2408 TCGv_i32 tcg_rs
= tcg_const_i32(rs
);
2409 if (s
->be_data
== MO_LE
) {
2410 gen_helper_casp_le_parallel(cpu_env
, tcg_rs
,
2411 clean_addr
, t1
, t2
);
2413 gen_helper_casp_be_parallel(cpu_env
, tcg_rs
,
2414 clean_addr
, t1
, t2
);
2416 tcg_temp_free_i32(tcg_rs
);
2418 gen_helper_exit_atomic(cpu_env
);
2419 s
->base
.is_jmp
= DISAS_NORETURN
;
2422 TCGv_i64 d1
= tcg_temp_new_i64();
2423 TCGv_i64 d2
= tcg_temp_new_i64();
2424 TCGv_i64 a2
= tcg_temp_new_i64();
2425 TCGv_i64 c1
= tcg_temp_new_i64();
2426 TCGv_i64 c2
= tcg_temp_new_i64();
2427 TCGv_i64 zero
= tcg_const_i64(0);
2429 /* Load the two words, in memory order. */
2430 tcg_gen_qemu_ld_i64(d1
, clean_addr
, memidx
,
2431 MO_64
| MO_ALIGN_16
| s
->be_data
);
2432 tcg_gen_addi_i64(a2
, clean_addr
, 8);
2433 tcg_gen_qemu_ld_i64(d2
, a2
, memidx
, MO_64
| s
->be_data
);
2435 /* Compare the two words, also in memory order. */
2436 tcg_gen_setcond_i64(TCG_COND_EQ
, c1
, d1
, s1
);
2437 tcg_gen_setcond_i64(TCG_COND_EQ
, c2
, d2
, s2
);
2438 tcg_gen_and_i64(c2
, c2
, c1
);
2440 /* If compare equal, write back new data, else write back old data. */
2441 tcg_gen_movcond_i64(TCG_COND_NE
, c1
, c2
, zero
, t1
, d1
);
2442 tcg_gen_movcond_i64(TCG_COND_NE
, c2
, c2
, zero
, t2
, d2
);
2443 tcg_gen_qemu_st_i64(c1
, clean_addr
, memidx
, MO_64
| s
->be_data
);
2444 tcg_gen_qemu_st_i64(c2
, a2
, memidx
, MO_64
| s
->be_data
);
2445 tcg_temp_free_i64(a2
);
2446 tcg_temp_free_i64(c1
);
2447 tcg_temp_free_i64(c2
);
2448 tcg_temp_free_i64(zero
);
2450 /* Write back the data from memory to Rs. */
2451 tcg_gen_mov_i64(s1
, d1
);
2452 tcg_gen_mov_i64(s2
, d2
);
2453 tcg_temp_free_i64(d1
);
2454 tcg_temp_free_i64(d2
);
2458 /* Update the Sixty-Four bit (SF) registersize. This logic is derived
2459 * from the ARMv8 specs for LDR (Shared decode for all encodings).
2461 static bool disas_ldst_compute_iss_sf(int size
, bool is_signed
, int opc
)
2463 int opc0
= extract32(opc
, 0, 1);
2467 regsize
= opc0
? 32 : 64;
2469 regsize
= size
== 3 ? 64 : 32;
2471 return regsize
== 64;
2474 /* Load/store exclusive
2476 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
2477 * +-----+-------------+----+---+----+------+----+-------+------+------+
2478 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
2479 * +-----+-------------+----+---+----+------+----+-------+------+------+
2481 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
2482 * L: 0 -> store, 1 -> load
2483 * o2: 0 -> exclusive, 1 -> not
2484 * o1: 0 -> single register, 1 -> register pair
2485 * o0: 1 -> load-acquire/store-release, 0 -> not
2487 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
2489 int rt
= extract32(insn
, 0, 5);
2490 int rn
= extract32(insn
, 5, 5);
2491 int rt2
= extract32(insn
, 10, 5);
2492 int rs
= extract32(insn
, 16, 5);
2493 int is_lasr
= extract32(insn
, 15, 1);
2494 int o2_L_o1_o0
= extract32(insn
, 21, 3) * 2 | is_lasr
;
2495 int size
= extract32(insn
, 30, 2);
2496 TCGv_i64 clean_addr
;
2498 switch (o2_L_o1_o0
) {
2499 case 0x0: /* STXR */
2500 case 0x1: /* STLXR */
2502 gen_check_sp_alignment(s
);
2505 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2507 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2508 gen_store_exclusive(s
, rs
, rt
, rt2
, clean_addr
, size
, false);
2511 case 0x4: /* LDXR */
2512 case 0x5: /* LDAXR */
2514 gen_check_sp_alignment(s
);
2516 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2518 gen_load_exclusive(s
, rt
, rt2
, clean_addr
, size
, false);
2520 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2524 case 0x8: /* STLLR */
2525 if (!dc_isar_feature(aa64_lor
, s
)) {
2528 /* StoreLORelease is the same as Store-Release for QEMU. */
2530 case 0x9: /* STLR */
2531 /* Generate ISS for non-exclusive accesses including LASR. */
2533 gen_check_sp_alignment(s
);
2535 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2536 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2537 do_gpr_st(s
, cpu_reg(s
, rt
), clean_addr
, size
, true, rt
,
2538 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2541 case 0xc: /* LDLAR */
2542 if (!dc_isar_feature(aa64_lor
, s
)) {
2545 /* LoadLOAcquire is the same as Load-Acquire for QEMU. */
2547 case 0xd: /* LDAR */
2548 /* Generate ISS for non-exclusive accesses including LASR. */
2550 gen_check_sp_alignment(s
);
2552 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2553 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, size
, false, false, true, rt
,
2554 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2555 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2558 case 0x2: case 0x3: /* CASP / STXP */
2559 if (size
& 2) { /* STXP / STLXP */
2561 gen_check_sp_alignment(s
);
2564 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2566 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2567 gen_store_exclusive(s
, rs
, rt
, rt2
, clean_addr
, size
, true);
2571 && ((rt
| rs
) & 1) == 0
2572 && dc_isar_feature(aa64_atomics
, s
)) {
2574 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2579 case 0x6: case 0x7: /* CASPA / LDXP */
2580 if (size
& 2) { /* LDXP / LDAXP */
2582 gen_check_sp_alignment(s
);
2584 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2586 gen_load_exclusive(s
, rt
, rt2
, clean_addr
, size
, true);
2588 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2593 && ((rt
| rs
) & 1) == 0
2594 && dc_isar_feature(aa64_atomics
, s
)) {
2595 /* CASPA / CASPAL */
2596 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2602 case 0xb: /* CASL */
2603 case 0xe: /* CASA */
2604 case 0xf: /* CASAL */
2605 if (rt2
== 31 && dc_isar_feature(aa64_atomics
, s
)) {
2606 gen_compare_and_swap(s
, rs
, rt
, rn
, size
);
2611 unallocated_encoding(s
);
2615 * Load register (literal)
2617 * 31 30 29 27 26 25 24 23 5 4 0
2618 * +-----+-------+---+-----+-------------------+-------+
2619 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
2620 * +-----+-------+---+-----+-------------------+-------+
2622 * V: 1 -> vector (simd/fp)
2623 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
2624 * 10-> 32 bit signed, 11 -> prefetch
2625 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
2627 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
2629 int rt
= extract32(insn
, 0, 5);
2630 int64_t imm
= sextract32(insn
, 5, 19) << 2;
2631 bool is_vector
= extract32(insn
, 26, 1);
2632 int opc
= extract32(insn
, 30, 2);
2633 bool is_signed
= false;
2635 TCGv_i64 tcg_rt
, clean_addr
;
2639 unallocated_encoding(s
);
2643 if (!fp_access_check(s
)) {
2648 /* PRFM (literal) : prefetch */
2651 size
= 2 + extract32(opc
, 0, 1);
2652 is_signed
= extract32(opc
, 1, 1);
2655 tcg_rt
= cpu_reg(s
, rt
);
2657 clean_addr
= tcg_const_i64(s
->pc_curr
+ imm
);
2659 do_fp_ld(s
, rt
, clean_addr
, size
);
2661 /* Only unsigned 32bit loads target 32bit registers. */
2662 bool iss_sf
= opc
!= 0;
2664 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, is_signed
, false,
2665 true, rt
, iss_sf
, false);
2667 tcg_temp_free_i64(clean_addr
);
2671 * LDNP (Load Pair - non-temporal hint)
2672 * LDP (Load Pair - non vector)
2673 * LDPSW (Load Pair Signed Word - non vector)
2674 * STNP (Store Pair - non-temporal hint)
2675 * STP (Store Pair - non vector)
2676 * LDNP (Load Pair of SIMD&FP - non-temporal hint)
2677 * LDP (Load Pair of SIMD&FP)
2678 * STNP (Store Pair of SIMD&FP - non-temporal hint)
2679 * STP (Store Pair of SIMD&FP)
2681 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
2682 * +-----+-------+---+---+-------+---+-----------------------------+
2683 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
2684 * +-----+-------+---+---+-------+---+-------+-------+------+------+
2686 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
2688 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
2689 * V: 0 -> GPR, 1 -> Vector
2690 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
2691 * 10 -> signed offset, 11 -> pre-index
2692 * L: 0 -> Store 1 -> Load
2694 * Rt, Rt2 = GPR or SIMD registers to be stored
2695 * Rn = general purpose register containing address
2696 * imm7 = signed offset (multiple of 4 or 8 depending on size)
2698 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
2700 int rt
= extract32(insn
, 0, 5);
2701 int rn
= extract32(insn
, 5, 5);
2702 int rt2
= extract32(insn
, 10, 5);
2703 uint64_t offset
= sextract64(insn
, 15, 7);
2704 int index
= extract32(insn
, 23, 2);
2705 bool is_vector
= extract32(insn
, 26, 1);
2706 bool is_load
= extract32(insn
, 22, 1);
2707 int opc
= extract32(insn
, 30, 2);
2709 bool is_signed
= false;
2710 bool postindex
= false;
2713 TCGv_i64 clean_addr
, dirty_addr
;
2718 unallocated_encoding(s
);
2725 size
= 2 + extract32(opc
, 1, 1);
2726 is_signed
= extract32(opc
, 0, 1);
2727 if (!is_load
&& is_signed
) {
2728 unallocated_encoding(s
);
2734 case 1: /* post-index */
2739 /* signed offset with "non-temporal" hint. Since we don't emulate
2740 * caches we don't care about hints to the cache system about
2741 * data access patterns, and handle this identically to plain
2745 /* There is no non-temporal-hint version of LDPSW */
2746 unallocated_encoding(s
);
2751 case 2: /* signed offset, rn not updated */
2754 case 3: /* pre-index */
2760 if (is_vector
&& !fp_access_check(s
)) {
2767 gen_check_sp_alignment(s
);
2770 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
2772 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
2774 clean_addr
= clean_data_tbi(s
, dirty_addr
);
2778 do_fp_ld(s
, rt
, clean_addr
, size
);
2780 do_fp_st(s
, rt
, clean_addr
, size
);
2782 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2784 do_fp_ld(s
, rt2
, clean_addr
, size
);
2786 do_fp_st(s
, rt2
, clean_addr
, size
);
2789 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2790 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
2793 TCGv_i64 tmp
= tcg_temp_new_i64();
2795 /* Do not modify tcg_rt before recognizing any exception
2796 * from the second load.
2798 do_gpr_ld(s
, tmp
, clean_addr
, size
, is_signed
, false,
2799 false, 0, false, false);
2800 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2801 do_gpr_ld(s
, tcg_rt2
, clean_addr
, size
, is_signed
, false,
2802 false, 0, false, false);
2804 tcg_gen_mov_i64(tcg_rt
, tmp
);
2805 tcg_temp_free_i64(tmp
);
2807 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
2808 false, 0, false, false);
2809 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2810 do_gpr_st(s
, tcg_rt2
, clean_addr
, size
,
2811 false, 0, false, false);
2817 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
2819 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), dirty_addr
);
2824 * Load/store (immediate post-indexed)
2825 * Load/store (immediate pre-indexed)
2826 * Load/store (unscaled immediate)
2828 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
2829 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2830 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
2831 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2833 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
2835 * V = 0 -> non-vector
2836 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
2837 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2839 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
,
2845 int rn
= extract32(insn
, 5, 5);
2846 int imm9
= sextract32(insn
, 12, 9);
2847 int idx
= extract32(insn
, 10, 2);
2848 bool is_signed
= false;
2849 bool is_store
= false;
2850 bool is_extended
= false;
2851 bool is_unpriv
= (idx
== 2);
2852 bool iss_valid
= !is_vector
;
2856 TCGv_i64 clean_addr
, dirty_addr
;
2859 size
|= (opc
& 2) << 1;
2860 if (size
> 4 || is_unpriv
) {
2861 unallocated_encoding(s
);
2864 is_store
= ((opc
& 1) == 0);
2865 if (!fp_access_check(s
)) {
2869 if (size
== 3 && opc
== 2) {
2870 /* PRFM - prefetch */
2872 unallocated_encoding(s
);
2877 if (opc
== 3 && size
> 1) {
2878 unallocated_encoding(s
);
2881 is_store
= (opc
== 0);
2882 is_signed
= extract32(opc
, 1, 1);
2883 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2901 g_assert_not_reached();
2905 gen_check_sp_alignment(s
);
2908 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
2910 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, imm9
);
2912 clean_addr
= clean_data_tbi(s
, dirty_addr
);
2916 do_fp_st(s
, rt
, clean_addr
, size
);
2918 do_fp_ld(s
, rt
, clean_addr
, size
);
2921 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2922 int memidx
= is_unpriv
? get_a64_user_mem_index(s
) : get_mem_index(s
);
2923 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2926 do_gpr_st_memidx(s
, tcg_rt
, clean_addr
, size
, memidx
,
2927 iss_valid
, rt
, iss_sf
, false);
2929 do_gpr_ld_memidx(s
, tcg_rt
, clean_addr
, size
,
2930 is_signed
, is_extended
, memidx
,
2931 iss_valid
, rt
, iss_sf
, false);
2936 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2938 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, imm9
);
2940 tcg_gen_mov_i64(tcg_rn
, dirty_addr
);
2945 * Load/store (register offset)
2947 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2948 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2949 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
2950 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2953 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2954 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2956 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2957 * opc<0>: 0 -> store, 1 -> load
2958 * V: 1 -> vector/simd
2959 * opt: extend encoding (see DecodeRegExtend)
2960 * S: if S=1 then scale (essentially index by sizeof(size))
2961 * Rt: register to transfer into/out of
2962 * Rn: address register or SP for base
2963 * Rm: offset register or ZR for offset
2965 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
,
2971 int rn
= extract32(insn
, 5, 5);
2972 int shift
= extract32(insn
, 12, 1);
2973 int rm
= extract32(insn
, 16, 5);
2974 int opt
= extract32(insn
, 13, 3);
2975 bool is_signed
= false;
2976 bool is_store
= false;
2977 bool is_extended
= false;
2979 TCGv_i64 tcg_rm
, clean_addr
, dirty_addr
;
2981 if (extract32(opt
, 1, 1) == 0) {
2982 unallocated_encoding(s
);
2987 size
|= (opc
& 2) << 1;
2989 unallocated_encoding(s
);
2992 is_store
= !extract32(opc
, 0, 1);
2993 if (!fp_access_check(s
)) {
2997 if (size
== 3 && opc
== 2) {
2998 /* PRFM - prefetch */
3001 if (opc
== 3 && size
> 1) {
3002 unallocated_encoding(s
);
3005 is_store
= (opc
== 0);
3006 is_signed
= extract32(opc
, 1, 1);
3007 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3011 gen_check_sp_alignment(s
);
3013 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3015 tcg_rm
= read_cpu_reg(s
, rm
, 1);
3016 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
3018 tcg_gen_add_i64(dirty_addr
, dirty_addr
, tcg_rm
);
3019 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3023 do_fp_st(s
, rt
, clean_addr
, size
);
3025 do_fp_ld(s
, rt
, clean_addr
, size
);
3028 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3029 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3031 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3032 true, rt
, iss_sf
, false);
3034 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
,
3035 is_signed
, is_extended
,
3036 true, rt
, iss_sf
, false);
3042 * Load/store (unsigned immediate)
3044 * 31 30 29 27 26 25 24 23 22 21 10 9 5
3045 * +----+-------+---+-----+-----+------------+-------+------+
3046 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
3047 * +----+-------+---+-----+-----+------------+-------+------+
3050 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
3051 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
3053 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
3054 * opc<0>: 0 -> store, 1 -> load
3055 * Rn: base address register (inc SP)
3056 * Rt: target register
3058 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
,
3064 int rn
= extract32(insn
, 5, 5);
3065 unsigned int imm12
= extract32(insn
, 10, 12);
3066 unsigned int offset
;
3068 TCGv_i64 clean_addr
, dirty_addr
;
3071 bool is_signed
= false;
3072 bool is_extended
= false;
3075 size
|= (opc
& 2) << 1;
3077 unallocated_encoding(s
);
3080 is_store
= !extract32(opc
, 0, 1);
3081 if (!fp_access_check(s
)) {
3085 if (size
== 3 && opc
== 2) {
3086 /* PRFM - prefetch */
3089 if (opc
== 3 && size
> 1) {
3090 unallocated_encoding(s
);
3093 is_store
= (opc
== 0);
3094 is_signed
= extract32(opc
, 1, 1);
3095 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3099 gen_check_sp_alignment(s
);
3101 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3102 offset
= imm12
<< size
;
3103 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3104 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3108 do_fp_st(s
, rt
, clean_addr
, size
);
3110 do_fp_ld(s
, rt
, clean_addr
, size
);
3113 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3114 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3116 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3117 true, rt
, iss_sf
, false);
3119 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, is_signed
, is_extended
,
3120 true, rt
, iss_sf
, false);
3125 /* Atomic memory operations
3127 * 31 30 27 26 24 22 21 16 15 12 10 5 0
3128 * +------+-------+---+-----+-----+---+----+----+-----+-----+----+-----+
3129 * | size | 1 1 1 | V | 0 0 | A R | 1 | Rs | o3 | opc | 0 0 | Rn | Rt |
3130 * +------+-------+---+-----+-----+--------+----+-----+-----+----+-----+
3132 * Rt: the result register
3133 * Rn: base address or SP
3134 * Rs: the source register for the operation
3135 * V: vector flag (always 0 as of v8.3)
3139 static void disas_ldst_atomic(DisasContext
*s
, uint32_t insn
,
3140 int size
, int rt
, bool is_vector
)
3142 int rs
= extract32(insn
, 16, 5);
3143 int rn
= extract32(insn
, 5, 5);
3144 int o3_opc
= extract32(insn
, 12, 4);
3145 TCGv_i64 tcg_rs
, clean_addr
;
3146 AtomicThreeOpFn
*fn
;
3148 if (is_vector
|| !dc_isar_feature(aa64_atomics
, s
)) {
3149 unallocated_encoding(s
);
3153 case 000: /* LDADD */
3154 fn
= tcg_gen_atomic_fetch_add_i64
;
3156 case 001: /* LDCLR */
3157 fn
= tcg_gen_atomic_fetch_and_i64
;
3159 case 002: /* LDEOR */
3160 fn
= tcg_gen_atomic_fetch_xor_i64
;
3162 case 003: /* LDSET */
3163 fn
= tcg_gen_atomic_fetch_or_i64
;
3165 case 004: /* LDSMAX */
3166 fn
= tcg_gen_atomic_fetch_smax_i64
;
3168 case 005: /* LDSMIN */
3169 fn
= tcg_gen_atomic_fetch_smin_i64
;
3171 case 006: /* LDUMAX */
3172 fn
= tcg_gen_atomic_fetch_umax_i64
;
3174 case 007: /* LDUMIN */
3175 fn
= tcg_gen_atomic_fetch_umin_i64
;
3178 fn
= tcg_gen_atomic_xchg_i64
;
3181 unallocated_encoding(s
);
3186 gen_check_sp_alignment(s
);
3188 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
3189 tcg_rs
= read_cpu_reg(s
, rs
, true);
3191 if (o3_opc
== 1) { /* LDCLR */
3192 tcg_gen_not_i64(tcg_rs
, tcg_rs
);
3195 /* The tcg atomic primitives are all full barriers. Therefore we
3196 * can ignore the Acquire and Release bits of this instruction.
3198 fn(cpu_reg(s
, rt
), clean_addr
, tcg_rs
, get_mem_index(s
),
3199 s
->be_data
| size
| MO_ALIGN
);
3203 * PAC memory operations
3205 * 31 30 27 26 24 22 21 12 11 10 5 0
3206 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3207 * | size | 1 1 1 | V | 0 0 | M S | 1 | imm9 | W | 1 | Rn | Rt |
3208 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3210 * Rt: the result register
3211 * Rn: base address or SP
3212 * V: vector flag (always 0 as of v8.3)
3213 * M: clear for key DA, set for key DB
3214 * W: pre-indexing flag
3217 static void disas_ldst_pac(DisasContext
*s
, uint32_t insn
,
3218 int size
, int rt
, bool is_vector
)
3220 int rn
= extract32(insn
, 5, 5);
3221 bool is_wback
= extract32(insn
, 11, 1);
3222 bool use_key_a
= !extract32(insn
, 23, 1);
3224 TCGv_i64 clean_addr
, dirty_addr
, tcg_rt
;
3226 if (size
!= 3 || is_vector
|| !dc_isar_feature(aa64_pauth
, s
)) {
3227 unallocated_encoding(s
);
3232 gen_check_sp_alignment(s
);
3234 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3236 if (s
->pauth_active
) {
3238 gen_helper_autda(dirty_addr
, cpu_env
, dirty_addr
, cpu_X
[31]);
3240 gen_helper_autdb(dirty_addr
, cpu_env
, dirty_addr
, cpu_X
[31]);
3244 /* Form the 10-bit signed, scaled offset. */
3245 offset
= (extract32(insn
, 22, 1) << 9) | extract32(insn
, 12, 9);
3246 offset
= sextract32(offset
<< size
, 0, 10 + size
);
3247 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3249 /* Note that "clean" and "dirty" here refer to TBI not PAC. */
3250 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3252 tcg_rt
= cpu_reg(s
, rt
);
3253 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, /* is_signed */ false,
3254 /* extend */ false, /* iss_valid */ !is_wback
,
3255 /* iss_srt */ rt
, /* iss_sf */ true, /* iss_ar */ false);
3258 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), dirty_addr
);
3262 /* Load/store register (all forms) */
3263 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
3265 int rt
= extract32(insn
, 0, 5);
3266 int opc
= extract32(insn
, 22, 2);
3267 bool is_vector
= extract32(insn
, 26, 1);
3268 int size
= extract32(insn
, 30, 2);
3270 switch (extract32(insn
, 24, 2)) {
3272 if (extract32(insn
, 21, 1) == 0) {
3273 /* Load/store register (unscaled immediate)
3274 * Load/store immediate pre/post-indexed
3275 * Load/store register unprivileged
3277 disas_ldst_reg_imm9(s
, insn
, opc
, size
, rt
, is_vector
);
3280 switch (extract32(insn
, 10, 2)) {
3282 disas_ldst_atomic(s
, insn
, size
, rt
, is_vector
);
3285 disas_ldst_reg_roffset(s
, insn
, opc
, size
, rt
, is_vector
);
3288 disas_ldst_pac(s
, insn
, size
, rt
, is_vector
);
3293 disas_ldst_reg_unsigned_imm(s
, insn
, opc
, size
, rt
, is_vector
);
3296 unallocated_encoding(s
);
3299 /* AdvSIMD load/store multiple structures
3301 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
3302 * +---+---+---------------+---+-------------+--------+------+------+------+
3303 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
3304 * +---+---+---------------+---+-------------+--------+------+------+------+
3306 * AdvSIMD load/store multiple structures (post-indexed)
3308 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
3309 * +---+---+---------------+---+---+---------+--------+------+------+------+
3310 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
3311 * +---+---+---------------+---+---+---------+--------+------+------+------+
3313 * Rt: first (or only) SIMD&FP register to be transferred
3314 * Rn: base address or SP
3315 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3317 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
3319 int rt
= extract32(insn
, 0, 5);
3320 int rn
= extract32(insn
, 5, 5);
3321 int rm
= extract32(insn
, 16, 5);
3322 int size
= extract32(insn
, 10, 2);
3323 int opcode
= extract32(insn
, 12, 4);
3324 bool is_store
= !extract32(insn
, 22, 1);
3325 bool is_postidx
= extract32(insn
, 23, 1);
3326 bool is_q
= extract32(insn
, 30, 1);
3327 TCGv_i64 clean_addr
, tcg_rn
, tcg_ebytes
;
3328 MemOp endian
= s
->be_data
;
3330 int ebytes
; /* bytes per element */
3331 int elements
; /* elements per vector */
3332 int rpt
; /* num iterations */
3333 int selem
; /* structure elements */
3336 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
3337 unallocated_encoding(s
);
3341 if (!is_postidx
&& rm
!= 0) {
3342 unallocated_encoding(s
);
3346 /* From the shared decode logic */
3377 unallocated_encoding(s
);
3381 if (size
== 3 && !is_q
&& selem
!= 1) {
3383 unallocated_encoding(s
);
3387 if (!fp_access_check(s
)) {
3392 gen_check_sp_alignment(s
);
3395 /* For our purposes, bytes are always little-endian. */
3400 /* Consecutive little-endian elements from a single register
3401 * can be promoted to a larger little-endian operation.
3403 if (selem
== 1 && endian
== MO_LE
) {
3407 elements
= (is_q
? 16 : 8) / ebytes
;
3409 tcg_rn
= cpu_reg_sp(s
, rn
);
3410 clean_addr
= clean_data_tbi(s
, tcg_rn
);
3411 tcg_ebytes
= tcg_const_i64(ebytes
);
3413 for (r
= 0; r
< rpt
; r
++) {
3415 for (e
= 0; e
< elements
; e
++) {
3417 for (xs
= 0; xs
< selem
; xs
++) {
3418 int tt
= (rt
+ r
+ xs
) % 32;
3420 do_vec_st(s
, tt
, e
, clean_addr
, size
, endian
);
3422 do_vec_ld(s
, tt
, e
, clean_addr
, size
, endian
);
3424 tcg_gen_add_i64(clean_addr
, clean_addr
, tcg_ebytes
);
3428 tcg_temp_free_i64(tcg_ebytes
);
3431 /* For non-quad operations, setting a slice of the low
3432 * 64 bits of the register clears the high 64 bits (in
3433 * the ARM ARM pseudocode this is implicit in the fact
3434 * that 'rval' is a 64 bit wide variable).
3435 * For quad operations, we might still need to zero the
3438 for (r
= 0; r
< rpt
* selem
; r
++) {
3439 int tt
= (rt
+ r
) % 32;
3440 clear_vec_high(s
, is_q
, tt
);
3446 tcg_gen_addi_i64(tcg_rn
, tcg_rn
, rpt
* elements
* selem
* ebytes
);
3448 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3453 /* AdvSIMD load/store single structure
3455 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3456 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3457 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
3458 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3460 * AdvSIMD load/store single structure (post-indexed)
3462 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3463 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3464 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
3465 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3467 * Rt: first (or only) SIMD&FP register to be transferred
3468 * Rn: base address or SP
3469 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3470 * index = encoded in Q:S:size dependent on size
3472 * lane_size = encoded in R, opc
3473 * transfer width = encoded in opc, S, size
3475 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
3477 int rt
= extract32(insn
, 0, 5);
3478 int rn
= extract32(insn
, 5, 5);
3479 int rm
= extract32(insn
, 16, 5);
3480 int size
= extract32(insn
, 10, 2);
3481 int S
= extract32(insn
, 12, 1);
3482 int opc
= extract32(insn
, 13, 3);
3483 int R
= extract32(insn
, 21, 1);
3484 int is_load
= extract32(insn
, 22, 1);
3485 int is_postidx
= extract32(insn
, 23, 1);
3486 int is_q
= extract32(insn
, 30, 1);
3488 int scale
= extract32(opc
, 1, 2);
3489 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
3490 bool replicate
= false;
3491 int index
= is_q
<< 3 | S
<< 2 | size
;
3493 TCGv_i64 clean_addr
, tcg_rn
, tcg_ebytes
;
3495 if (extract32(insn
, 31, 1)) {
3496 unallocated_encoding(s
);
3499 if (!is_postidx
&& rm
!= 0) {
3500 unallocated_encoding(s
);
3506 if (!is_load
|| S
) {
3507 unallocated_encoding(s
);
3516 if (extract32(size
, 0, 1)) {
3517 unallocated_encoding(s
);
3523 if (extract32(size
, 1, 1)) {
3524 unallocated_encoding(s
);
3527 if (!extract32(size
, 0, 1)) {
3531 unallocated_encoding(s
);
3539 g_assert_not_reached();
3542 if (!fp_access_check(s
)) {
3546 ebytes
= 1 << scale
;
3549 gen_check_sp_alignment(s
);
3552 tcg_rn
= cpu_reg_sp(s
, rn
);
3553 clean_addr
= clean_data_tbi(s
, tcg_rn
);
3554 tcg_ebytes
= tcg_const_i64(ebytes
);
3556 for (xs
= 0; xs
< selem
; xs
++) {
3558 /* Load and replicate to all elements */
3559 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3561 tcg_gen_qemu_ld_i64(tcg_tmp
, clean_addr
,
3562 get_mem_index(s
), s
->be_data
+ scale
);
3563 tcg_gen_gvec_dup_i64(scale
, vec_full_reg_offset(s
, rt
),
3564 (is_q
+ 1) * 8, vec_full_reg_size(s
),
3566 tcg_temp_free_i64(tcg_tmp
);
3568 /* Load/store one element per register */
3570 do_vec_ld(s
, rt
, index
, clean_addr
, scale
, s
->be_data
);
3572 do_vec_st(s
, rt
, index
, clean_addr
, scale
, s
->be_data
);
3575 tcg_gen_add_i64(clean_addr
, clean_addr
, tcg_ebytes
);
3578 tcg_temp_free_i64(tcg_ebytes
);
3582 tcg_gen_addi_i64(tcg_rn
, tcg_rn
, selem
* ebytes
);
3584 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3589 /* Loads and stores */
3590 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
3592 switch (extract32(insn
, 24, 6)) {
3593 case 0x08: /* Load/store exclusive */
3594 disas_ldst_excl(s
, insn
);
3596 case 0x18: case 0x1c: /* Load register (literal) */
3597 disas_ld_lit(s
, insn
);
3599 case 0x28: case 0x29:
3600 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
3601 disas_ldst_pair(s
, insn
);
3603 case 0x38: case 0x39:
3604 case 0x3c: case 0x3d: /* Load/store register (all forms) */
3605 disas_ldst_reg(s
, insn
);
3607 case 0x0c: /* AdvSIMD load/store multiple structures */
3608 disas_ldst_multiple_struct(s
, insn
);
3610 case 0x0d: /* AdvSIMD load/store single structure */
3611 disas_ldst_single_struct(s
, insn
);
3614 unallocated_encoding(s
);
3619 /* PC-rel. addressing
3620 * 31 30 29 28 24 23 5 4 0
3621 * +----+-------+-----------+-------------------+------+
3622 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
3623 * +----+-------+-----------+-------------------+------+
3625 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
3627 unsigned int page
, rd
;
3631 page
= extract32(insn
, 31, 1);
3632 /* SignExtend(immhi:immlo) -> offset */
3633 offset
= sextract64(insn
, 5, 19);
3634 offset
= offset
<< 2 | extract32(insn
, 29, 2);
3635 rd
= extract32(insn
, 0, 5);
3639 /* ADRP (page based) */
3644 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
3648 * Add/subtract (immediate)
3650 * 31 30 29 28 24 23 22 21 10 9 5 4 0
3651 * +--+--+--+-----------+-----+-------------+-----+-----+
3652 * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
3653 * +--+--+--+-----------+-----+-------------+-----+-----+
3655 * sf: 0 -> 32bit, 1 -> 64bit
3656 * op: 0 -> add , 1 -> sub
3658 * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
3660 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
3662 int rd
= extract32(insn
, 0, 5);
3663 int rn
= extract32(insn
, 5, 5);
3664 uint64_t imm
= extract32(insn
, 10, 12);
3665 int shift
= extract32(insn
, 22, 2);
3666 bool setflags
= extract32(insn
, 29, 1);
3667 bool sub_op
= extract32(insn
, 30, 1);
3668 bool is_64bit
= extract32(insn
, 31, 1);
3670 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
3671 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
3672 TCGv_i64 tcg_result
;
3681 unallocated_encoding(s
);
3685 tcg_result
= tcg_temp_new_i64();
3688 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
3690 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
3693 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
3695 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
3697 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
3699 tcg_temp_free_i64(tcg_imm
);
3703 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3705 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3708 tcg_temp_free_i64(tcg_result
);
3711 /* The input should be a value in the bottom e bits (with higher
3712 * bits zero); returns that value replicated into every element
3713 * of size e in a 64 bit integer.
3715 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
3725 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
3726 static inline uint64_t bitmask64(unsigned int length
)
3728 assert(length
> 0 && length
<= 64);
3729 return ~0ULL >> (64 - length
);
3732 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
3733 * only require the wmask. Returns false if the imms/immr/immn are a reserved
3734 * value (ie should cause a guest UNDEF exception), and true if they are
3735 * valid, in which case the decoded bit pattern is written to result.
3737 bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
3738 unsigned int imms
, unsigned int immr
)
3741 unsigned e
, levels
, s
, r
;
3744 assert(immn
< 2 && imms
< 64 && immr
< 64);
3746 /* The bit patterns we create here are 64 bit patterns which
3747 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
3748 * 64 bits each. Each element contains the same value: a run
3749 * of between 1 and e-1 non-zero bits, rotated within the
3750 * element by between 0 and e-1 bits.
3752 * The element size and run length are encoded into immn (1 bit)
3753 * and imms (6 bits) as follows:
3754 * 64 bit elements: immn = 1, imms = <length of run - 1>
3755 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
3756 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
3757 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
3758 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
3759 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
3760 * Notice that immn = 0, imms = 11111x is the only combination
3761 * not covered by one of the above options; this is reserved.
3762 * Further, <length of run - 1> all-ones is a reserved pattern.
3764 * In all cases the rotation is by immr % e (and immr is 6 bits).
3767 /* First determine the element size */
3768 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
3770 /* This is the immn == 0, imms == 0x11111x case */
3780 /* <length of run - 1> mustn't be all-ones. */
3784 /* Create the value of one element: s+1 set bits rotated
3785 * by r within the element (which is e bits wide)...
3787 mask
= bitmask64(s
+ 1);
3789 mask
= (mask
>> r
) | (mask
<< (e
- r
));
3790 mask
&= bitmask64(e
);
3792 /* ...then replicate the element over the whole 64 bit value */
3793 mask
= bitfield_replicate(mask
, e
);
3798 /* Logical (immediate)
3799 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3800 * +----+-----+-------------+---+------+------+------+------+
3801 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
3802 * +----+-----+-------------+---+------+------+------+------+
3804 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
3806 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
3807 TCGv_i64 tcg_rd
, tcg_rn
;
3809 bool is_and
= false;
3811 sf
= extract32(insn
, 31, 1);
3812 opc
= extract32(insn
, 29, 2);
3813 is_n
= extract32(insn
, 22, 1);
3814 immr
= extract32(insn
, 16, 6);
3815 imms
= extract32(insn
, 10, 6);
3816 rn
= extract32(insn
, 5, 5);
3817 rd
= extract32(insn
, 0, 5);
3820 unallocated_encoding(s
);
3824 if (opc
== 0x3) { /* ANDS */
3825 tcg_rd
= cpu_reg(s
, rd
);
3827 tcg_rd
= cpu_reg_sp(s
, rd
);
3829 tcg_rn
= cpu_reg(s
, rn
);
3831 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
3832 /* some immediate field values are reserved */
3833 unallocated_encoding(s
);
3838 wmask
&= 0xffffffff;
3842 case 0x3: /* ANDS */
3844 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
3848 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
3851 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
3854 assert(FALSE
); /* must handle all above */
3858 if (!sf
&& !is_and
) {
3859 /* zero extend final result; we know we can skip this for AND
3860 * since the immediate had the high 32 bits clear.
3862 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3865 if (opc
== 3) { /* ANDS */
3866 gen_logic_CC(sf
, tcg_rd
);
3871 * Move wide (immediate)
3873 * 31 30 29 28 23 22 21 20 5 4 0
3874 * +--+-----+-------------+-----+----------------+------+
3875 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
3876 * +--+-----+-------------+-----+----------------+------+
3878 * sf: 0 -> 32 bit, 1 -> 64 bit
3879 * opc: 00 -> N, 10 -> Z, 11 -> K
3880 * hw: shift/16 (0,16, and sf only 32, 48)
3882 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
3884 int rd
= extract32(insn
, 0, 5);
3885 uint64_t imm
= extract32(insn
, 5, 16);
3886 int sf
= extract32(insn
, 31, 1);
3887 int opc
= extract32(insn
, 29, 2);
3888 int pos
= extract32(insn
, 21, 2) << 4;
3889 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3892 if (!sf
&& (pos
>= 32)) {
3893 unallocated_encoding(s
);
3907 tcg_gen_movi_i64(tcg_rd
, imm
);
3910 tcg_imm
= tcg_const_i64(imm
);
3911 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
3912 tcg_temp_free_i64(tcg_imm
);
3914 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3918 unallocated_encoding(s
);
3924 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3925 * +----+-----+-------------+---+------+------+------+------+
3926 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
3927 * +----+-----+-------------+---+------+------+------+------+
3929 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
3931 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
3932 TCGv_i64 tcg_rd
, tcg_tmp
;
3934 sf
= extract32(insn
, 31, 1);
3935 opc
= extract32(insn
, 29, 2);
3936 n
= extract32(insn
, 22, 1);
3937 ri
= extract32(insn
, 16, 6);
3938 si
= extract32(insn
, 10, 6);
3939 rn
= extract32(insn
, 5, 5);
3940 rd
= extract32(insn
, 0, 5);
3941 bitsize
= sf
? 64 : 32;
3943 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
3944 unallocated_encoding(s
);
3948 tcg_rd
= cpu_reg(s
, rd
);
3950 /* Suppress the zero-extend for !sf. Since RI and SI are constrained
3951 to be smaller than bitsize, we'll never reference data outside the
3952 low 32-bits anyway. */
3953 tcg_tmp
= read_cpu_reg(s
, rn
, 1);
3955 /* Recognize simple(r) extractions. */
3957 /* Wd<s-r:0> = Wn<s:r> */
3958 len
= (si
- ri
) + 1;
3959 if (opc
== 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */
3960 tcg_gen_sextract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
3962 } else if (opc
== 2) { /* UBFM: UBFX, LSR, UXTB, UXTH */
3963 tcg_gen_extract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
3966 /* opc == 1, BFXIL fall through to deposit */
3967 tcg_gen_shri_i64(tcg_tmp
, tcg_tmp
, ri
);
3970 /* Handle the ri > si case with a deposit
3971 * Wd<32+s-r,32-r> = Wn<s:0>
3974 pos
= (bitsize
- ri
) & (bitsize
- 1);
3977 if (opc
== 0 && len
< ri
) {
3978 /* SBFM: sign extend the destination field from len to fill
3979 the balance of the word. Let the deposit below insert all
3980 of those sign bits. */
3981 tcg_gen_sextract_i64(tcg_tmp
, tcg_tmp
, 0, len
);
3985 if (opc
== 1) { /* BFM, BFXIL */
3986 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
3988 /* SBFM or UBFM: We start with zero, and we haven't modified
3989 any bits outside bitsize, therefore the zero-extension
3990 below is unneeded. */
3991 tcg_gen_deposit_z_i64(tcg_rd
, tcg_tmp
, pos
, len
);
3996 if (!sf
) { /* zero extend final result */
3997 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4002 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
4003 * +----+------+-------------+---+----+------+--------+------+------+
4004 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
4005 * +----+------+-------------+---+----+------+--------+------+------+
4007 static void disas_extract(DisasContext
*s
, uint32_t insn
)
4009 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
4011 sf
= extract32(insn
, 31, 1);
4012 n
= extract32(insn
, 22, 1);
4013 rm
= extract32(insn
, 16, 5);
4014 imm
= extract32(insn
, 10, 6);
4015 rn
= extract32(insn
, 5, 5);
4016 rd
= extract32(insn
, 0, 5);
4017 op21
= extract32(insn
, 29, 2);
4018 op0
= extract32(insn
, 21, 1);
4019 bitsize
= sf
? 64 : 32;
4021 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
4022 unallocated_encoding(s
);
4024 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
4026 tcg_rd
= cpu_reg(s
, rd
);
4028 if (unlikely(imm
== 0)) {
4029 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
4030 * so an extract from bit 0 is a special case.
4033 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
4035 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
4038 tcg_rm
= cpu_reg(s
, rm
);
4039 tcg_rn
= cpu_reg(s
, rn
);
4042 /* Specialization to ROR happens in EXTRACT2. */
4043 tcg_gen_extract2_i64(tcg_rd
, tcg_rm
, tcg_rn
, imm
);
4045 TCGv_i32 t0
= tcg_temp_new_i32();
4047 tcg_gen_extrl_i64_i32(t0
, tcg_rm
);
4049 tcg_gen_rotri_i32(t0
, t0
, imm
);
4051 TCGv_i32 t1
= tcg_temp_new_i32();
4052 tcg_gen_extrl_i64_i32(t1
, tcg_rn
);
4053 tcg_gen_extract2_i32(t0
, t0
, t1
, imm
);
4054 tcg_temp_free_i32(t1
);
4056 tcg_gen_extu_i32_i64(tcg_rd
, t0
);
4057 tcg_temp_free_i32(t0
);
4063 /* Data processing - immediate */
4064 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
4066 switch (extract32(insn
, 23, 6)) {
4067 case 0x20: case 0x21: /* PC-rel. addressing */
4068 disas_pc_rel_adr(s
, insn
);
4070 case 0x22: case 0x23: /* Add/subtract (immediate) */
4071 disas_add_sub_imm(s
, insn
);
4073 case 0x24: /* Logical (immediate) */
4074 disas_logic_imm(s
, insn
);
4076 case 0x25: /* Move wide (immediate) */
4077 disas_movw_imm(s
, insn
);
4079 case 0x26: /* Bitfield */
4080 disas_bitfield(s
, insn
);
4082 case 0x27: /* Extract */
4083 disas_extract(s
, insn
);
4086 unallocated_encoding(s
);
4091 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
4092 * Note that it is the caller's responsibility to ensure that the
4093 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
4094 * mandated semantics for out of range shifts.
4096 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4097 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
4099 switch (shift_type
) {
4100 case A64_SHIFT_TYPE_LSL
:
4101 tcg_gen_shl_i64(dst
, src
, shift_amount
);
4103 case A64_SHIFT_TYPE_LSR
:
4104 tcg_gen_shr_i64(dst
, src
, shift_amount
);
4106 case A64_SHIFT_TYPE_ASR
:
4108 tcg_gen_ext32s_i64(dst
, src
);
4110 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
4112 case A64_SHIFT_TYPE_ROR
:
4114 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
4117 t0
= tcg_temp_new_i32();
4118 t1
= tcg_temp_new_i32();
4119 tcg_gen_extrl_i64_i32(t0
, src
);
4120 tcg_gen_extrl_i64_i32(t1
, shift_amount
);
4121 tcg_gen_rotr_i32(t0
, t0
, t1
);
4122 tcg_gen_extu_i32_i64(dst
, t0
);
4123 tcg_temp_free_i32(t0
);
4124 tcg_temp_free_i32(t1
);
4128 assert(FALSE
); /* all shift types should be handled */
4132 if (!sf
) { /* zero extend final result */
4133 tcg_gen_ext32u_i64(dst
, dst
);
4137 /* Shift a TCGv src by immediate, put result in dst.
4138 * The shift amount must be in range (this should always be true as the
4139 * relevant instructions will UNDEF on bad shift immediates).
4141 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4142 enum a64_shift_type shift_type
, unsigned int shift_i
)
4144 assert(shift_i
< (sf
? 64 : 32));
4147 tcg_gen_mov_i64(dst
, src
);
4149 TCGv_i64 shift_const
;
4151 shift_const
= tcg_const_i64(shift_i
);
4152 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
4153 tcg_temp_free_i64(shift_const
);
4157 /* Logical (shifted register)
4158 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4159 * +----+-----+-----------+-------+---+------+--------+------+------+
4160 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
4161 * +----+-----+-----------+-------+---+------+--------+------+------+
4163 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
4165 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
4166 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
4168 sf
= extract32(insn
, 31, 1);
4169 opc
= extract32(insn
, 29, 2);
4170 shift_type
= extract32(insn
, 22, 2);
4171 invert
= extract32(insn
, 21, 1);
4172 rm
= extract32(insn
, 16, 5);
4173 shift_amount
= extract32(insn
, 10, 6);
4174 rn
= extract32(insn
, 5, 5);
4175 rd
= extract32(insn
, 0, 5);
4177 if (!sf
&& (shift_amount
& (1 << 5))) {
4178 unallocated_encoding(s
);
4182 tcg_rd
= cpu_reg(s
, rd
);
4184 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
4185 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
4186 * register-register MOV and MVN, so it is worth special casing.
4188 tcg_rm
= cpu_reg(s
, rm
);
4190 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
4192 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4196 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
4198 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
4204 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4207 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
4210 tcg_rn
= cpu_reg(s
, rn
);
4212 switch (opc
| (invert
<< 2)) {
4215 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4218 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4221 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4225 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4228 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4231 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4239 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4243 gen_logic_CC(sf
, tcg_rd
);
4248 * Add/subtract (extended register)
4250 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
4251 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4252 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
4253 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4255 * sf: 0 -> 32bit, 1 -> 64bit
4256 * op: 0 -> add , 1 -> sub
4259 * option: extension type (see DecodeRegExtend)
4260 * imm3: optional shift to Rm
4262 * Rd = Rn + LSL(extend(Rm), amount)
4264 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
4266 int rd
= extract32(insn
, 0, 5);
4267 int rn
= extract32(insn
, 5, 5);
4268 int imm3
= extract32(insn
, 10, 3);
4269 int option
= extract32(insn
, 13, 3);
4270 int rm
= extract32(insn
, 16, 5);
4271 int opt
= extract32(insn
, 22, 2);
4272 bool setflags
= extract32(insn
, 29, 1);
4273 bool sub_op
= extract32(insn
, 30, 1);
4274 bool sf
= extract32(insn
, 31, 1);
4276 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
4278 TCGv_i64 tcg_result
;
4280 if (imm3
> 4 || opt
!= 0) {
4281 unallocated_encoding(s
);
4285 /* non-flag setting ops may use SP */
4287 tcg_rd
= cpu_reg_sp(s
, rd
);
4289 tcg_rd
= cpu_reg(s
, rd
);
4291 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
4293 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4294 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
4296 tcg_result
= tcg_temp_new_i64();
4300 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4302 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4306 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4308 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4313 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4315 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4318 tcg_temp_free_i64(tcg_result
);
4322 * Add/subtract (shifted register)
4324 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4325 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4326 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
4327 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4329 * sf: 0 -> 32bit, 1 -> 64bit
4330 * op: 0 -> add , 1 -> sub
4332 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
4333 * imm6: Shift amount to apply to Rm before the add/sub
4335 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
4337 int rd
= extract32(insn
, 0, 5);
4338 int rn
= extract32(insn
, 5, 5);
4339 int imm6
= extract32(insn
, 10, 6);
4340 int rm
= extract32(insn
, 16, 5);
4341 int shift_type
= extract32(insn
, 22, 2);
4342 bool setflags
= extract32(insn
, 29, 1);
4343 bool sub_op
= extract32(insn
, 30, 1);
4344 bool sf
= extract32(insn
, 31, 1);
4346 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4347 TCGv_i64 tcg_rn
, tcg_rm
;
4348 TCGv_i64 tcg_result
;
4350 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
4351 unallocated_encoding(s
);
4355 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4356 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4358 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
4360 tcg_result
= tcg_temp_new_i64();
4364 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4366 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4370 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4372 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4377 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4379 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4382 tcg_temp_free_i64(tcg_result
);
4385 /* Data-processing (3 source)
4387 * 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
4388 * +--+------+-----------+------+------+----+------+------+------+
4389 * |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
4390 * +--+------+-----------+------+------+----+------+------+------+
4392 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
4394 int rd
= extract32(insn
, 0, 5);
4395 int rn
= extract32(insn
, 5, 5);
4396 int ra
= extract32(insn
, 10, 5);
4397 int rm
= extract32(insn
, 16, 5);
4398 int op_id
= (extract32(insn
, 29, 3) << 4) |
4399 (extract32(insn
, 21, 3) << 1) |
4400 extract32(insn
, 15, 1);
4401 bool sf
= extract32(insn
, 31, 1);
4402 bool is_sub
= extract32(op_id
, 0, 1);
4403 bool is_high
= extract32(op_id
, 2, 1);
4404 bool is_signed
= false;
4409 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
4411 case 0x42: /* SMADDL */
4412 case 0x43: /* SMSUBL */
4413 case 0x44: /* SMULH */
4416 case 0x0: /* MADD (32bit) */
4417 case 0x1: /* MSUB (32bit) */
4418 case 0x40: /* MADD (64bit) */
4419 case 0x41: /* MSUB (64bit) */
4420 case 0x4a: /* UMADDL */
4421 case 0x4b: /* UMSUBL */
4422 case 0x4c: /* UMULH */
4425 unallocated_encoding(s
);
4430 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
4431 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4432 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
4433 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
4436 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
4438 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
4441 tcg_temp_free_i64(low_bits
);
4445 tcg_op1
= tcg_temp_new_i64();
4446 tcg_op2
= tcg_temp_new_i64();
4447 tcg_tmp
= tcg_temp_new_i64();
4450 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
4451 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
4454 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
4455 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
4457 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
4458 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
4462 if (ra
== 31 && !is_sub
) {
4463 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
4464 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
4466 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
4468 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
4470 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
4475 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
4478 tcg_temp_free_i64(tcg_op1
);
4479 tcg_temp_free_i64(tcg_op2
);
4480 tcg_temp_free_i64(tcg_tmp
);
4483 /* Add/subtract (with carry)
4484 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
4485 * +--+--+--+------------------------+------+-------------+------+-----+
4486 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | 0 0 0 0 0 0 | Rn | Rd |
4487 * +--+--+--+------------------------+------+-------------+------+-----+
4490 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
4492 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
4493 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
4495 sf
= extract32(insn
, 31, 1);
4496 op
= extract32(insn
, 30, 1);
4497 setflags
= extract32(insn
, 29, 1);
4498 rm
= extract32(insn
, 16, 5);
4499 rn
= extract32(insn
, 5, 5);
4500 rd
= extract32(insn
, 0, 5);
4502 tcg_rd
= cpu_reg(s
, rd
);
4503 tcg_rn
= cpu_reg(s
, rn
);
4506 tcg_y
= new_tmp_a64(s
);
4507 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
4509 tcg_y
= cpu_reg(s
, rm
);
4513 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
4515 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
4520 * Rotate right into flags
4521 * 31 30 29 21 15 10 5 4 0
4522 * +--+--+--+-----------------+--------+-----------+------+--+------+
4523 * |sf|op| S| 1 1 0 1 0 0 0 0 | imm6 | 0 0 0 0 1 | Rn |o2| mask |
4524 * +--+--+--+-----------------+--------+-----------+------+--+------+
4526 static void disas_rotate_right_into_flags(DisasContext
*s
, uint32_t insn
)
4528 int mask
= extract32(insn
, 0, 4);
4529 int o2
= extract32(insn
, 4, 1);
4530 int rn
= extract32(insn
, 5, 5);
4531 int imm6
= extract32(insn
, 15, 6);
4532 int sf_op_s
= extract32(insn
, 29, 3);
4536 if (sf_op_s
!= 5 || o2
!= 0 || !dc_isar_feature(aa64_condm_4
, s
)) {
4537 unallocated_encoding(s
);
4541 tcg_rn
= read_cpu_reg(s
, rn
, 1);
4542 tcg_gen_rotri_i64(tcg_rn
, tcg_rn
, imm6
);
4544 nzcv
= tcg_temp_new_i32();
4545 tcg_gen_extrl_i64_i32(nzcv
, tcg_rn
);
4547 if (mask
& 8) { /* N */
4548 tcg_gen_shli_i32(cpu_NF
, nzcv
, 31 - 3);
4550 if (mask
& 4) { /* Z */
4551 tcg_gen_not_i32(cpu_ZF
, nzcv
);
4552 tcg_gen_andi_i32(cpu_ZF
, cpu_ZF
, 4);
4554 if (mask
& 2) { /* C */
4555 tcg_gen_extract_i32(cpu_CF
, nzcv
, 1, 1);
4557 if (mask
& 1) { /* V */
4558 tcg_gen_shli_i32(cpu_VF
, nzcv
, 31 - 0);
4561 tcg_temp_free_i32(nzcv
);
4565 * Evaluate into flags
4566 * 31 30 29 21 15 14 10 5 4 0
4567 * +--+--+--+-----------------+---------+----+---------+------+--+------+
4568 * |sf|op| S| 1 1 0 1 0 0 0 0 | opcode2 | sz | 0 0 1 0 | Rn |o3| mask |
4569 * +--+--+--+-----------------+---------+----+---------+------+--+------+
4571 static void disas_evaluate_into_flags(DisasContext
*s
, uint32_t insn
)
4573 int o3_mask
= extract32(insn
, 0, 5);
4574 int rn
= extract32(insn
, 5, 5);
4575 int o2
= extract32(insn
, 15, 6);
4576 int sz
= extract32(insn
, 14, 1);
4577 int sf_op_s
= extract32(insn
, 29, 3);
4581 if (sf_op_s
!= 1 || o2
!= 0 || o3_mask
!= 0xd ||
4582 !dc_isar_feature(aa64_condm_4
, s
)) {
4583 unallocated_encoding(s
);
4586 shift
= sz
? 16 : 24; /* SETF16 or SETF8 */
4588 tmp
= tcg_temp_new_i32();
4589 tcg_gen_extrl_i64_i32(tmp
, cpu_reg(s
, rn
));
4590 tcg_gen_shli_i32(cpu_NF
, tmp
, shift
);
4591 tcg_gen_shli_i32(cpu_VF
, tmp
, shift
- 1);
4592 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
4593 tcg_gen_xor_i32(cpu_VF
, cpu_VF
, cpu_NF
);
4594 tcg_temp_free_i32(tmp
);
4597 /* Conditional compare (immediate / register)
4598 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
4599 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
4600 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
4601 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
4604 static void disas_cc(DisasContext
*s
, uint32_t insn
)
4606 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
4607 TCGv_i32 tcg_t0
, tcg_t1
, tcg_t2
;
4608 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
4611 if (!extract32(insn
, 29, 1)) {
4612 unallocated_encoding(s
);
4615 if (insn
& (1 << 10 | 1 << 4)) {
4616 unallocated_encoding(s
);
4619 sf
= extract32(insn
, 31, 1);
4620 op
= extract32(insn
, 30, 1);
4621 is_imm
= extract32(insn
, 11, 1);
4622 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
4623 cond
= extract32(insn
, 12, 4);
4624 rn
= extract32(insn
, 5, 5);
4625 nzcv
= extract32(insn
, 0, 4);
4627 /* Set T0 = !COND. */
4628 tcg_t0
= tcg_temp_new_i32();
4629 arm_test_cc(&c
, cond
);
4630 tcg_gen_setcondi_i32(tcg_invert_cond(c
.cond
), tcg_t0
, c
.value
, 0);
4633 /* Load the arguments for the new comparison. */
4635 tcg_y
= new_tmp_a64(s
);
4636 tcg_gen_movi_i64(tcg_y
, y
);
4638 tcg_y
= cpu_reg(s
, y
);
4640 tcg_rn
= cpu_reg(s
, rn
);
4642 /* Set the flags for the new comparison. */
4643 tcg_tmp
= tcg_temp_new_i64();
4645 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
4647 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
4649 tcg_temp_free_i64(tcg_tmp
);
4651 /* If COND was false, force the flags to #nzcv. Compute two masks
4652 * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).
4653 * For tcg hosts that support ANDC, we can make do with just T1.
4654 * In either case, allow the tcg optimizer to delete any unused mask.
4656 tcg_t1
= tcg_temp_new_i32();
4657 tcg_t2
= tcg_temp_new_i32();
4658 tcg_gen_neg_i32(tcg_t1
, tcg_t0
);
4659 tcg_gen_subi_i32(tcg_t2
, tcg_t0
, 1);
4661 if (nzcv
& 8) { /* N */
4662 tcg_gen_or_i32(cpu_NF
, cpu_NF
, tcg_t1
);
4664 if (TCG_TARGET_HAS_andc_i32
) {
4665 tcg_gen_andc_i32(cpu_NF
, cpu_NF
, tcg_t1
);
4667 tcg_gen_and_i32(cpu_NF
, cpu_NF
, tcg_t2
);
4670 if (nzcv
& 4) { /* Z */
4671 if (TCG_TARGET_HAS_andc_i32
) {
4672 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, tcg_t1
);
4674 tcg_gen_and_i32(cpu_ZF
, cpu_ZF
, tcg_t2
);
4677 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, tcg_t0
);
4679 if (nzcv
& 2) { /* C */
4680 tcg_gen_or_i32(cpu_CF
, cpu_CF
, tcg_t0
);
4682 if (TCG_TARGET_HAS_andc_i32
) {
4683 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, tcg_t1
);
4685 tcg_gen_and_i32(cpu_CF
, cpu_CF
, tcg_t2
);
4688 if (nzcv
& 1) { /* V */
4689 tcg_gen_or_i32(cpu_VF
, cpu_VF
, tcg_t1
);
4691 if (TCG_TARGET_HAS_andc_i32
) {
4692 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tcg_t1
);
4694 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tcg_t2
);
4697 tcg_temp_free_i32(tcg_t0
);
4698 tcg_temp_free_i32(tcg_t1
);
4699 tcg_temp_free_i32(tcg_t2
);
4702 /* Conditional select
4703 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
4704 * +----+----+---+-----------------+------+------+-----+------+------+
4705 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
4706 * +----+----+---+-----------------+------+------+-----+------+------+
4708 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
4710 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
4711 TCGv_i64 tcg_rd
, zero
;
4714 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
4715 /* S == 1 or op2<1> == 1 */
4716 unallocated_encoding(s
);
4719 sf
= extract32(insn
, 31, 1);
4720 else_inv
= extract32(insn
, 30, 1);
4721 rm
= extract32(insn
, 16, 5);
4722 cond
= extract32(insn
, 12, 4);
4723 else_inc
= extract32(insn
, 10, 1);
4724 rn
= extract32(insn
, 5, 5);
4725 rd
= extract32(insn
, 0, 5);
4727 tcg_rd
= cpu_reg(s
, rd
);
4729 a64_test_cc(&c
, cond
);
4730 zero
= tcg_const_i64(0);
4732 if (rn
== 31 && rm
== 31 && (else_inc
^ else_inv
)) {
4734 tcg_gen_setcond_i64(tcg_invert_cond(c
.cond
), tcg_rd
, c
.value
, zero
);
4736 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
4739 TCGv_i64 t_true
= cpu_reg(s
, rn
);
4740 TCGv_i64 t_false
= read_cpu_reg(s
, rm
, 1);
4741 if (else_inv
&& else_inc
) {
4742 tcg_gen_neg_i64(t_false
, t_false
);
4743 } else if (else_inv
) {
4744 tcg_gen_not_i64(t_false
, t_false
);
4745 } else if (else_inc
) {
4746 tcg_gen_addi_i64(t_false
, t_false
, 1);
4748 tcg_gen_movcond_i64(c
.cond
, tcg_rd
, c
.value
, zero
, t_true
, t_false
);
4751 tcg_temp_free_i64(zero
);
4755 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4759 static void handle_clz(DisasContext
*s
, unsigned int sf
,
4760 unsigned int rn
, unsigned int rd
)
4762 TCGv_i64 tcg_rd
, tcg_rn
;
4763 tcg_rd
= cpu_reg(s
, rd
);
4764 tcg_rn
= cpu_reg(s
, rn
);
4767 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
4769 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4770 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4771 tcg_gen_clzi_i32(tcg_tmp32
, tcg_tmp32
, 32);
4772 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4773 tcg_temp_free_i32(tcg_tmp32
);
4777 static void handle_cls(DisasContext
*s
, unsigned int sf
,
4778 unsigned int rn
, unsigned int rd
)
4780 TCGv_i64 tcg_rd
, tcg_rn
;
4781 tcg_rd
= cpu_reg(s
, rd
);
4782 tcg_rn
= cpu_reg(s
, rn
);
4785 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
4787 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4788 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4789 tcg_gen_clrsb_i32(tcg_tmp32
, tcg_tmp32
);
4790 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4791 tcg_temp_free_i32(tcg_tmp32
);
4795 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
4796 unsigned int rn
, unsigned int rd
)
4798 TCGv_i64 tcg_rd
, tcg_rn
;
4799 tcg_rd
= cpu_reg(s
, rd
);
4800 tcg_rn
= cpu_reg(s
, rn
);
4803 gen_helper_rbit64(tcg_rd
, tcg_rn
);
4805 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4806 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4807 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
4808 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4809 tcg_temp_free_i32(tcg_tmp32
);
4813 /* REV with sf==1, opcode==3 ("REV64") */
4814 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
4815 unsigned int rn
, unsigned int rd
)
4818 unallocated_encoding(s
);
4821 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
4824 /* REV with sf==0, opcode==2
4825 * REV32 (sf==1, opcode==2)
4827 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
4828 unsigned int rn
, unsigned int rd
)
4830 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4833 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4834 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4836 /* bswap32_i64 requires zero high word */
4837 tcg_gen_ext32u_i64(tcg_tmp
, tcg_rn
);
4838 tcg_gen_bswap32_i64(tcg_rd
, tcg_tmp
);
4839 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
4840 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
4841 tcg_gen_concat32_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4843 tcg_temp_free_i64(tcg_tmp
);
4845 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rn
));
4846 tcg_gen_bswap32_i64(tcg_rd
, tcg_rd
);
4850 /* REV16 (opcode==1) */
4851 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
4852 unsigned int rn
, unsigned int rd
)
4854 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4855 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4856 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4857 TCGv_i64 mask
= tcg_const_i64(sf
? 0x00ff00ff00ff00ffull
: 0x00ff00ff);
4859 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 8);
4860 tcg_gen_and_i64(tcg_rd
, tcg_rn
, mask
);
4861 tcg_gen_and_i64(tcg_tmp
, tcg_tmp
, mask
);
4862 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, 8);
4863 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4865 tcg_temp_free_i64(mask
);
4866 tcg_temp_free_i64(tcg_tmp
);
4869 /* Data-processing (1 source)
4870 * 31 30 29 28 21 20 16 15 10 9 5 4 0
4871 * +----+---+---+-----------------+---------+--------+------+------+
4872 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
4873 * +----+---+---+-----------------+---------+--------+------+------+
4875 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
4877 unsigned int sf
, opcode
, opcode2
, rn
, rd
;
4880 if (extract32(insn
, 29, 1)) {
4881 unallocated_encoding(s
);
4885 sf
= extract32(insn
, 31, 1);
4886 opcode
= extract32(insn
, 10, 6);
4887 opcode2
= extract32(insn
, 16, 5);
4888 rn
= extract32(insn
, 5, 5);
4889 rd
= extract32(insn
, 0, 5);
4891 #define MAP(SF, O2, O1) ((SF) | (O1 << 1) | (O2 << 7))
4893 switch (MAP(sf
, opcode2
, opcode
)) {
4894 case MAP(0, 0x00, 0x00): /* RBIT */
4895 case MAP(1, 0x00, 0x00):
4896 handle_rbit(s
, sf
, rn
, rd
);
4898 case MAP(0, 0x00, 0x01): /* REV16 */
4899 case MAP(1, 0x00, 0x01):
4900 handle_rev16(s
, sf
, rn
, rd
);
4902 case MAP(0, 0x00, 0x02): /* REV/REV32 */
4903 case MAP(1, 0x00, 0x02):
4904 handle_rev32(s
, sf
, rn
, rd
);
4906 case MAP(1, 0x00, 0x03): /* REV64 */
4907 handle_rev64(s
, sf
, rn
, rd
);
4909 case MAP(0, 0x00, 0x04): /* CLZ */
4910 case MAP(1, 0x00, 0x04):
4911 handle_clz(s
, sf
, rn
, rd
);
4913 case MAP(0, 0x00, 0x05): /* CLS */
4914 case MAP(1, 0x00, 0x05):
4915 handle_cls(s
, sf
, rn
, rd
);
4917 case MAP(1, 0x01, 0x00): /* PACIA */
4918 if (s
->pauth_active
) {
4919 tcg_rd
= cpu_reg(s
, rd
);
4920 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4921 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4922 goto do_unallocated
;
4925 case MAP(1, 0x01, 0x01): /* PACIB */
4926 if (s
->pauth_active
) {
4927 tcg_rd
= cpu_reg(s
, rd
);
4928 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4929 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4930 goto do_unallocated
;
4933 case MAP(1, 0x01, 0x02): /* PACDA */
4934 if (s
->pauth_active
) {
4935 tcg_rd
= cpu_reg(s
, rd
);
4936 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4937 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4938 goto do_unallocated
;
4941 case MAP(1, 0x01, 0x03): /* PACDB */
4942 if (s
->pauth_active
) {
4943 tcg_rd
= cpu_reg(s
, rd
);
4944 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4945 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4946 goto do_unallocated
;
4949 case MAP(1, 0x01, 0x04): /* AUTIA */
4950 if (s
->pauth_active
) {
4951 tcg_rd
= cpu_reg(s
, rd
);
4952 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4953 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4954 goto do_unallocated
;
4957 case MAP(1, 0x01, 0x05): /* AUTIB */
4958 if (s
->pauth_active
) {
4959 tcg_rd
= cpu_reg(s
, rd
);
4960 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4961 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4962 goto do_unallocated
;
4965 case MAP(1, 0x01, 0x06): /* AUTDA */
4966 if (s
->pauth_active
) {
4967 tcg_rd
= cpu_reg(s
, rd
);
4968 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4969 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4970 goto do_unallocated
;
4973 case MAP(1, 0x01, 0x07): /* AUTDB */
4974 if (s
->pauth_active
) {
4975 tcg_rd
= cpu_reg(s
, rd
);
4976 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4977 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4978 goto do_unallocated
;
4981 case MAP(1, 0x01, 0x08): /* PACIZA */
4982 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4983 goto do_unallocated
;
4984 } else if (s
->pauth_active
) {
4985 tcg_rd
= cpu_reg(s
, rd
);
4986 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4989 case MAP(1, 0x01, 0x09): /* PACIZB */
4990 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4991 goto do_unallocated
;
4992 } else if (s
->pauth_active
) {
4993 tcg_rd
= cpu_reg(s
, rd
);
4994 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4997 case MAP(1, 0x01, 0x0a): /* PACDZA */
4998 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4999 goto do_unallocated
;
5000 } else if (s
->pauth_active
) {
5001 tcg_rd
= cpu_reg(s
, rd
);
5002 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5005 case MAP(1, 0x01, 0x0b): /* PACDZB */
5006 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5007 goto do_unallocated
;
5008 } else if (s
->pauth_active
) {
5009 tcg_rd
= cpu_reg(s
, rd
);
5010 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5013 case MAP(1, 0x01, 0x0c): /* AUTIZA */
5014 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5015 goto do_unallocated
;
5016 } else if (s
->pauth_active
) {
5017 tcg_rd
= cpu_reg(s
, rd
);
5018 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5021 case MAP(1, 0x01, 0x0d): /* AUTIZB */
5022 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5023 goto do_unallocated
;
5024 } else if (s
->pauth_active
) {
5025 tcg_rd
= cpu_reg(s
, rd
);
5026 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5029 case MAP(1, 0x01, 0x0e): /* AUTDZA */
5030 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5031 goto do_unallocated
;
5032 } else if (s
->pauth_active
) {
5033 tcg_rd
= cpu_reg(s
, rd
);
5034 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5037 case MAP(1, 0x01, 0x0f): /* AUTDZB */
5038 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5039 goto do_unallocated
;
5040 } else if (s
->pauth_active
) {
5041 tcg_rd
= cpu_reg(s
, rd
);
5042 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5045 case MAP(1, 0x01, 0x10): /* XPACI */
5046 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5047 goto do_unallocated
;
5048 } else if (s
->pauth_active
) {
5049 tcg_rd
= cpu_reg(s
, rd
);
5050 gen_helper_xpaci(tcg_rd
, cpu_env
, tcg_rd
);
5053 case MAP(1, 0x01, 0x11): /* XPACD */
5054 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5055 goto do_unallocated
;
5056 } else if (s
->pauth_active
) {
5057 tcg_rd
= cpu_reg(s
, rd
);
5058 gen_helper_xpacd(tcg_rd
, cpu_env
, tcg_rd
);
5063 unallocated_encoding(s
);
5070 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
5071 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5073 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
5074 tcg_rd
= cpu_reg(s
, rd
);
5076 if (!sf
&& is_signed
) {
5077 tcg_n
= new_tmp_a64(s
);
5078 tcg_m
= new_tmp_a64(s
);
5079 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
5080 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
5082 tcg_n
= read_cpu_reg(s
, rn
, sf
);
5083 tcg_m
= read_cpu_reg(s
, rm
, sf
);
5087 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
5089 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
5092 if (!sf
) { /* zero extend final result */
5093 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
5097 /* LSLV, LSRV, ASRV, RORV */
5098 static void handle_shift_reg(DisasContext
*s
,
5099 enum a64_shift_type shift_type
, unsigned int sf
,
5100 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5102 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
5103 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5104 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
5106 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
5107 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
5108 tcg_temp_free_i64(tcg_shift
);
5111 /* CRC32[BHWX], CRC32C[BHWX] */
5112 static void handle_crc32(DisasContext
*s
,
5113 unsigned int sf
, unsigned int sz
, bool crc32c
,
5114 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5116 TCGv_i64 tcg_acc
, tcg_val
;
5119 if (!dc_isar_feature(aa64_crc32
, s
)
5120 || (sf
== 1 && sz
!= 3)
5121 || (sf
== 0 && sz
== 3)) {
5122 unallocated_encoding(s
);
5127 tcg_val
= cpu_reg(s
, rm
);
5141 g_assert_not_reached();
5143 tcg_val
= new_tmp_a64(s
);
5144 tcg_gen_andi_i64(tcg_val
, cpu_reg(s
, rm
), mask
);
5147 tcg_acc
= cpu_reg(s
, rn
);
5148 tcg_bytes
= tcg_const_i32(1 << sz
);
5151 gen_helper_crc32c_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
5153 gen_helper_crc32_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
5156 tcg_temp_free_i32(tcg_bytes
);
5159 /* Data-processing (2 source)
5160 * 31 30 29 28 21 20 16 15 10 9 5 4 0
5161 * +----+---+---+-----------------+------+--------+------+------+
5162 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
5163 * +----+---+---+-----------------+------+--------+------+------+
5165 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
5167 unsigned int sf
, rm
, opcode
, rn
, rd
;
5168 sf
= extract32(insn
, 31, 1);
5169 rm
= extract32(insn
, 16, 5);
5170 opcode
= extract32(insn
, 10, 6);
5171 rn
= extract32(insn
, 5, 5);
5172 rd
= extract32(insn
, 0, 5);
5174 if (extract32(insn
, 29, 1)) {
5175 unallocated_encoding(s
);
5181 handle_div(s
, false, sf
, rm
, rn
, rd
);
5184 handle_div(s
, true, sf
, rm
, rn
, rd
);
5187 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
5190 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
5193 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
5196 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
5198 case 12: /* PACGA */
5199 if (sf
== 0 || !dc_isar_feature(aa64_pauth
, s
)) {
5200 goto do_unallocated
;
5202 gen_helper_pacga(cpu_reg(s
, rd
), cpu_env
,
5203 cpu_reg(s
, rn
), cpu_reg_sp(s
, rm
));
5212 case 23: /* CRC32 */
5214 int sz
= extract32(opcode
, 0, 2);
5215 bool crc32c
= extract32(opcode
, 2, 1);
5216 handle_crc32(s
, sf
, sz
, crc32c
, rm
, rn
, rd
);
5221 unallocated_encoding(s
);
5227 * Data processing - register
5228 * 31 30 29 28 25 21 20 16 10 0
5229 * +--+---+--+---+-------+-----+-------+-------+---------+
5230 * | |op0| |op1| 1 0 1 | op2 | | op3 | |
5231 * +--+---+--+---+-------+-----+-------+-------+---------+
5233 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
5235 int op0
= extract32(insn
, 30, 1);
5236 int op1
= extract32(insn
, 28, 1);
5237 int op2
= extract32(insn
, 21, 4);
5238 int op3
= extract32(insn
, 10, 6);
5243 /* Add/sub (extended register) */
5244 disas_add_sub_ext_reg(s
, insn
);
5246 /* Add/sub (shifted register) */
5247 disas_add_sub_reg(s
, insn
);
5250 /* Logical (shifted register) */
5251 disas_logic_reg(s
, insn
);
5259 case 0x00: /* Add/subtract (with carry) */
5260 disas_adc_sbc(s
, insn
);
5263 case 0x01: /* Rotate right into flags */
5265 disas_rotate_right_into_flags(s
, insn
);
5268 case 0x02: /* Evaluate into flags */
5272 disas_evaluate_into_flags(s
, insn
);
5276 goto do_unallocated
;
5280 case 0x2: /* Conditional compare */
5281 disas_cc(s
, insn
); /* both imm and reg forms */
5284 case 0x4: /* Conditional select */
5285 disas_cond_select(s
, insn
);
5288 case 0x6: /* Data-processing */
5289 if (op0
) { /* (1 source) */
5290 disas_data_proc_1src(s
, insn
);
5291 } else { /* (2 source) */
5292 disas_data_proc_2src(s
, insn
);
5295 case 0x8 ... 0xf: /* (3 source) */
5296 disas_data_proc_3src(s
, insn
);
5301 unallocated_encoding(s
);
5306 static void handle_fp_compare(DisasContext
*s
, int size
,
5307 unsigned int rn
, unsigned int rm
,
5308 bool cmp_with_zero
, bool signal_all_nans
)
5310 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
5311 TCGv_ptr fpst
= get_fpstatus_ptr(size
== MO_16
);
5313 if (size
== MO_64
) {
5314 TCGv_i64 tcg_vn
, tcg_vm
;
5316 tcg_vn
= read_fp_dreg(s
, rn
);
5317 if (cmp_with_zero
) {
5318 tcg_vm
= tcg_const_i64(0);
5320 tcg_vm
= read_fp_dreg(s
, rm
);
5322 if (signal_all_nans
) {
5323 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5325 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5327 tcg_temp_free_i64(tcg_vn
);
5328 tcg_temp_free_i64(tcg_vm
);
5330 TCGv_i32 tcg_vn
= tcg_temp_new_i32();
5331 TCGv_i32 tcg_vm
= tcg_temp_new_i32();
5333 read_vec_element_i32(s
, tcg_vn
, rn
, 0, size
);
5334 if (cmp_with_zero
) {
5335 tcg_gen_movi_i32(tcg_vm
, 0);
5337 read_vec_element_i32(s
, tcg_vm
, rm
, 0, size
);
5342 if (signal_all_nans
) {
5343 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5345 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5349 if (signal_all_nans
) {
5350 gen_helper_vfp_cmpeh_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5352 gen_helper_vfp_cmph_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5356 g_assert_not_reached();
5359 tcg_temp_free_i32(tcg_vn
);
5360 tcg_temp_free_i32(tcg_vm
);
5363 tcg_temp_free_ptr(fpst
);
5365 gen_set_nzcv(tcg_flags
);
5367 tcg_temp_free_i64(tcg_flags
);
5370 /* Floating point compare
5371 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
5372 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
5373 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
5374 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
5376 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
5378 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
5381 mos
= extract32(insn
, 29, 3);
5382 type
= extract32(insn
, 22, 2);
5383 rm
= extract32(insn
, 16, 5);
5384 op
= extract32(insn
, 14, 2);
5385 rn
= extract32(insn
, 5, 5);
5386 opc
= extract32(insn
, 3, 2);
5387 op2r
= extract32(insn
, 0, 3);
5389 if (mos
|| op
|| op2r
) {
5390 unallocated_encoding(s
);
5403 if (dc_isar_feature(aa64_fp16
, s
)) {
5408 unallocated_encoding(s
);
5412 if (!fp_access_check(s
)) {
5416 handle_fp_compare(s
, size
, rn
, rm
, opc
& 1, opc
& 2);
5419 /* Floating point conditional compare
5420 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
5421 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
5422 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
5423 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
5425 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
5427 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
5429 TCGLabel
*label_continue
= NULL
;
5432 mos
= extract32(insn
, 29, 3);
5433 type
= extract32(insn
, 22, 2);
5434 rm
= extract32(insn
, 16, 5);
5435 cond
= extract32(insn
, 12, 4);
5436 rn
= extract32(insn
, 5, 5);
5437 op
= extract32(insn
, 4, 1);
5438 nzcv
= extract32(insn
, 0, 4);
5441 unallocated_encoding(s
);
5454 if (dc_isar_feature(aa64_fp16
, s
)) {
5459 unallocated_encoding(s
);
5463 if (!fp_access_check(s
)) {
5467 if (cond
< 0x0e) { /* not always */
5468 TCGLabel
*label_match
= gen_new_label();
5469 label_continue
= gen_new_label();
5470 arm_gen_test_cc(cond
, label_match
);
5472 tcg_flags
= tcg_const_i64(nzcv
<< 28);
5473 gen_set_nzcv(tcg_flags
);
5474 tcg_temp_free_i64(tcg_flags
);
5475 tcg_gen_br(label_continue
);
5476 gen_set_label(label_match
);
5479 handle_fp_compare(s
, size
, rn
, rm
, false, op
);
5482 gen_set_label(label_continue
);
5486 /* Floating point conditional select
5487 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
5488 * +---+---+---+-----------+------+---+------+------+-----+------+------+
5489 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
5490 * +---+---+---+-----------+------+---+------+------+-----+------+------+
5492 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
5494 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
5495 TCGv_i64 t_true
, t_false
, t_zero
;
5499 mos
= extract32(insn
, 29, 3);
5500 type
= extract32(insn
, 22, 2);
5501 rm
= extract32(insn
, 16, 5);
5502 cond
= extract32(insn
, 12, 4);
5503 rn
= extract32(insn
, 5, 5);
5504 rd
= extract32(insn
, 0, 5);
5507 unallocated_encoding(s
);
5520 if (dc_isar_feature(aa64_fp16
, s
)) {
5525 unallocated_encoding(s
);
5529 if (!fp_access_check(s
)) {
5533 /* Zero extend sreg & hreg inputs to 64 bits now. */
5534 t_true
= tcg_temp_new_i64();
5535 t_false
= tcg_temp_new_i64();
5536 read_vec_element(s
, t_true
, rn
, 0, sz
);
5537 read_vec_element(s
, t_false
, rm
, 0, sz
);
5539 a64_test_cc(&c
, cond
);
5540 t_zero
= tcg_const_i64(0);
5541 tcg_gen_movcond_i64(c
.cond
, t_true
, c
.value
, t_zero
, t_true
, t_false
);
5542 tcg_temp_free_i64(t_zero
);
5543 tcg_temp_free_i64(t_false
);
5546 /* Note that sregs & hregs write back zeros to the high bits,
5547 and we've already done the zero-extension. */
5548 write_fp_dreg(s
, rd
, t_true
);
5549 tcg_temp_free_i64(t_true
);
5552 /* Floating-point data-processing (1 source) - half precision */
5553 static void handle_fp_1src_half(DisasContext
*s
, int opcode
, int rd
, int rn
)
5555 TCGv_ptr fpst
= NULL
;
5556 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
5557 TCGv_i32 tcg_res
= tcg_temp_new_i32();
5560 case 0x0: /* FMOV */
5561 tcg_gen_mov_i32(tcg_res
, tcg_op
);
5563 case 0x1: /* FABS */
5564 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
5566 case 0x2: /* FNEG */
5567 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
5569 case 0x3: /* FSQRT */
5570 fpst
= get_fpstatus_ptr(true);
5571 gen_helper_sqrt_f16(tcg_res
, tcg_op
, fpst
);
5573 case 0x8: /* FRINTN */
5574 case 0x9: /* FRINTP */
5575 case 0xa: /* FRINTM */
5576 case 0xb: /* FRINTZ */
5577 case 0xc: /* FRINTA */
5579 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
5580 fpst
= get_fpstatus_ptr(true);
5582 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5583 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
5585 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5586 tcg_temp_free_i32(tcg_rmode
);
5589 case 0xe: /* FRINTX */
5590 fpst
= get_fpstatus_ptr(true);
5591 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, fpst
);
5593 case 0xf: /* FRINTI */
5594 fpst
= get_fpstatus_ptr(true);
5595 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
5601 write_fp_sreg(s
, rd
, tcg_res
);
5604 tcg_temp_free_ptr(fpst
);
5606 tcg_temp_free_i32(tcg_op
);
5607 tcg_temp_free_i32(tcg_res
);
5610 /* Floating-point data-processing (1 source) - single precision */
5611 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
5613 void (*gen_fpst
)(TCGv_i32
, TCGv_i32
, TCGv_ptr
);
5614 TCGv_i32 tcg_op
, tcg_res
;
5618 tcg_op
= read_fp_sreg(s
, rn
);
5619 tcg_res
= tcg_temp_new_i32();
5622 case 0x0: /* FMOV */
5623 tcg_gen_mov_i32(tcg_res
, tcg_op
);
5625 case 0x1: /* FABS */
5626 gen_helper_vfp_abss(tcg_res
, tcg_op
);
5628 case 0x2: /* FNEG */
5629 gen_helper_vfp_negs(tcg_res
, tcg_op
);
5631 case 0x3: /* FSQRT */
5632 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
5634 case 0x8: /* FRINTN */
5635 case 0x9: /* FRINTP */
5636 case 0xa: /* FRINTM */
5637 case 0xb: /* FRINTZ */
5638 case 0xc: /* FRINTA */
5639 rmode
= arm_rmode_to_sf(opcode
& 7);
5640 gen_fpst
= gen_helper_rints
;
5642 case 0xe: /* FRINTX */
5643 gen_fpst
= gen_helper_rints_exact
;
5645 case 0xf: /* FRINTI */
5646 gen_fpst
= gen_helper_rints
;
5648 case 0x10: /* FRINT32Z */
5649 rmode
= float_round_to_zero
;
5650 gen_fpst
= gen_helper_frint32_s
;
5652 case 0x11: /* FRINT32X */
5653 gen_fpst
= gen_helper_frint32_s
;
5655 case 0x12: /* FRINT64Z */
5656 rmode
= float_round_to_zero
;
5657 gen_fpst
= gen_helper_frint64_s
;
5659 case 0x13: /* FRINT64X */
5660 gen_fpst
= gen_helper_frint64_s
;
5663 g_assert_not_reached();
5666 fpst
= get_fpstatus_ptr(false);
5668 TCGv_i32 tcg_rmode
= tcg_const_i32(rmode
);
5669 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5670 gen_fpst(tcg_res
, tcg_op
, fpst
);
5671 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5672 tcg_temp_free_i32(tcg_rmode
);
5674 gen_fpst(tcg_res
, tcg_op
, fpst
);
5676 tcg_temp_free_ptr(fpst
);
5679 write_fp_sreg(s
, rd
, tcg_res
);
5680 tcg_temp_free_i32(tcg_op
);
5681 tcg_temp_free_i32(tcg_res
);
5684 /* Floating-point data-processing (1 source) - double precision */
5685 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
5687 void (*gen_fpst
)(TCGv_i64
, TCGv_i64
, TCGv_ptr
);
5688 TCGv_i64 tcg_op
, tcg_res
;
5693 case 0x0: /* FMOV */
5694 gen_gvec_fn2(s
, false, rd
, rn
, tcg_gen_gvec_mov
, 0);
5698 tcg_op
= read_fp_dreg(s
, rn
);
5699 tcg_res
= tcg_temp_new_i64();
5702 case 0x1: /* FABS */
5703 gen_helper_vfp_absd(tcg_res
, tcg_op
);
5705 case 0x2: /* FNEG */
5706 gen_helper_vfp_negd(tcg_res
, tcg_op
);
5708 case 0x3: /* FSQRT */
5709 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
5711 case 0x8: /* FRINTN */
5712 case 0x9: /* FRINTP */
5713 case 0xa: /* FRINTM */
5714 case 0xb: /* FRINTZ */
5715 case 0xc: /* FRINTA */
5716 rmode
= arm_rmode_to_sf(opcode
& 7);
5717 gen_fpst
= gen_helper_rintd
;
5719 case 0xe: /* FRINTX */
5720 gen_fpst
= gen_helper_rintd_exact
;
5722 case 0xf: /* FRINTI */
5723 gen_fpst
= gen_helper_rintd
;
5725 case 0x10: /* FRINT32Z */
5726 rmode
= float_round_to_zero
;
5727 gen_fpst
= gen_helper_frint32_d
;
5729 case 0x11: /* FRINT32X */
5730 gen_fpst
= gen_helper_frint32_d
;
5732 case 0x12: /* FRINT64Z */
5733 rmode
= float_round_to_zero
;
5734 gen_fpst
= gen_helper_frint64_d
;
5736 case 0x13: /* FRINT64X */
5737 gen_fpst
= gen_helper_frint64_d
;
5740 g_assert_not_reached();
5743 fpst
= get_fpstatus_ptr(false);
5745 TCGv_i32 tcg_rmode
= tcg_const_i32(rmode
);
5746 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5747 gen_fpst(tcg_res
, tcg_op
, fpst
);
5748 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5749 tcg_temp_free_i32(tcg_rmode
);
5751 gen_fpst(tcg_res
, tcg_op
, fpst
);
5753 tcg_temp_free_ptr(fpst
);
5756 write_fp_dreg(s
, rd
, tcg_res
);
5757 tcg_temp_free_i64(tcg_op
);
5758 tcg_temp_free_i64(tcg_res
);
5761 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
5762 int rd
, int rn
, int dtype
, int ntype
)
5767 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
5769 /* Single to double */
5770 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
5771 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
5772 write_fp_dreg(s
, rd
, tcg_rd
);
5773 tcg_temp_free_i64(tcg_rd
);
5775 /* Single to half */
5776 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5777 TCGv_i32 ahp
= get_ahp_flag();
5778 TCGv_ptr fpst
= get_fpstatus_ptr(false);
5780 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
5781 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
5782 write_fp_sreg(s
, rd
, tcg_rd
);
5783 tcg_temp_free_i32(tcg_rd
);
5784 tcg_temp_free_i32(ahp
);
5785 tcg_temp_free_ptr(fpst
);
5787 tcg_temp_free_i32(tcg_rn
);
5792 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
5793 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5795 /* Double to single */
5796 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
5798 TCGv_ptr fpst
= get_fpstatus_ptr(false);
5799 TCGv_i32 ahp
= get_ahp_flag();
5800 /* Double to half */
5801 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
5802 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
5803 tcg_temp_free_ptr(fpst
);
5804 tcg_temp_free_i32(ahp
);
5806 write_fp_sreg(s
, rd
, tcg_rd
);
5807 tcg_temp_free_i32(tcg_rd
);
5808 tcg_temp_free_i64(tcg_rn
);
5813 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
5814 TCGv_ptr tcg_fpst
= get_fpstatus_ptr(false);
5815 TCGv_i32 tcg_ahp
= get_ahp_flag();
5816 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
5818 /* Half to single */
5819 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5820 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
5821 write_fp_sreg(s
, rd
, tcg_rd
);
5822 tcg_temp_free_i32(tcg_rd
);
5824 /* Half to double */
5825 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
5826 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
5827 write_fp_dreg(s
, rd
, tcg_rd
);
5828 tcg_temp_free_i64(tcg_rd
);
5830 tcg_temp_free_i32(tcg_rn
);
5831 tcg_temp_free_ptr(tcg_fpst
);
5832 tcg_temp_free_i32(tcg_ahp
);
5840 /* Floating point data-processing (1 source)
5841 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
5842 * +---+---+---+-----------+------+---+--------+-----------+------+------+
5843 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
5844 * +---+---+---+-----------+------+---+--------+-----------+------+------+
5846 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
5848 int mos
= extract32(insn
, 29, 3);
5849 int type
= extract32(insn
, 22, 2);
5850 int opcode
= extract32(insn
, 15, 6);
5851 int rn
= extract32(insn
, 5, 5);
5852 int rd
= extract32(insn
, 0, 5);
5855 unallocated_encoding(s
);
5860 case 0x4: case 0x5: case 0x7:
5862 /* FCVT between half, single and double precision */
5863 int dtype
= extract32(opcode
, 0, 2);
5864 if (type
== 2 || dtype
== type
) {
5865 unallocated_encoding(s
);
5868 if (!fp_access_check(s
)) {
5872 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
5876 case 0x10 ... 0x13: /* FRINT{32,64}{X,Z} */
5877 if (type
> 1 || !dc_isar_feature(aa64_frint
, s
)) {
5878 unallocated_encoding(s
);
5885 /* 32-to-32 and 64-to-64 ops */
5888 if (!fp_access_check(s
)) {
5891 handle_fp_1src_single(s
, opcode
, rd
, rn
);
5894 if (!fp_access_check(s
)) {
5897 handle_fp_1src_double(s
, opcode
, rd
, rn
);
5900 if (!dc_isar_feature(aa64_fp16
, s
)) {
5901 unallocated_encoding(s
);
5905 if (!fp_access_check(s
)) {
5908 handle_fp_1src_half(s
, opcode
, rd
, rn
);
5911 unallocated_encoding(s
);
5916 unallocated_encoding(s
);
5921 /* Floating-point data-processing (2 source) - single precision */
5922 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
5923 int rd
, int rn
, int rm
)
5930 tcg_res
= tcg_temp_new_i32();
5931 fpst
= get_fpstatus_ptr(false);
5932 tcg_op1
= read_fp_sreg(s
, rn
);
5933 tcg_op2
= read_fp_sreg(s
, rm
);
5936 case 0x0: /* FMUL */
5937 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5939 case 0x1: /* FDIV */
5940 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5942 case 0x2: /* FADD */
5943 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5945 case 0x3: /* FSUB */
5946 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5948 case 0x4: /* FMAX */
5949 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5951 case 0x5: /* FMIN */
5952 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5954 case 0x6: /* FMAXNM */
5955 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5957 case 0x7: /* FMINNM */
5958 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5960 case 0x8: /* FNMUL */
5961 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5962 gen_helper_vfp_negs(tcg_res
, tcg_res
);
5966 write_fp_sreg(s
, rd
, tcg_res
);
5968 tcg_temp_free_ptr(fpst
);
5969 tcg_temp_free_i32(tcg_op1
);
5970 tcg_temp_free_i32(tcg_op2
);
5971 tcg_temp_free_i32(tcg_res
);
5974 /* Floating-point data-processing (2 source) - double precision */
5975 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
5976 int rd
, int rn
, int rm
)
5983 tcg_res
= tcg_temp_new_i64();
5984 fpst
= get_fpstatus_ptr(false);
5985 tcg_op1
= read_fp_dreg(s
, rn
);
5986 tcg_op2
= read_fp_dreg(s
, rm
);
5989 case 0x0: /* FMUL */
5990 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5992 case 0x1: /* FDIV */
5993 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5995 case 0x2: /* FADD */
5996 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5998 case 0x3: /* FSUB */
5999 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6001 case 0x4: /* FMAX */
6002 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6004 case 0x5: /* FMIN */
6005 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6007 case 0x6: /* FMAXNM */
6008 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6010 case 0x7: /* FMINNM */
6011 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6013 case 0x8: /* FNMUL */
6014 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6015 gen_helper_vfp_negd(tcg_res
, tcg_res
);
6019 write_fp_dreg(s
, rd
, tcg_res
);
6021 tcg_temp_free_ptr(fpst
);
6022 tcg_temp_free_i64(tcg_op1
);
6023 tcg_temp_free_i64(tcg_op2
);
6024 tcg_temp_free_i64(tcg_res
);
6027 /* Floating-point data-processing (2 source) - half precision */
6028 static void handle_fp_2src_half(DisasContext
*s
, int opcode
,
6029 int rd
, int rn
, int rm
)
6036 tcg_res
= tcg_temp_new_i32();
6037 fpst
= get_fpstatus_ptr(true);
6038 tcg_op1
= read_fp_hreg(s
, rn
);
6039 tcg_op2
= read_fp_hreg(s
, rm
);
6042 case 0x0: /* FMUL */
6043 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6045 case 0x1: /* FDIV */
6046 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6048 case 0x2: /* FADD */
6049 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6051 case 0x3: /* FSUB */
6052 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6054 case 0x4: /* FMAX */
6055 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6057 case 0x5: /* FMIN */
6058 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6060 case 0x6: /* FMAXNM */
6061 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6063 case 0x7: /* FMINNM */
6064 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6066 case 0x8: /* FNMUL */
6067 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6068 tcg_gen_xori_i32(tcg_res
, tcg_res
, 0x8000);
6071 g_assert_not_reached();
6074 write_fp_sreg(s
, rd
, tcg_res
);
6076 tcg_temp_free_ptr(fpst
);
6077 tcg_temp_free_i32(tcg_op1
);
6078 tcg_temp_free_i32(tcg_op2
);
6079 tcg_temp_free_i32(tcg_res
);
6082 /* Floating point data-processing (2 source)
6083 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
6084 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
6085 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
6086 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
6088 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
6090 int mos
= extract32(insn
, 29, 3);
6091 int type
= extract32(insn
, 22, 2);
6092 int rd
= extract32(insn
, 0, 5);
6093 int rn
= extract32(insn
, 5, 5);
6094 int rm
= extract32(insn
, 16, 5);
6095 int opcode
= extract32(insn
, 12, 4);
6097 if (opcode
> 8 || mos
) {
6098 unallocated_encoding(s
);
6104 if (!fp_access_check(s
)) {
6107 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
6110 if (!fp_access_check(s
)) {
6113 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
6116 if (!dc_isar_feature(aa64_fp16
, s
)) {
6117 unallocated_encoding(s
);
6120 if (!fp_access_check(s
)) {
6123 handle_fp_2src_half(s
, opcode
, rd
, rn
, rm
);
6126 unallocated_encoding(s
);
6130 /* Floating-point data-processing (3 source) - single precision */
6131 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
6132 int rd
, int rn
, int rm
, int ra
)
6134 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
6135 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6136 TCGv_ptr fpst
= get_fpstatus_ptr(false);
6138 tcg_op1
= read_fp_sreg(s
, rn
);
6139 tcg_op2
= read_fp_sreg(s
, rm
);
6140 tcg_op3
= read_fp_sreg(s
, ra
);
6142 /* These are fused multiply-add, and must be done as one
6143 * floating point operation with no rounding between the
6144 * multiplication and addition steps.
6145 * NB that doing the negations here as separate steps is
6146 * correct : an input NaN should come out with its sign bit
6147 * flipped if it is a negated-input.
6150 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
6154 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
6157 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6159 write_fp_sreg(s
, rd
, tcg_res
);
6161 tcg_temp_free_ptr(fpst
);
6162 tcg_temp_free_i32(tcg_op1
);
6163 tcg_temp_free_i32(tcg_op2
);
6164 tcg_temp_free_i32(tcg_op3
);
6165 tcg_temp_free_i32(tcg_res
);
6168 /* Floating-point data-processing (3 source) - double precision */
6169 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
6170 int rd
, int rn
, int rm
, int ra
)
6172 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
6173 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6174 TCGv_ptr fpst
= get_fpstatus_ptr(false);
6176 tcg_op1
= read_fp_dreg(s
, rn
);
6177 tcg_op2
= read_fp_dreg(s
, rm
);
6178 tcg_op3
= read_fp_dreg(s
, ra
);
6180 /* These are fused multiply-add, and must be done as one
6181 * floating point operation with no rounding between the
6182 * multiplication and addition steps.
6183 * NB that doing the negations here as separate steps is
6184 * correct : an input NaN should come out with its sign bit
6185 * flipped if it is a negated-input.
6188 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
6192 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
6195 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6197 write_fp_dreg(s
, rd
, tcg_res
);
6199 tcg_temp_free_ptr(fpst
);
6200 tcg_temp_free_i64(tcg_op1
);
6201 tcg_temp_free_i64(tcg_op2
);
6202 tcg_temp_free_i64(tcg_op3
);
6203 tcg_temp_free_i64(tcg_res
);
6206 /* Floating-point data-processing (3 source) - half precision */
6207 static void handle_fp_3src_half(DisasContext
*s
, bool o0
, bool o1
,
6208 int rd
, int rn
, int rm
, int ra
)
6210 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
6211 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6212 TCGv_ptr fpst
= get_fpstatus_ptr(true);
6214 tcg_op1
= read_fp_hreg(s
, rn
);
6215 tcg_op2
= read_fp_hreg(s
, rm
);
6216 tcg_op3
= read_fp_hreg(s
, ra
);
6218 /* These are fused multiply-add, and must be done as one
6219 * floating point operation with no rounding between the
6220 * multiplication and addition steps.
6221 * NB that doing the negations here as separate steps is
6222 * correct : an input NaN should come out with its sign bit
6223 * flipped if it is a negated-input.
6226 tcg_gen_xori_i32(tcg_op3
, tcg_op3
, 0x8000);
6230 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
6233 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6235 write_fp_sreg(s
, rd
, tcg_res
);
6237 tcg_temp_free_ptr(fpst
);
6238 tcg_temp_free_i32(tcg_op1
);
6239 tcg_temp_free_i32(tcg_op2
);
6240 tcg_temp_free_i32(tcg_op3
);
6241 tcg_temp_free_i32(tcg_res
);
6244 /* Floating point data-processing (3 source)
6245 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
6246 * +---+---+---+-----------+------+----+------+----+------+------+------+
6247 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
6248 * +---+---+---+-----------+------+----+------+----+------+------+------+
6250 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
6252 int mos
= extract32(insn
, 29, 3);
6253 int type
= extract32(insn
, 22, 2);
6254 int rd
= extract32(insn
, 0, 5);
6255 int rn
= extract32(insn
, 5, 5);
6256 int ra
= extract32(insn
, 10, 5);
6257 int rm
= extract32(insn
, 16, 5);
6258 bool o0
= extract32(insn
, 15, 1);
6259 bool o1
= extract32(insn
, 21, 1);
6262 unallocated_encoding(s
);
6268 if (!fp_access_check(s
)) {
6271 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6274 if (!fp_access_check(s
)) {
6277 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6280 if (!dc_isar_feature(aa64_fp16
, s
)) {
6281 unallocated_encoding(s
);
6284 if (!fp_access_check(s
)) {
6287 handle_fp_3src_half(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6290 unallocated_encoding(s
);
6294 /* Floating point immediate
6295 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
6296 * +---+---+---+-----------+------+---+------------+-------+------+------+
6297 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
6298 * +---+---+---+-----------+------+---+------------+-------+------+------+
6300 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
6302 int rd
= extract32(insn
, 0, 5);
6303 int imm5
= extract32(insn
, 5, 5);
6304 int imm8
= extract32(insn
, 13, 8);
6305 int type
= extract32(insn
, 22, 2);
6306 int mos
= extract32(insn
, 29, 3);
6312 unallocated_encoding(s
);
6325 if (dc_isar_feature(aa64_fp16
, s
)) {
6330 unallocated_encoding(s
);
6334 if (!fp_access_check(s
)) {
6338 imm
= vfp_expand_imm(sz
, imm8
);
6340 tcg_res
= tcg_const_i64(imm
);
6341 write_fp_dreg(s
, rd
, tcg_res
);
6342 tcg_temp_free_i64(tcg_res
);
6345 /* Handle floating point <=> fixed point conversions. Note that we can
6346 * also deal with fp <=> integer conversions as a special case (scale == 64)
6347 * OPTME: consider handling that special case specially or at least skipping
6348 * the call to scalbn in the helpers for zero shifts.
6350 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
6351 bool itof
, int rmode
, int scale
, int sf
, int type
)
6353 bool is_signed
= !(opcode
& 1);
6354 TCGv_ptr tcg_fpstatus
;
6355 TCGv_i32 tcg_shift
, tcg_single
;
6356 TCGv_i64 tcg_double
;
6358 tcg_fpstatus
= get_fpstatus_ptr(type
== 3);
6360 tcg_shift
= tcg_const_i32(64 - scale
);
6363 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
6365 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
6368 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
6370 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
6373 tcg_int
= tcg_extend
;
6377 case 1: /* float64 */
6378 tcg_double
= tcg_temp_new_i64();
6380 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
6381 tcg_shift
, tcg_fpstatus
);
6383 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
6384 tcg_shift
, tcg_fpstatus
);
6386 write_fp_dreg(s
, rd
, tcg_double
);
6387 tcg_temp_free_i64(tcg_double
);
6390 case 0: /* float32 */
6391 tcg_single
= tcg_temp_new_i32();
6393 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
6394 tcg_shift
, tcg_fpstatus
);
6396 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
6397 tcg_shift
, tcg_fpstatus
);
6399 write_fp_sreg(s
, rd
, tcg_single
);
6400 tcg_temp_free_i32(tcg_single
);
6403 case 3: /* float16 */
6404 tcg_single
= tcg_temp_new_i32();
6406 gen_helper_vfp_sqtoh(tcg_single
, tcg_int
,
6407 tcg_shift
, tcg_fpstatus
);
6409 gen_helper_vfp_uqtoh(tcg_single
, tcg_int
,
6410 tcg_shift
, tcg_fpstatus
);
6412 write_fp_sreg(s
, rd
, tcg_single
);
6413 tcg_temp_free_i32(tcg_single
);
6417 g_assert_not_reached();
6420 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
6423 if (extract32(opcode
, 2, 1)) {
6424 /* There are too many rounding modes to all fit into rmode,
6425 * so FCVTA[US] is a special case.
6427 rmode
= FPROUNDING_TIEAWAY
;
6430 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
6432 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
6435 case 1: /* float64 */
6436 tcg_double
= read_fp_dreg(s
, rn
);
6439 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
6440 tcg_shift
, tcg_fpstatus
);
6442 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
6443 tcg_shift
, tcg_fpstatus
);
6447 gen_helper_vfp_tould(tcg_int
, tcg_double
,
6448 tcg_shift
, tcg_fpstatus
);
6450 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
6451 tcg_shift
, tcg_fpstatus
);
6455 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
6457 tcg_temp_free_i64(tcg_double
);
6460 case 0: /* float32 */
6461 tcg_single
= read_fp_sreg(s
, rn
);
6464 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
6465 tcg_shift
, tcg_fpstatus
);
6467 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
6468 tcg_shift
, tcg_fpstatus
);
6471 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
6473 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
6474 tcg_shift
, tcg_fpstatus
);
6476 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
6477 tcg_shift
, tcg_fpstatus
);
6479 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
6480 tcg_temp_free_i32(tcg_dest
);
6482 tcg_temp_free_i32(tcg_single
);
6485 case 3: /* float16 */
6486 tcg_single
= read_fp_sreg(s
, rn
);
6489 gen_helper_vfp_tosqh(tcg_int
, tcg_single
,
6490 tcg_shift
, tcg_fpstatus
);
6492 gen_helper_vfp_touqh(tcg_int
, tcg_single
,
6493 tcg_shift
, tcg_fpstatus
);
6496 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
6498 gen_helper_vfp_toslh(tcg_dest
, tcg_single
,
6499 tcg_shift
, tcg_fpstatus
);
6501 gen_helper_vfp_toulh(tcg_dest
, tcg_single
,
6502 tcg_shift
, tcg_fpstatus
);
6504 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
6505 tcg_temp_free_i32(tcg_dest
);
6507 tcg_temp_free_i32(tcg_single
);
6511 g_assert_not_reached();
6514 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
6515 tcg_temp_free_i32(tcg_rmode
);
6518 tcg_temp_free_ptr(tcg_fpstatus
);
6519 tcg_temp_free_i32(tcg_shift
);
6522 /* Floating point <-> fixed point conversions
6523 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
6524 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
6525 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
6526 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
6528 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
6530 int rd
= extract32(insn
, 0, 5);
6531 int rn
= extract32(insn
, 5, 5);
6532 int scale
= extract32(insn
, 10, 6);
6533 int opcode
= extract32(insn
, 16, 3);
6534 int rmode
= extract32(insn
, 19, 2);
6535 int type
= extract32(insn
, 22, 2);
6536 bool sbit
= extract32(insn
, 29, 1);
6537 bool sf
= extract32(insn
, 31, 1);
6540 if (sbit
|| (!sf
&& scale
< 32)) {
6541 unallocated_encoding(s
);
6546 case 0: /* float32 */
6547 case 1: /* float64 */
6549 case 3: /* float16 */
6550 if (dc_isar_feature(aa64_fp16
, s
)) {
6555 unallocated_encoding(s
);
6559 switch ((rmode
<< 3) | opcode
) {
6560 case 0x2: /* SCVTF */
6561 case 0x3: /* UCVTF */
6564 case 0x18: /* FCVTZS */
6565 case 0x19: /* FCVTZU */
6569 unallocated_encoding(s
);
6573 if (!fp_access_check(s
)) {
6577 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
6580 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
6582 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
6583 * without conversion.
6587 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
6593 tmp
= tcg_temp_new_i64();
6594 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
6595 write_fp_dreg(s
, rd
, tmp
);
6596 tcg_temp_free_i64(tmp
);
6600 write_fp_dreg(s
, rd
, tcg_rn
);
6603 /* 64 bit to top half. */
6604 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(s
, rd
));
6605 clear_vec_high(s
, true, rd
);
6609 tmp
= tcg_temp_new_i64();
6610 tcg_gen_ext16u_i64(tmp
, tcg_rn
);
6611 write_fp_dreg(s
, rd
, tmp
);
6612 tcg_temp_free_i64(tmp
);
6615 g_assert_not_reached();
6618 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
6623 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_32
));
6627 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_64
));
6630 /* 64 bits from top half */
6631 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(s
, rn
));
6635 tcg_gen_ld16u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_16
));
6638 g_assert_not_reached();
6643 static void handle_fjcvtzs(DisasContext
*s
, int rd
, int rn
)
6645 TCGv_i64 t
= read_fp_dreg(s
, rn
);
6646 TCGv_ptr fpstatus
= get_fpstatus_ptr(false);
6648 gen_helper_fjcvtzs(t
, t
, fpstatus
);
6650 tcg_temp_free_ptr(fpstatus
);
6652 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), t
);
6653 tcg_gen_extrh_i64_i32(cpu_ZF
, t
);
6654 tcg_gen_movi_i32(cpu_CF
, 0);
6655 tcg_gen_movi_i32(cpu_NF
, 0);
6656 tcg_gen_movi_i32(cpu_VF
, 0);
6658 tcg_temp_free_i64(t
);
6661 /* Floating point <-> integer conversions
6662 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
6663 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
6664 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
6665 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
6667 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
6669 int rd
= extract32(insn
, 0, 5);
6670 int rn
= extract32(insn
, 5, 5);
6671 int opcode
= extract32(insn
, 16, 3);
6672 int rmode
= extract32(insn
, 19, 2);
6673 int type
= extract32(insn
, 22, 2);
6674 bool sbit
= extract32(insn
, 29, 1);
6675 bool sf
= extract32(insn
, 31, 1);
6679 goto do_unallocated
;
6687 case 4: /* FCVTAS */
6688 case 5: /* FCVTAU */
6690 goto do_unallocated
;
6693 case 0: /* FCVT[NPMZ]S */
6694 case 1: /* FCVT[NPMZ]U */
6696 case 0: /* float32 */
6697 case 1: /* float64 */
6699 case 3: /* float16 */
6700 if (!dc_isar_feature(aa64_fp16
, s
)) {
6701 goto do_unallocated
;
6705 goto do_unallocated
;
6707 if (!fp_access_check(s
)) {
6710 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
6714 switch (sf
<< 7 | type
<< 5 | rmode
<< 3 | opcode
) {
6715 case 0b01100110: /* FMOV half <-> 32-bit int */
6717 case 0b11100110: /* FMOV half <-> 64-bit int */
6719 if (!dc_isar_feature(aa64_fp16
, s
)) {
6720 goto do_unallocated
;
6723 case 0b00000110: /* FMOV 32-bit */
6725 case 0b10100110: /* FMOV 64-bit */
6727 case 0b11001110: /* FMOV top half of 128-bit */
6729 if (!fp_access_check(s
)) {
6733 handle_fmov(s
, rd
, rn
, type
, itof
);
6736 case 0b00111110: /* FJCVTZS */
6737 if (!dc_isar_feature(aa64_jscvt
, s
)) {
6738 goto do_unallocated
;
6739 } else if (fp_access_check(s
)) {
6740 handle_fjcvtzs(s
, rd
, rn
);
6746 unallocated_encoding(s
);
6753 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
6754 * 31 30 29 28 25 24 0
6755 * +---+---+---+---------+-----------------------------+
6756 * | | 0 | | 1 1 1 1 | |
6757 * +---+---+---+---------+-----------------------------+
6759 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
6761 if (extract32(insn
, 24, 1)) {
6762 /* Floating point data-processing (3 source) */
6763 disas_fp_3src(s
, insn
);
6764 } else if (extract32(insn
, 21, 1) == 0) {
6765 /* Floating point to fixed point conversions */
6766 disas_fp_fixed_conv(s
, insn
);
6768 switch (extract32(insn
, 10, 2)) {
6770 /* Floating point conditional compare */
6771 disas_fp_ccomp(s
, insn
);
6774 /* Floating point data-processing (2 source) */
6775 disas_fp_2src(s
, insn
);
6778 /* Floating point conditional select */
6779 disas_fp_csel(s
, insn
);
6782 switch (ctz32(extract32(insn
, 12, 4))) {
6783 case 0: /* [15:12] == xxx1 */
6784 /* Floating point immediate */
6785 disas_fp_imm(s
, insn
);
6787 case 1: /* [15:12] == xx10 */
6788 /* Floating point compare */
6789 disas_fp_compare(s
, insn
);
6791 case 2: /* [15:12] == x100 */
6792 /* Floating point data-processing (1 source) */
6793 disas_fp_1src(s
, insn
);
6795 case 3: /* [15:12] == 1000 */
6796 unallocated_encoding(s
);
6798 default: /* [15:12] == 0000 */
6799 /* Floating point <-> integer conversions */
6800 disas_fp_int_conv(s
, insn
);
6808 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
6811 /* Extract 64 bits from the middle of two concatenated 64 bit
6812 * vector register slices left:right. The extracted bits start
6813 * at 'pos' bits into the right (least significant) side.
6814 * We return the result in tcg_right, and guarantee not to
6817 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
6818 assert(pos
> 0 && pos
< 64);
6820 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
6821 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
6822 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
6824 tcg_temp_free_i64(tcg_tmp
);
6828 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
6829 * +---+---+-------------+-----+---+------+---+------+---+------+------+
6830 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
6831 * +---+---+-------------+-----+---+------+---+------+---+------+------+
6833 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
6835 int is_q
= extract32(insn
, 30, 1);
6836 int op2
= extract32(insn
, 22, 2);
6837 int imm4
= extract32(insn
, 11, 4);
6838 int rm
= extract32(insn
, 16, 5);
6839 int rn
= extract32(insn
, 5, 5);
6840 int rd
= extract32(insn
, 0, 5);
6841 int pos
= imm4
<< 3;
6842 TCGv_i64 tcg_resl
, tcg_resh
;
6844 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
6845 unallocated_encoding(s
);
6849 if (!fp_access_check(s
)) {
6853 tcg_resh
= tcg_temp_new_i64();
6854 tcg_resl
= tcg_temp_new_i64();
6856 /* Vd gets bits starting at pos bits into Vm:Vn. This is
6857 * either extracting 128 bits from a 128:128 concatenation, or
6858 * extracting 64 bits from a 64:64 concatenation.
6861 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
6863 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
6864 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
6866 tcg_gen_movi_i64(tcg_resh
, 0);
6873 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
6874 EltPosns
*elt
= eltposns
;
6881 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
6883 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
6886 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
6887 tcg_hh
= tcg_temp_new_i64();
6888 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
6889 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
6890 tcg_temp_free_i64(tcg_hh
);
6894 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
6895 tcg_temp_free_i64(tcg_resl
);
6896 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
6897 tcg_temp_free_i64(tcg_resh
);
6898 clear_vec_high(s
, true, rd
);
6902 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
6903 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
6904 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
6905 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
6907 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
6909 int op2
= extract32(insn
, 22, 2);
6910 int is_q
= extract32(insn
, 30, 1);
6911 int rm
= extract32(insn
, 16, 5);
6912 int rn
= extract32(insn
, 5, 5);
6913 int rd
= extract32(insn
, 0, 5);
6914 int is_tblx
= extract32(insn
, 12, 1);
6915 int len
= extract32(insn
, 13, 2);
6916 TCGv_i64 tcg_resl
, tcg_resh
, tcg_idx
;
6917 TCGv_i32 tcg_regno
, tcg_numregs
;
6920 unallocated_encoding(s
);
6924 if (!fp_access_check(s
)) {
6928 /* This does a table lookup: for every byte element in the input
6929 * we index into a table formed from up to four vector registers,
6930 * and then the output is the result of the lookups. Our helper
6931 * function does the lookup operation for a single 64 bit part of
6934 tcg_resl
= tcg_temp_new_i64();
6935 tcg_resh
= tcg_temp_new_i64();
6938 read_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
6940 tcg_gen_movi_i64(tcg_resl
, 0);
6942 if (is_tblx
&& is_q
) {
6943 read_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
6945 tcg_gen_movi_i64(tcg_resh
, 0);
6948 tcg_idx
= tcg_temp_new_i64();
6949 tcg_regno
= tcg_const_i32(rn
);
6950 tcg_numregs
= tcg_const_i32(len
+ 1);
6951 read_vec_element(s
, tcg_idx
, rm
, 0, MO_64
);
6952 gen_helper_simd_tbl(tcg_resl
, cpu_env
, tcg_resl
, tcg_idx
,
6953 tcg_regno
, tcg_numregs
);
6955 read_vec_element(s
, tcg_idx
, rm
, 1, MO_64
);
6956 gen_helper_simd_tbl(tcg_resh
, cpu_env
, tcg_resh
, tcg_idx
,
6957 tcg_regno
, tcg_numregs
);
6959 tcg_temp_free_i64(tcg_idx
);
6960 tcg_temp_free_i32(tcg_regno
);
6961 tcg_temp_free_i32(tcg_numregs
);
6963 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
6964 tcg_temp_free_i64(tcg_resl
);
6965 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
6966 tcg_temp_free_i64(tcg_resh
);
6967 clear_vec_high(s
, true, rd
);
6971 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
6972 * +---+---+-------------+------+---+------+---+------------------+------+
6973 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
6974 * +---+---+-------------+------+---+------+---+------------------+------+
6976 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
6978 int rd
= extract32(insn
, 0, 5);
6979 int rn
= extract32(insn
, 5, 5);
6980 int rm
= extract32(insn
, 16, 5);
6981 int size
= extract32(insn
, 22, 2);
6982 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
6983 * bit 2 indicates 1 vs 2 variant of the insn.
6985 int opcode
= extract32(insn
, 12, 2);
6986 bool part
= extract32(insn
, 14, 1);
6987 bool is_q
= extract32(insn
, 30, 1);
6988 int esize
= 8 << size
;
6990 int datasize
= is_q
? 128 : 64;
6991 int elements
= datasize
/ esize
;
6992 TCGv_i64 tcg_res
, tcg_resl
, tcg_resh
;
6994 if (opcode
== 0 || (size
== 3 && !is_q
)) {
6995 unallocated_encoding(s
);
6999 if (!fp_access_check(s
)) {
7003 tcg_resl
= tcg_const_i64(0);
7004 tcg_resh
= tcg_const_i64(0);
7005 tcg_res
= tcg_temp_new_i64();
7007 for (i
= 0; i
< elements
; i
++) {
7009 case 1: /* UZP1/2 */
7011 int midpoint
= elements
/ 2;
7013 read_vec_element(s
, tcg_res
, rn
, 2 * i
+ part
, size
);
7015 read_vec_element(s
, tcg_res
, rm
,
7016 2 * (i
- midpoint
) + part
, size
);
7020 case 2: /* TRN1/2 */
7022 read_vec_element(s
, tcg_res
, rm
, (i
& ~1) + part
, size
);
7024 read_vec_element(s
, tcg_res
, rn
, (i
& ~1) + part
, size
);
7027 case 3: /* ZIP1/2 */
7029 int base
= part
* elements
/ 2;
7031 read_vec_element(s
, tcg_res
, rm
, base
+ (i
>> 1), size
);
7033 read_vec_element(s
, tcg_res
, rn
, base
+ (i
>> 1), size
);
7038 g_assert_not_reached();
7043 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
);
7044 tcg_gen_or_i64(tcg_resl
, tcg_resl
, tcg_res
);
7046 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
- 64);
7047 tcg_gen_or_i64(tcg_resh
, tcg_resh
, tcg_res
);
7051 tcg_temp_free_i64(tcg_res
);
7053 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7054 tcg_temp_free_i64(tcg_resl
);
7055 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7056 tcg_temp_free_i64(tcg_resh
);
7057 clear_vec_high(s
, true, rd
);
7061 * do_reduction_op helper
7063 * This mirrors the Reduce() pseudocode in the ARM ARM. It is
7064 * important for correct NaN propagation that we do these
7065 * operations in exactly the order specified by the pseudocode.
7067 * This is a recursive function, TCG temps should be freed by the
7068 * calling function once it is done with the values.
7070 static TCGv_i32
do_reduction_op(DisasContext
*s
, int fpopcode
, int rn
,
7071 int esize
, int size
, int vmap
, TCGv_ptr fpst
)
7073 if (esize
== size
) {
7075 MemOp msize
= esize
== 16 ? MO_16
: MO_32
;
7078 /* We should have one register left here */
7079 assert(ctpop8(vmap
) == 1);
7080 element
= ctz32(vmap
);
7081 assert(element
< 8);
7083 tcg_elem
= tcg_temp_new_i32();
7084 read_vec_element_i32(s
, tcg_elem
, rn
, element
, msize
);
7087 int bits
= size
/ 2;
7088 int shift
= ctpop8(vmap
) / 2;
7089 int vmap_lo
= (vmap
>> shift
) & vmap
;
7090 int vmap_hi
= (vmap
& ~vmap_lo
);
7091 TCGv_i32 tcg_hi
, tcg_lo
, tcg_res
;
7093 tcg_hi
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_hi
, fpst
);
7094 tcg_lo
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_lo
, fpst
);
7095 tcg_res
= tcg_temp_new_i32();
7098 case 0x0c: /* fmaxnmv half-precision */
7099 gen_helper_advsimd_maxnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7101 case 0x0f: /* fmaxv half-precision */
7102 gen_helper_advsimd_maxh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7104 case 0x1c: /* fminnmv half-precision */
7105 gen_helper_advsimd_minnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7107 case 0x1f: /* fminv half-precision */
7108 gen_helper_advsimd_minh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7110 case 0x2c: /* fmaxnmv */
7111 gen_helper_vfp_maxnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7113 case 0x2f: /* fmaxv */
7114 gen_helper_vfp_maxs(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7116 case 0x3c: /* fminnmv */
7117 gen_helper_vfp_minnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7119 case 0x3f: /* fminv */
7120 gen_helper_vfp_mins(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7123 g_assert_not_reached();
7126 tcg_temp_free_i32(tcg_hi
);
7127 tcg_temp_free_i32(tcg_lo
);
7132 /* AdvSIMD across lanes
7133 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7134 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
7135 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
7136 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
7138 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
7140 int rd
= extract32(insn
, 0, 5);
7141 int rn
= extract32(insn
, 5, 5);
7142 int size
= extract32(insn
, 22, 2);
7143 int opcode
= extract32(insn
, 12, 5);
7144 bool is_q
= extract32(insn
, 30, 1);
7145 bool is_u
= extract32(insn
, 29, 1);
7147 bool is_min
= false;
7151 TCGv_i64 tcg_res
, tcg_elt
;
7154 case 0x1b: /* ADDV */
7156 unallocated_encoding(s
);
7160 case 0x3: /* SADDLV, UADDLV */
7161 case 0xa: /* SMAXV, UMAXV */
7162 case 0x1a: /* SMINV, UMINV */
7163 if (size
== 3 || (size
== 2 && !is_q
)) {
7164 unallocated_encoding(s
);
7168 case 0xc: /* FMAXNMV, FMINNMV */
7169 case 0xf: /* FMAXV, FMINV */
7170 /* Bit 1 of size field encodes min vs max and the actual size
7171 * depends on the encoding of the U bit. If not set (and FP16
7172 * enabled) then we do half-precision float instead of single
7175 is_min
= extract32(size
, 1, 1);
7177 if (!is_u
&& dc_isar_feature(aa64_fp16
, s
)) {
7179 } else if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
7180 unallocated_encoding(s
);
7187 unallocated_encoding(s
);
7191 if (!fp_access_check(s
)) {
7196 elements
= (is_q
? 128 : 64) / esize
;
7198 tcg_res
= tcg_temp_new_i64();
7199 tcg_elt
= tcg_temp_new_i64();
7201 /* These instructions operate across all lanes of a vector
7202 * to produce a single result. We can guarantee that a 64
7203 * bit intermediate is sufficient:
7204 * + for [US]ADDLV the maximum element size is 32 bits, and
7205 * the result type is 64 bits
7206 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
7207 * same as the element size, which is 32 bits at most
7208 * For the integer operations we can choose to work at 64
7209 * or 32 bits and truncate at the end; for simplicity
7210 * we use 64 bits always. The floating point
7211 * ops do require 32 bit intermediates, though.
7214 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
7216 for (i
= 1; i
< elements
; i
++) {
7217 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
7220 case 0x03: /* SADDLV / UADDLV */
7221 case 0x1b: /* ADDV */
7222 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
7224 case 0x0a: /* SMAXV / UMAXV */
7226 tcg_gen_umax_i64(tcg_res
, tcg_res
, tcg_elt
);
7228 tcg_gen_smax_i64(tcg_res
, tcg_res
, tcg_elt
);
7231 case 0x1a: /* SMINV / UMINV */
7233 tcg_gen_umin_i64(tcg_res
, tcg_res
, tcg_elt
);
7235 tcg_gen_smin_i64(tcg_res
, tcg_res
, tcg_elt
);
7239 g_assert_not_reached();
7244 /* Floating point vector reduction ops which work across 32
7245 * bit (single) or 16 bit (half-precision) intermediates.
7246 * Note that correct NaN propagation requires that we do these
7247 * operations in exactly the order specified by the pseudocode.
7249 TCGv_ptr fpst
= get_fpstatus_ptr(size
== MO_16
);
7250 int fpopcode
= opcode
| is_min
<< 4 | is_u
<< 5;
7251 int vmap
= (1 << elements
) - 1;
7252 TCGv_i32 tcg_res32
= do_reduction_op(s
, fpopcode
, rn
, esize
,
7253 (is_q
? 128 : 64), vmap
, fpst
);
7254 tcg_gen_extu_i32_i64(tcg_res
, tcg_res32
);
7255 tcg_temp_free_i32(tcg_res32
);
7256 tcg_temp_free_ptr(fpst
);
7259 tcg_temp_free_i64(tcg_elt
);
7261 /* Now truncate the result to the width required for the final output */
7262 if (opcode
== 0x03) {
7263 /* SADDLV, UADDLV: result is 2*esize */
7269 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
7272 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
7275 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
7280 g_assert_not_reached();
7283 write_fp_dreg(s
, rd
, tcg_res
);
7284 tcg_temp_free_i64(tcg_res
);
7287 /* DUP (Element, Vector)
7289 * 31 30 29 21 20 16 15 10 9 5 4 0
7290 * +---+---+-------------------+--------+-------------+------+------+
7291 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7292 * +---+---+-------------------+--------+-------------+------+------+
7294 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7296 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
7299 int size
= ctz32(imm5
);
7300 int index
= imm5
>> (size
+ 1);
7302 if (size
> 3 || (size
== 3 && !is_q
)) {
7303 unallocated_encoding(s
);
7307 if (!fp_access_check(s
)) {
7311 tcg_gen_gvec_dup_mem(size
, vec_full_reg_offset(s
, rd
),
7312 vec_reg_offset(s
, rn
, index
, size
),
7313 is_q
? 16 : 8, vec_full_reg_size(s
));
7316 /* DUP (element, scalar)
7317 * 31 21 20 16 15 10 9 5 4 0
7318 * +-----------------------+--------+-------------+------+------+
7319 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7320 * +-----------------------+--------+-------------+------+------+
7322 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
7325 int size
= ctz32(imm5
);
7330 unallocated_encoding(s
);
7334 if (!fp_access_check(s
)) {
7338 index
= imm5
>> (size
+ 1);
7340 /* This instruction just extracts the specified element and
7341 * zero-extends it into the bottom of the destination register.
7343 tmp
= tcg_temp_new_i64();
7344 read_vec_element(s
, tmp
, rn
, index
, size
);
7345 write_fp_dreg(s
, rd
, tmp
);
7346 tcg_temp_free_i64(tmp
);
7351 * 31 30 29 21 20 16 15 10 9 5 4 0
7352 * +---+---+-------------------+--------+-------------+------+------+
7353 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
7354 * +---+---+-------------------+--------+-------------+------+------+
7356 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7358 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
7361 int size
= ctz32(imm5
);
7362 uint32_t dofs
, oprsz
, maxsz
;
7364 if (size
> 3 || ((size
== 3) && !is_q
)) {
7365 unallocated_encoding(s
);
7369 if (!fp_access_check(s
)) {
7373 dofs
= vec_full_reg_offset(s
, rd
);
7374 oprsz
= is_q
? 16 : 8;
7375 maxsz
= vec_full_reg_size(s
);
7377 tcg_gen_gvec_dup_i64(size
, dofs
, oprsz
, maxsz
, cpu_reg(s
, rn
));
7382 * 31 21 20 16 15 14 11 10 9 5 4 0
7383 * +-----------------------+--------+------------+---+------+------+
7384 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7385 * +-----------------------+--------+------------+---+------+------+
7387 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7388 * index: encoded in imm5<4:size+1>
7390 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
7393 int size
= ctz32(imm5
);
7394 int src_index
, dst_index
;
7398 unallocated_encoding(s
);
7402 if (!fp_access_check(s
)) {
7406 dst_index
= extract32(imm5
, 1+size
, 5);
7407 src_index
= extract32(imm4
, size
, 4);
7409 tmp
= tcg_temp_new_i64();
7411 read_vec_element(s
, tmp
, rn
, src_index
, size
);
7412 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
7414 tcg_temp_free_i64(tmp
);
7416 /* INS is considered a 128-bit write for SVE. */
7417 clear_vec_high(s
, true, rd
);
7423 * 31 21 20 16 15 10 9 5 4 0
7424 * +-----------------------+--------+-------------+------+------+
7425 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
7426 * +-----------------------+--------+-------------+------+------+
7428 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7429 * index: encoded in imm5<4:size+1>
7431 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
7433 int size
= ctz32(imm5
);
7437 unallocated_encoding(s
);
7441 if (!fp_access_check(s
)) {
7445 idx
= extract32(imm5
, 1 + size
, 4 - size
);
7446 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
7448 /* INS is considered a 128-bit write for SVE. */
7449 clear_vec_high(s
, true, rd
);
7456 * 31 30 29 21 20 16 15 12 10 9 5 4 0
7457 * +---+---+-------------------+--------+-------------+------+------+
7458 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
7459 * +---+---+-------------------+--------+-------------+------+------+
7461 * U: unsigned when set
7462 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7464 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
7465 int rn
, int rd
, int imm5
)
7467 int size
= ctz32(imm5
);
7471 /* Check for UnallocatedEncodings */
7473 if (size
> 2 || (size
== 2 && !is_q
)) {
7474 unallocated_encoding(s
);
7479 || (size
< 3 && is_q
)
7480 || (size
== 3 && !is_q
)) {
7481 unallocated_encoding(s
);
7486 if (!fp_access_check(s
)) {
7490 element
= extract32(imm5
, 1+size
, 4);
7492 tcg_rd
= cpu_reg(s
, rd
);
7493 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
7494 if (is_signed
&& !is_q
) {
7495 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
7500 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
7501 * +---+---+----+-----------------+------+---+------+---+------+------+
7502 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7503 * +---+---+----+-----------------+------+---+------+---+------+------+
7505 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
7507 int rd
= extract32(insn
, 0, 5);
7508 int rn
= extract32(insn
, 5, 5);
7509 int imm4
= extract32(insn
, 11, 4);
7510 int op
= extract32(insn
, 29, 1);
7511 int is_q
= extract32(insn
, 30, 1);
7512 int imm5
= extract32(insn
, 16, 5);
7517 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
7519 unallocated_encoding(s
);
7524 /* DUP (element - vector) */
7525 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
7529 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
7534 handle_simd_insg(s
, rd
, rn
, imm5
);
7536 unallocated_encoding(s
);
7541 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
7542 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
7545 unallocated_encoding(s
);
7551 /* AdvSIMD modified immediate
7552 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
7553 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
7554 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
7555 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
7557 * There are a number of operations that can be carried out here:
7558 * MOVI - move (shifted) imm into register
7559 * MVNI - move inverted (shifted) imm into register
7560 * ORR - bitwise OR of (shifted) imm with register
7561 * BIC - bitwise clear of (shifted) imm with register
7562 * With ARMv8.2 we also have:
7563 * FMOV half-precision
7565 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
7567 int rd
= extract32(insn
, 0, 5);
7568 int cmode
= extract32(insn
, 12, 4);
7569 int cmode_3_1
= extract32(cmode
, 1, 3);
7570 int cmode_0
= extract32(cmode
, 0, 1);
7571 int o2
= extract32(insn
, 11, 1);
7572 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
7573 bool is_neg
= extract32(insn
, 29, 1);
7574 bool is_q
= extract32(insn
, 30, 1);
7577 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
7578 /* Check for FMOV (vector, immediate) - half-precision */
7579 if (!(dc_isar_feature(aa64_fp16
, s
) && o2
&& cmode
== 0xf)) {
7580 unallocated_encoding(s
);
7585 if (!fp_access_check(s
)) {
7589 /* See AdvSIMDExpandImm() in ARM ARM */
7590 switch (cmode_3_1
) {
7591 case 0: /* Replicate(Zeros(24):imm8, 2) */
7592 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
7593 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
7594 case 3: /* Replicate(imm8:Zeros(24), 2) */
7596 int shift
= cmode_3_1
* 8;
7597 imm
= bitfield_replicate(abcdefgh
<< shift
, 32);
7600 case 4: /* Replicate(Zeros(8):imm8, 4) */
7601 case 5: /* Replicate(imm8:Zeros(8), 4) */
7603 int shift
= (cmode_3_1
& 0x1) * 8;
7604 imm
= bitfield_replicate(abcdefgh
<< shift
, 16);
7609 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
7610 imm
= (abcdefgh
<< 16) | 0xffff;
7612 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
7613 imm
= (abcdefgh
<< 8) | 0xff;
7615 imm
= bitfield_replicate(imm
, 32);
7618 if (!cmode_0
&& !is_neg
) {
7619 imm
= bitfield_replicate(abcdefgh
, 8);
7620 } else if (!cmode_0
&& is_neg
) {
7623 for (i
= 0; i
< 8; i
++) {
7624 if ((abcdefgh
) & (1 << i
)) {
7625 imm
|= 0xffULL
<< (i
* 8);
7628 } else if (cmode_0
) {
7630 imm
= (abcdefgh
& 0x3f) << 48;
7631 if (abcdefgh
& 0x80) {
7632 imm
|= 0x8000000000000000ULL
;
7634 if (abcdefgh
& 0x40) {
7635 imm
|= 0x3fc0000000000000ULL
;
7637 imm
|= 0x4000000000000000ULL
;
7641 /* FMOV (vector, immediate) - half-precision */
7642 imm
= vfp_expand_imm(MO_16
, abcdefgh
);
7643 /* now duplicate across the lanes */
7644 imm
= bitfield_replicate(imm
, 16);
7646 imm
= (abcdefgh
& 0x3f) << 19;
7647 if (abcdefgh
& 0x80) {
7650 if (abcdefgh
& 0x40) {
7661 fprintf(stderr
, "%s: cmode_3_1: %x\n", __func__
, cmode_3_1
);
7662 g_assert_not_reached();
7665 if (cmode_3_1
!= 7 && is_neg
) {
7669 if (!((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9)) {
7670 /* MOVI or MVNI, with MVNI negation handled above. */
7671 tcg_gen_gvec_dup64i(vec_full_reg_offset(s
, rd
), is_q
? 16 : 8,
7672 vec_full_reg_size(s
), imm
);
7674 /* ORR or BIC, with BIC negation to AND handled above. */
7676 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_andi
, MO_64
);
7678 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_ori
, MO_64
);
7683 /* AdvSIMD scalar copy
7684 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
7685 * +-----+----+-----------------+------+---+------+---+------+------+
7686 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7687 * +-----+----+-----------------+------+---+------+---+------+------+
7689 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
7691 int rd
= extract32(insn
, 0, 5);
7692 int rn
= extract32(insn
, 5, 5);
7693 int imm4
= extract32(insn
, 11, 4);
7694 int imm5
= extract32(insn
, 16, 5);
7695 int op
= extract32(insn
, 29, 1);
7697 if (op
!= 0 || imm4
!= 0) {
7698 unallocated_encoding(s
);
7702 /* DUP (element, scalar) */
7703 handle_simd_dupes(s
, rd
, rn
, imm5
);
7706 /* AdvSIMD scalar pairwise
7707 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7708 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7709 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
7710 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7712 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
7714 int u
= extract32(insn
, 29, 1);
7715 int size
= extract32(insn
, 22, 2);
7716 int opcode
= extract32(insn
, 12, 5);
7717 int rn
= extract32(insn
, 5, 5);
7718 int rd
= extract32(insn
, 0, 5);
7721 /* For some ops (the FP ones), size[1] is part of the encoding.
7722 * For ADDP strictly it is not but size[1] is always 1 for valid
7725 opcode
|= (extract32(size
, 1, 1) << 5);
7728 case 0x3b: /* ADDP */
7729 if (u
|| size
!= 3) {
7730 unallocated_encoding(s
);
7733 if (!fp_access_check(s
)) {
7739 case 0xc: /* FMAXNMP */
7740 case 0xd: /* FADDP */
7741 case 0xf: /* FMAXP */
7742 case 0x2c: /* FMINNMP */
7743 case 0x2f: /* FMINP */
7744 /* FP op, size[0] is 32 or 64 bit*/
7746 if (!dc_isar_feature(aa64_fp16
, s
)) {
7747 unallocated_encoding(s
);
7753 size
= extract32(size
, 0, 1) ? MO_64
: MO_32
;
7756 if (!fp_access_check(s
)) {
7760 fpst
= get_fpstatus_ptr(size
== MO_16
);
7763 unallocated_encoding(s
);
7767 if (size
== MO_64
) {
7768 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7769 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7770 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7772 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
7773 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
7776 case 0x3b: /* ADDP */
7777 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
7779 case 0xc: /* FMAXNMP */
7780 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7782 case 0xd: /* FADDP */
7783 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7785 case 0xf: /* FMAXP */
7786 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7788 case 0x2c: /* FMINNMP */
7789 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7791 case 0x2f: /* FMINP */
7792 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7795 g_assert_not_reached();
7798 write_fp_dreg(s
, rd
, tcg_res
);
7800 tcg_temp_free_i64(tcg_op1
);
7801 tcg_temp_free_i64(tcg_op2
);
7802 tcg_temp_free_i64(tcg_res
);
7804 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
7805 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7806 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7808 read_vec_element_i32(s
, tcg_op1
, rn
, 0, size
);
7809 read_vec_element_i32(s
, tcg_op2
, rn
, 1, size
);
7811 if (size
== MO_16
) {
7813 case 0xc: /* FMAXNMP */
7814 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7816 case 0xd: /* FADDP */
7817 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7819 case 0xf: /* FMAXP */
7820 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7822 case 0x2c: /* FMINNMP */
7823 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7825 case 0x2f: /* FMINP */
7826 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7829 g_assert_not_reached();
7833 case 0xc: /* FMAXNMP */
7834 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7836 case 0xd: /* FADDP */
7837 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7839 case 0xf: /* FMAXP */
7840 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7842 case 0x2c: /* FMINNMP */
7843 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7845 case 0x2f: /* FMINP */
7846 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7849 g_assert_not_reached();
7853 write_fp_sreg(s
, rd
, tcg_res
);
7855 tcg_temp_free_i32(tcg_op1
);
7856 tcg_temp_free_i32(tcg_op2
);
7857 tcg_temp_free_i32(tcg_res
);
7861 tcg_temp_free_ptr(fpst
);
7866 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
7868 * This code is handles the common shifting code and is used by both
7869 * the vector and scalar code.
7871 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
7872 TCGv_i64 tcg_rnd
, bool accumulate
,
7873 bool is_u
, int size
, int shift
)
7875 bool extended_result
= false;
7876 bool round
= tcg_rnd
!= NULL
;
7878 TCGv_i64 tcg_src_hi
;
7880 if (round
&& size
== 3) {
7881 extended_result
= true;
7882 ext_lshift
= 64 - shift
;
7883 tcg_src_hi
= tcg_temp_new_i64();
7884 } else if (shift
== 64) {
7885 if (!accumulate
&& is_u
) {
7886 /* result is zero */
7887 tcg_gen_movi_i64(tcg_res
, 0);
7892 /* Deal with the rounding step */
7894 if (extended_result
) {
7895 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7897 /* take care of sign extending tcg_res */
7898 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
7899 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
7900 tcg_src
, tcg_src_hi
,
7903 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
7907 tcg_temp_free_i64(tcg_zero
);
7909 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
7913 /* Now do the shift right */
7914 if (round
&& extended_result
) {
7915 /* extended case, >64 bit precision required */
7916 if (ext_lshift
== 0) {
7917 /* special case, only high bits matter */
7918 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
7920 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
7921 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
7922 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
7927 /* essentially shifting in 64 zeros */
7928 tcg_gen_movi_i64(tcg_src
, 0);
7930 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
7934 /* effectively extending the sign-bit */
7935 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
7937 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
7943 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
7945 tcg_gen_mov_i64(tcg_res
, tcg_src
);
7948 if (extended_result
) {
7949 tcg_temp_free_i64(tcg_src_hi
);
7953 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
7954 static void handle_scalar_simd_shri(DisasContext
*s
,
7955 bool is_u
, int immh
, int immb
,
7956 int opcode
, int rn
, int rd
)
7959 int immhb
= immh
<< 3 | immb
;
7960 int shift
= 2 * (8 << size
) - immhb
;
7961 bool accumulate
= false;
7963 bool insert
= false;
7968 if (!extract32(immh
, 3, 1)) {
7969 unallocated_encoding(s
);
7973 if (!fp_access_check(s
)) {
7978 case 0x02: /* SSRA / USRA (accumulate) */
7981 case 0x04: /* SRSHR / URSHR (rounding) */
7984 case 0x06: /* SRSRA / URSRA (accum + rounding) */
7985 accumulate
= round
= true;
7987 case 0x08: /* SRI */
7993 uint64_t round_const
= 1ULL << (shift
- 1);
7994 tcg_round
= tcg_const_i64(round_const
);
7999 tcg_rn
= read_fp_dreg(s
, rn
);
8000 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
8003 /* shift count same as element size is valid but does nothing;
8004 * special case to avoid potential shift by 64.
8006 int esize
= 8 << size
;
8007 if (shift
!= esize
) {
8008 tcg_gen_shri_i64(tcg_rn
, tcg_rn
, shift
);
8009 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, 0, esize
- shift
);
8012 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8013 accumulate
, is_u
, size
, shift
);
8016 write_fp_dreg(s
, rd
, tcg_rd
);
8018 tcg_temp_free_i64(tcg_rn
);
8019 tcg_temp_free_i64(tcg_rd
);
8021 tcg_temp_free_i64(tcg_round
);
8025 /* SHL/SLI - Scalar shift left */
8026 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
8027 int immh
, int immb
, int opcode
,
8030 int size
= 32 - clz32(immh
) - 1;
8031 int immhb
= immh
<< 3 | immb
;
8032 int shift
= immhb
- (8 << size
);
8033 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8034 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8036 if (!extract32(immh
, 3, 1)) {
8037 unallocated_encoding(s
);
8041 if (!fp_access_check(s
)) {
8045 tcg_rn
= read_fp_dreg(s
, rn
);
8046 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
8049 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, shift
, 64 - shift
);
8051 tcg_gen_shli_i64(tcg_rd
, tcg_rn
, shift
);
8054 write_fp_dreg(s
, rd
, tcg_rd
);
8056 tcg_temp_free_i64(tcg_rn
);
8057 tcg_temp_free_i64(tcg_rd
);
8060 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
8061 * (signed/unsigned) narrowing */
8062 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
8063 bool is_u_shift
, bool is_u_narrow
,
8064 int immh
, int immb
, int opcode
,
8067 int immhb
= immh
<< 3 | immb
;
8068 int size
= 32 - clz32(immh
) - 1;
8069 int esize
= 8 << size
;
8070 int shift
= (2 * esize
) - immhb
;
8071 int elements
= is_scalar
? 1 : (64 / esize
);
8072 bool round
= extract32(opcode
, 0, 1);
8073 MemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
8074 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
8075 TCGv_i32 tcg_rd_narrowed
;
8078 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
8079 { gen_helper_neon_narrow_sat_s8
,
8080 gen_helper_neon_unarrow_sat8
},
8081 { gen_helper_neon_narrow_sat_s16
,
8082 gen_helper_neon_unarrow_sat16
},
8083 { gen_helper_neon_narrow_sat_s32
,
8084 gen_helper_neon_unarrow_sat32
},
8087 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
8088 gen_helper_neon_narrow_sat_u8
,
8089 gen_helper_neon_narrow_sat_u16
,
8090 gen_helper_neon_narrow_sat_u32
,
8093 NeonGenNarrowEnvFn
*narrowfn
;
8099 if (extract32(immh
, 3, 1)) {
8100 unallocated_encoding(s
);
8104 if (!fp_access_check(s
)) {
8109 narrowfn
= unsigned_narrow_fns
[size
];
8111 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
8114 tcg_rn
= tcg_temp_new_i64();
8115 tcg_rd
= tcg_temp_new_i64();
8116 tcg_rd_narrowed
= tcg_temp_new_i32();
8117 tcg_final
= tcg_const_i64(0);
8120 uint64_t round_const
= 1ULL << (shift
- 1);
8121 tcg_round
= tcg_const_i64(round_const
);
8126 for (i
= 0; i
< elements
; i
++) {
8127 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
8128 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8129 false, is_u_shift
, size
+1, shift
);
8130 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
8131 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
8132 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
8136 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
8138 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
8142 tcg_temp_free_i64(tcg_round
);
8144 tcg_temp_free_i64(tcg_rn
);
8145 tcg_temp_free_i64(tcg_rd
);
8146 tcg_temp_free_i32(tcg_rd_narrowed
);
8147 tcg_temp_free_i64(tcg_final
);
8149 clear_vec_high(s
, is_q
, rd
);
8152 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
8153 static void handle_simd_qshl(DisasContext
*s
, bool scalar
, bool is_q
,
8154 bool src_unsigned
, bool dst_unsigned
,
8155 int immh
, int immb
, int rn
, int rd
)
8157 int immhb
= immh
<< 3 | immb
;
8158 int size
= 32 - clz32(immh
) - 1;
8159 int shift
= immhb
- (8 << size
);
8163 assert(!(scalar
&& is_q
));
8166 if (!is_q
&& extract32(immh
, 3, 1)) {
8167 unallocated_encoding(s
);
8171 /* Since we use the variable-shift helpers we must
8172 * replicate the shift count into each element of
8173 * the tcg_shift value.
8177 shift
|= shift
<< 8;
8180 shift
|= shift
<< 16;
8186 g_assert_not_reached();
8190 if (!fp_access_check(s
)) {
8195 TCGv_i64 tcg_shift
= tcg_const_i64(shift
);
8196 static NeonGenTwo64OpEnvFn
* const fns
[2][2] = {
8197 { gen_helper_neon_qshl_s64
, gen_helper_neon_qshlu_s64
},
8198 { NULL
, gen_helper_neon_qshl_u64
},
8200 NeonGenTwo64OpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
];
8201 int maxpass
= is_q
? 2 : 1;
8203 for (pass
= 0; pass
< maxpass
; pass
++) {
8204 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8206 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8207 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
8208 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
8210 tcg_temp_free_i64(tcg_op
);
8212 tcg_temp_free_i64(tcg_shift
);
8213 clear_vec_high(s
, is_q
, rd
);
8215 TCGv_i32 tcg_shift
= tcg_const_i32(shift
);
8216 static NeonGenTwoOpEnvFn
* const fns
[2][2][3] = {
8218 { gen_helper_neon_qshl_s8
,
8219 gen_helper_neon_qshl_s16
,
8220 gen_helper_neon_qshl_s32
},
8221 { gen_helper_neon_qshlu_s8
,
8222 gen_helper_neon_qshlu_s16
,
8223 gen_helper_neon_qshlu_s32
}
8225 { NULL
, NULL
, NULL
},
8226 { gen_helper_neon_qshl_u8
,
8227 gen_helper_neon_qshl_u16
,
8228 gen_helper_neon_qshl_u32
}
8231 NeonGenTwoOpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
][size
];
8232 MemOp memop
= scalar
? size
: MO_32
;
8233 int maxpass
= scalar
? 1 : is_q
? 4 : 2;
8235 for (pass
= 0; pass
< maxpass
; pass
++) {
8236 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8238 read_vec_element_i32(s
, tcg_op
, rn
, pass
, memop
);
8239 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
8243 tcg_gen_ext8u_i32(tcg_op
, tcg_op
);
8246 tcg_gen_ext16u_i32(tcg_op
, tcg_op
);
8251 g_assert_not_reached();
8253 write_fp_sreg(s
, rd
, tcg_op
);
8255 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
8258 tcg_temp_free_i32(tcg_op
);
8260 tcg_temp_free_i32(tcg_shift
);
8263 clear_vec_high(s
, is_q
, rd
);
8268 /* Common vector code for handling integer to FP conversion */
8269 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
8270 int elements
, int is_signed
,
8271 int fracbits
, int size
)
8273 TCGv_ptr tcg_fpst
= get_fpstatus_ptr(size
== MO_16
);
8274 TCGv_i32 tcg_shift
= NULL
;
8276 MemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
8279 if (fracbits
|| size
== MO_64
) {
8280 tcg_shift
= tcg_const_i32(fracbits
);
8283 if (size
== MO_64
) {
8284 TCGv_i64 tcg_int64
= tcg_temp_new_i64();
8285 TCGv_i64 tcg_double
= tcg_temp_new_i64();
8287 for (pass
= 0; pass
< elements
; pass
++) {
8288 read_vec_element(s
, tcg_int64
, rn
, pass
, mop
);
8291 gen_helper_vfp_sqtod(tcg_double
, tcg_int64
,
8292 tcg_shift
, tcg_fpst
);
8294 gen_helper_vfp_uqtod(tcg_double
, tcg_int64
,
8295 tcg_shift
, tcg_fpst
);
8297 if (elements
== 1) {
8298 write_fp_dreg(s
, rd
, tcg_double
);
8300 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
8304 tcg_temp_free_i64(tcg_int64
);
8305 tcg_temp_free_i64(tcg_double
);
8308 TCGv_i32 tcg_int32
= tcg_temp_new_i32();
8309 TCGv_i32 tcg_float
= tcg_temp_new_i32();
8311 for (pass
= 0; pass
< elements
; pass
++) {
8312 read_vec_element_i32(s
, tcg_int32
, rn
, pass
, mop
);
8318 gen_helper_vfp_sltos(tcg_float
, tcg_int32
,
8319 tcg_shift
, tcg_fpst
);
8321 gen_helper_vfp_ultos(tcg_float
, tcg_int32
,
8322 tcg_shift
, tcg_fpst
);
8326 gen_helper_vfp_sitos(tcg_float
, tcg_int32
, tcg_fpst
);
8328 gen_helper_vfp_uitos(tcg_float
, tcg_int32
, tcg_fpst
);
8335 gen_helper_vfp_sltoh(tcg_float
, tcg_int32
,
8336 tcg_shift
, tcg_fpst
);
8338 gen_helper_vfp_ultoh(tcg_float
, tcg_int32
,
8339 tcg_shift
, tcg_fpst
);
8343 gen_helper_vfp_sitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8345 gen_helper_vfp_uitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8350 g_assert_not_reached();
8353 if (elements
== 1) {
8354 write_fp_sreg(s
, rd
, tcg_float
);
8356 write_vec_element_i32(s
, tcg_float
, rd
, pass
, size
);
8360 tcg_temp_free_i32(tcg_int32
);
8361 tcg_temp_free_i32(tcg_float
);
8364 tcg_temp_free_ptr(tcg_fpst
);
8366 tcg_temp_free_i32(tcg_shift
);
8369 clear_vec_high(s
, elements
<< size
== 16, rd
);
8372 /* UCVTF/SCVTF - Integer to FP conversion */
8373 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
8374 bool is_q
, bool is_u
,
8375 int immh
, int immb
, int opcode
,
8378 int size
, elements
, fracbits
;
8379 int immhb
= immh
<< 3 | immb
;
8383 if (!is_scalar
&& !is_q
) {
8384 unallocated_encoding(s
);
8387 } else if (immh
& 4) {
8389 } else if (immh
& 2) {
8391 if (!dc_isar_feature(aa64_fp16
, s
)) {
8392 unallocated_encoding(s
);
8396 /* immh == 0 would be a failure of the decode logic */
8397 g_assert(immh
== 1);
8398 unallocated_encoding(s
);
8405 elements
= (8 << is_q
) >> size
;
8407 fracbits
= (16 << size
) - immhb
;
8409 if (!fp_access_check(s
)) {
8413 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
8416 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
8417 static void handle_simd_shift_fpint_conv(DisasContext
*s
, bool is_scalar
,
8418 bool is_q
, bool is_u
,
8419 int immh
, int immb
, int rn
, int rd
)
8421 int immhb
= immh
<< 3 | immb
;
8422 int pass
, size
, fracbits
;
8423 TCGv_ptr tcg_fpstatus
;
8424 TCGv_i32 tcg_rmode
, tcg_shift
;
8428 if (!is_scalar
&& !is_q
) {
8429 unallocated_encoding(s
);
8432 } else if (immh
& 0x4) {
8434 } else if (immh
& 0x2) {
8436 if (!dc_isar_feature(aa64_fp16
, s
)) {
8437 unallocated_encoding(s
);
8441 /* Should have split out AdvSIMD modified immediate earlier. */
8443 unallocated_encoding(s
);
8447 if (!fp_access_check(s
)) {
8451 assert(!(is_scalar
&& is_q
));
8453 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO
));
8454 tcg_fpstatus
= get_fpstatus_ptr(size
== MO_16
);
8455 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
8456 fracbits
= (16 << size
) - immhb
;
8457 tcg_shift
= tcg_const_i32(fracbits
);
8459 if (size
== MO_64
) {
8460 int maxpass
= is_scalar
? 1 : 2;
8462 for (pass
= 0; pass
< maxpass
; pass
++) {
8463 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8465 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8467 gen_helper_vfp_touqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8469 gen_helper_vfp_tosqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8471 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
8472 tcg_temp_free_i64(tcg_op
);
8474 clear_vec_high(s
, is_q
, rd
);
8476 void (*fn
)(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
8477 int maxpass
= is_scalar
? 1 : ((8 << is_q
) >> size
);
8482 fn
= gen_helper_vfp_touhh
;
8484 fn
= gen_helper_vfp_toshh
;
8489 fn
= gen_helper_vfp_touls
;
8491 fn
= gen_helper_vfp_tosls
;
8495 g_assert_not_reached();
8498 for (pass
= 0; pass
< maxpass
; pass
++) {
8499 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8501 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
8502 fn(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8504 write_fp_sreg(s
, rd
, tcg_op
);
8506 write_vec_element_i32(s
, tcg_op
, rd
, pass
, size
);
8508 tcg_temp_free_i32(tcg_op
);
8511 clear_vec_high(s
, is_q
, rd
);
8515 tcg_temp_free_ptr(tcg_fpstatus
);
8516 tcg_temp_free_i32(tcg_shift
);
8517 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
8518 tcg_temp_free_i32(tcg_rmode
);
8521 /* AdvSIMD scalar shift by immediate
8522 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
8523 * +-----+---+-------------+------+------+--------+---+------+------+
8524 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
8525 * +-----+---+-------------+------+------+--------+---+------+------+
8527 * This is the scalar version so it works on a fixed sized registers
8529 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
8531 int rd
= extract32(insn
, 0, 5);
8532 int rn
= extract32(insn
, 5, 5);
8533 int opcode
= extract32(insn
, 11, 5);
8534 int immb
= extract32(insn
, 16, 3);
8535 int immh
= extract32(insn
, 19, 4);
8536 bool is_u
= extract32(insn
, 29, 1);
8539 unallocated_encoding(s
);
8544 case 0x08: /* SRI */
8546 unallocated_encoding(s
);
8550 case 0x00: /* SSHR / USHR */
8551 case 0x02: /* SSRA / USRA */
8552 case 0x04: /* SRSHR / URSHR */
8553 case 0x06: /* SRSRA / URSRA */
8554 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8556 case 0x0a: /* SHL / SLI */
8557 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8559 case 0x1c: /* SCVTF, UCVTF */
8560 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
8563 case 0x10: /* SQSHRUN, SQSHRUN2 */
8564 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
8566 unallocated_encoding(s
);
8569 handle_vec_simd_sqshrn(s
, true, false, false, true,
8570 immh
, immb
, opcode
, rn
, rd
);
8572 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
8573 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
8574 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
8575 immh
, immb
, opcode
, rn
, rd
);
8577 case 0xc: /* SQSHLU */
8579 unallocated_encoding(s
);
8582 handle_simd_qshl(s
, true, false, false, true, immh
, immb
, rn
, rd
);
8584 case 0xe: /* SQSHL, UQSHL */
8585 handle_simd_qshl(s
, true, false, is_u
, is_u
, immh
, immb
, rn
, rd
);
8587 case 0x1f: /* FCVTZS, FCVTZU */
8588 handle_simd_shift_fpint_conv(s
, true, false, is_u
, immh
, immb
, rn
, rd
);
8591 unallocated_encoding(s
);
8596 /* AdvSIMD scalar three different
8597 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
8598 * +-----+---+-----------+------+---+------+--------+-----+------+------+
8599 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
8600 * +-----+---+-----------+------+---+------+--------+-----+------+------+
8602 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
8604 bool is_u
= extract32(insn
, 29, 1);
8605 int size
= extract32(insn
, 22, 2);
8606 int opcode
= extract32(insn
, 12, 4);
8607 int rm
= extract32(insn
, 16, 5);
8608 int rn
= extract32(insn
, 5, 5);
8609 int rd
= extract32(insn
, 0, 5);
8612 unallocated_encoding(s
);
8617 case 0x9: /* SQDMLAL, SQDMLAL2 */
8618 case 0xb: /* SQDMLSL, SQDMLSL2 */
8619 case 0xd: /* SQDMULL, SQDMULL2 */
8620 if (size
== 0 || size
== 3) {
8621 unallocated_encoding(s
);
8626 unallocated_encoding(s
);
8630 if (!fp_access_check(s
)) {
8635 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8636 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8637 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8639 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
8640 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
8642 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
8643 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
8646 case 0xd: /* SQDMULL, SQDMULL2 */
8648 case 0xb: /* SQDMLSL, SQDMLSL2 */
8649 tcg_gen_neg_i64(tcg_res
, tcg_res
);
8651 case 0x9: /* SQDMLAL, SQDMLAL2 */
8652 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
8653 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
8657 g_assert_not_reached();
8660 write_fp_dreg(s
, rd
, tcg_res
);
8662 tcg_temp_free_i64(tcg_op1
);
8663 tcg_temp_free_i64(tcg_op2
);
8664 tcg_temp_free_i64(tcg_res
);
8666 TCGv_i32 tcg_op1
= read_fp_hreg(s
, rn
);
8667 TCGv_i32 tcg_op2
= read_fp_hreg(s
, rm
);
8668 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8670 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
8671 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
8674 case 0xd: /* SQDMULL, SQDMULL2 */
8676 case 0xb: /* SQDMLSL, SQDMLSL2 */
8677 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
8679 case 0x9: /* SQDMLAL, SQDMLAL2 */
8681 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
8682 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
8683 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
8685 tcg_temp_free_i64(tcg_op3
);
8689 g_assert_not_reached();
8692 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
8693 write_fp_dreg(s
, rd
, tcg_res
);
8695 tcg_temp_free_i32(tcg_op1
);
8696 tcg_temp_free_i32(tcg_op2
);
8697 tcg_temp_free_i64(tcg_res
);
8701 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
8702 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
8704 /* Handle 64x64->64 opcodes which are shared between the scalar
8705 * and vector 3-same groups. We cover every opcode where size == 3
8706 * is valid in either the three-reg-same (integer, not pairwise)
8707 * or scalar-three-reg-same groups.
8712 case 0x1: /* SQADD */
8714 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8716 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8719 case 0x5: /* SQSUB */
8721 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8723 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8726 case 0x6: /* CMGT, CMHI */
8727 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
8728 * We implement this using setcond (test) and then negating.
8730 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
8732 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
8733 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
8735 case 0x7: /* CMGE, CMHS */
8736 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
8738 case 0x11: /* CMTST, CMEQ */
8743 gen_cmtst_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8745 case 0x8: /* SSHL, USHL */
8747 gen_ushl_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8749 gen_sshl_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8752 case 0x9: /* SQSHL, UQSHL */
8754 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8756 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8759 case 0xa: /* SRSHL, URSHL */
8761 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
8763 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
8766 case 0xb: /* SQRSHL, UQRSHL */
8768 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8770 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8773 case 0x10: /* ADD, SUB */
8775 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8777 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8781 g_assert_not_reached();
8785 /* Handle the 3-same-operands float operations; shared by the scalar
8786 * and vector encodings. The caller must filter out any encodings
8787 * not allocated for the encoding it is dealing with.
8789 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
8790 int fpopcode
, int rd
, int rn
, int rm
)
8793 TCGv_ptr fpst
= get_fpstatus_ptr(false);
8795 for (pass
= 0; pass
< elements
; pass
++) {
8798 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8799 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8800 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8802 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8803 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8806 case 0x39: /* FMLS */
8807 /* As usual for ARM, separate negation for fused multiply-add */
8808 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
8810 case 0x19: /* FMLA */
8811 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8812 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
8815 case 0x18: /* FMAXNM */
8816 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8818 case 0x1a: /* FADD */
8819 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8821 case 0x1b: /* FMULX */
8822 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8824 case 0x1c: /* FCMEQ */
8825 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8827 case 0x1e: /* FMAX */
8828 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8830 case 0x1f: /* FRECPS */
8831 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8833 case 0x38: /* FMINNM */
8834 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8836 case 0x3a: /* FSUB */
8837 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8839 case 0x3e: /* FMIN */
8840 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8842 case 0x3f: /* FRSQRTS */
8843 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8845 case 0x5b: /* FMUL */
8846 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8848 case 0x5c: /* FCMGE */
8849 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8851 case 0x5d: /* FACGE */
8852 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8854 case 0x5f: /* FDIV */
8855 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8857 case 0x7a: /* FABD */
8858 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8859 gen_helper_vfp_absd(tcg_res
, tcg_res
);
8861 case 0x7c: /* FCMGT */
8862 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8864 case 0x7d: /* FACGT */
8865 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8868 g_assert_not_reached();
8871 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8873 tcg_temp_free_i64(tcg_res
);
8874 tcg_temp_free_i64(tcg_op1
);
8875 tcg_temp_free_i64(tcg_op2
);
8878 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8879 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8880 TCGv_i32 tcg_res
= tcg_temp_new_i32();
8882 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
8883 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
8886 case 0x39: /* FMLS */
8887 /* As usual for ARM, separate negation for fused multiply-add */
8888 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
8890 case 0x19: /* FMLA */
8891 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
8892 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
8895 case 0x1a: /* FADD */
8896 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8898 case 0x1b: /* FMULX */
8899 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8901 case 0x1c: /* FCMEQ */
8902 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8904 case 0x1e: /* FMAX */
8905 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8907 case 0x1f: /* FRECPS */
8908 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8910 case 0x18: /* FMAXNM */
8911 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8913 case 0x38: /* FMINNM */
8914 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8916 case 0x3a: /* FSUB */
8917 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8919 case 0x3e: /* FMIN */
8920 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8922 case 0x3f: /* FRSQRTS */
8923 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8925 case 0x5b: /* FMUL */
8926 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8928 case 0x5c: /* FCMGE */
8929 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8931 case 0x5d: /* FACGE */
8932 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8934 case 0x5f: /* FDIV */
8935 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8937 case 0x7a: /* FABD */
8938 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8939 gen_helper_vfp_abss(tcg_res
, tcg_res
);
8941 case 0x7c: /* FCMGT */
8942 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8944 case 0x7d: /* FACGT */
8945 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8948 g_assert_not_reached();
8951 if (elements
== 1) {
8952 /* scalar single so clear high part */
8953 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
8955 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
8956 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
8957 tcg_temp_free_i64(tcg_tmp
);
8959 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
8962 tcg_temp_free_i32(tcg_res
);
8963 tcg_temp_free_i32(tcg_op1
);
8964 tcg_temp_free_i32(tcg_op2
);
8968 tcg_temp_free_ptr(fpst
);
8970 clear_vec_high(s
, elements
* (size
? 8 : 4) > 8, rd
);
8973 /* AdvSIMD scalar three same
8974 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
8975 * +-----+---+-----------+------+---+------+--------+---+------+------+
8976 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
8977 * +-----+---+-----------+------+---+------+--------+---+------+------+
8979 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
8981 int rd
= extract32(insn
, 0, 5);
8982 int rn
= extract32(insn
, 5, 5);
8983 int opcode
= extract32(insn
, 11, 5);
8984 int rm
= extract32(insn
, 16, 5);
8985 int size
= extract32(insn
, 22, 2);
8986 bool u
= extract32(insn
, 29, 1);
8989 if (opcode
>= 0x18) {
8990 /* Floating point: U, size[1] and opcode indicate operation */
8991 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
8993 case 0x1b: /* FMULX */
8994 case 0x1f: /* FRECPS */
8995 case 0x3f: /* FRSQRTS */
8996 case 0x5d: /* FACGE */
8997 case 0x7d: /* FACGT */
8998 case 0x1c: /* FCMEQ */
8999 case 0x5c: /* FCMGE */
9000 case 0x7c: /* FCMGT */
9001 case 0x7a: /* FABD */
9004 unallocated_encoding(s
);
9008 if (!fp_access_check(s
)) {
9012 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
9017 case 0x1: /* SQADD, UQADD */
9018 case 0x5: /* SQSUB, UQSUB */
9019 case 0x9: /* SQSHL, UQSHL */
9020 case 0xb: /* SQRSHL, UQRSHL */
9022 case 0x8: /* SSHL, USHL */
9023 case 0xa: /* SRSHL, URSHL */
9024 case 0x6: /* CMGT, CMHI */
9025 case 0x7: /* CMGE, CMHS */
9026 case 0x11: /* CMTST, CMEQ */
9027 case 0x10: /* ADD, SUB (vector) */
9029 unallocated_encoding(s
);
9033 case 0x16: /* SQDMULH, SQRDMULH (vector) */
9034 if (size
!= 1 && size
!= 2) {
9035 unallocated_encoding(s
);
9040 unallocated_encoding(s
);
9044 if (!fp_access_check(s
)) {
9048 tcg_rd
= tcg_temp_new_i64();
9051 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
9052 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
9054 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
9055 tcg_temp_free_i64(tcg_rn
);
9056 tcg_temp_free_i64(tcg_rm
);
9058 /* Do a single operation on the lowest element in the vector.
9059 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
9060 * no side effects for all these operations.
9061 * OPTME: special-purpose helpers would avoid doing some
9062 * unnecessary work in the helper for the 8 and 16 bit cases.
9064 NeonGenTwoOpEnvFn
*genenvfn
;
9065 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9066 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
9067 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
9069 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
9070 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
9073 case 0x1: /* SQADD, UQADD */
9075 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9076 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
9077 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
9078 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
9080 genenvfn
= fns
[size
][u
];
9083 case 0x5: /* SQSUB, UQSUB */
9085 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9086 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
9087 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
9088 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
9090 genenvfn
= fns
[size
][u
];
9093 case 0x9: /* SQSHL, UQSHL */
9095 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9096 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
9097 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
9098 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
9100 genenvfn
= fns
[size
][u
];
9103 case 0xb: /* SQRSHL, UQRSHL */
9105 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9106 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
9107 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
9108 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
9110 genenvfn
= fns
[size
][u
];
9113 case 0x16: /* SQDMULH, SQRDMULH */
9115 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
9116 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
9117 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
9119 assert(size
== 1 || size
== 2);
9120 genenvfn
= fns
[size
- 1][u
];
9124 g_assert_not_reached();
9127 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
9128 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
9129 tcg_temp_free_i32(tcg_rd32
);
9130 tcg_temp_free_i32(tcg_rn
);
9131 tcg_temp_free_i32(tcg_rm
);
9134 write_fp_dreg(s
, rd
, tcg_rd
);
9136 tcg_temp_free_i64(tcg_rd
);
9139 /* AdvSIMD scalar three same FP16
9140 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
9141 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
9142 * | 0 1 | U | 1 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
9143 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
9144 * v: 0101 1110 0100 0000 0000 0100 0000 0000 => 5e400400
9145 * m: 1101 1111 0110 0000 1100 0100 0000 0000 => df60c400
9147 static void disas_simd_scalar_three_reg_same_fp16(DisasContext
*s
,
9150 int rd
= extract32(insn
, 0, 5);
9151 int rn
= extract32(insn
, 5, 5);
9152 int opcode
= extract32(insn
, 11, 3);
9153 int rm
= extract32(insn
, 16, 5);
9154 bool u
= extract32(insn
, 29, 1);
9155 bool a
= extract32(insn
, 23, 1);
9156 int fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
9163 case 0x03: /* FMULX */
9164 case 0x04: /* FCMEQ (reg) */
9165 case 0x07: /* FRECPS */
9166 case 0x0f: /* FRSQRTS */
9167 case 0x14: /* FCMGE (reg) */
9168 case 0x15: /* FACGE */
9169 case 0x1a: /* FABD */
9170 case 0x1c: /* FCMGT (reg) */
9171 case 0x1d: /* FACGT */
9174 unallocated_encoding(s
);
9178 if (!dc_isar_feature(aa64_fp16
, s
)) {
9179 unallocated_encoding(s
);
9182 if (!fp_access_check(s
)) {
9186 fpst
= get_fpstatus_ptr(true);
9188 tcg_op1
= read_fp_hreg(s
, rn
);
9189 tcg_op2
= read_fp_hreg(s
, rm
);
9190 tcg_res
= tcg_temp_new_i32();
9193 case 0x03: /* FMULX */
9194 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9196 case 0x04: /* FCMEQ (reg) */
9197 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9199 case 0x07: /* FRECPS */
9200 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9202 case 0x0f: /* FRSQRTS */
9203 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9205 case 0x14: /* FCMGE (reg) */
9206 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9208 case 0x15: /* FACGE */
9209 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9211 case 0x1a: /* FABD */
9212 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9213 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
9215 case 0x1c: /* FCMGT (reg) */
9216 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9218 case 0x1d: /* FACGT */
9219 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9222 g_assert_not_reached();
9225 write_fp_sreg(s
, rd
, tcg_res
);
9228 tcg_temp_free_i32(tcg_res
);
9229 tcg_temp_free_i32(tcg_op1
);
9230 tcg_temp_free_i32(tcg_op2
);
9231 tcg_temp_free_ptr(fpst
);
9234 /* AdvSIMD scalar three same extra
9235 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
9236 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9237 * | 0 1 | U | 1 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
9238 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9240 static void disas_simd_scalar_three_reg_same_extra(DisasContext
*s
,
9243 int rd
= extract32(insn
, 0, 5);
9244 int rn
= extract32(insn
, 5, 5);
9245 int opcode
= extract32(insn
, 11, 4);
9246 int rm
= extract32(insn
, 16, 5);
9247 int size
= extract32(insn
, 22, 2);
9248 bool u
= extract32(insn
, 29, 1);
9249 TCGv_i32 ele1
, ele2
, ele3
;
9253 switch (u
* 16 + opcode
) {
9254 case 0x10: /* SQRDMLAH (vector) */
9255 case 0x11: /* SQRDMLSH (vector) */
9256 if (size
!= 1 && size
!= 2) {
9257 unallocated_encoding(s
);
9260 feature
= dc_isar_feature(aa64_rdm
, s
);
9263 unallocated_encoding(s
);
9267 unallocated_encoding(s
);
9270 if (!fp_access_check(s
)) {
9274 /* Do a single operation on the lowest element in the vector.
9275 * We use the standard Neon helpers and rely on 0 OP 0 == 0
9276 * with no side effects for all these operations.
9277 * OPTME: special-purpose helpers would avoid doing some
9278 * unnecessary work in the helper for the 16 bit cases.
9280 ele1
= tcg_temp_new_i32();
9281 ele2
= tcg_temp_new_i32();
9282 ele3
= tcg_temp_new_i32();
9284 read_vec_element_i32(s
, ele1
, rn
, 0, size
);
9285 read_vec_element_i32(s
, ele2
, rm
, 0, size
);
9286 read_vec_element_i32(s
, ele3
, rd
, 0, size
);
9289 case 0x0: /* SQRDMLAH */
9291 gen_helper_neon_qrdmlah_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9293 gen_helper_neon_qrdmlah_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9296 case 0x1: /* SQRDMLSH */
9298 gen_helper_neon_qrdmlsh_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9300 gen_helper_neon_qrdmlsh_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9304 g_assert_not_reached();
9306 tcg_temp_free_i32(ele1
);
9307 tcg_temp_free_i32(ele2
);
9309 res
= tcg_temp_new_i64();
9310 tcg_gen_extu_i32_i64(res
, ele3
);
9311 tcg_temp_free_i32(ele3
);
9313 write_fp_dreg(s
, rd
, res
);
9314 tcg_temp_free_i64(res
);
9317 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
9318 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
9319 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
9321 /* Handle 64->64 opcodes which are shared between the scalar and
9322 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
9323 * is valid in either group and also the double-precision fp ops.
9324 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
9330 case 0x4: /* CLS, CLZ */
9332 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
9334 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
9338 /* This opcode is shared with CNT and RBIT but we have earlier
9339 * enforced that size == 3 if and only if this is the NOT insn.
9341 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
9343 case 0x7: /* SQABS, SQNEG */
9345 gen_helper_neon_qneg_s64(tcg_rd
, cpu_env
, tcg_rn
);
9347 gen_helper_neon_qabs_s64(tcg_rd
, cpu_env
, tcg_rn
);
9350 case 0xa: /* CMLT */
9351 /* 64 bit integer comparison against zero, result is
9352 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
9357 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
9358 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
9360 case 0x8: /* CMGT, CMGE */
9361 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
9363 case 0x9: /* CMEQ, CMLE */
9364 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
9366 case 0xb: /* ABS, NEG */
9368 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
9370 tcg_gen_abs_i64(tcg_rd
, tcg_rn
);
9373 case 0x2f: /* FABS */
9374 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
9376 case 0x6f: /* FNEG */
9377 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
9379 case 0x7f: /* FSQRT */
9380 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
9382 case 0x1a: /* FCVTNS */
9383 case 0x1b: /* FCVTMS */
9384 case 0x1c: /* FCVTAS */
9385 case 0x3a: /* FCVTPS */
9386 case 0x3b: /* FCVTZS */
9388 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9389 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9390 tcg_temp_free_i32(tcg_shift
);
9393 case 0x5a: /* FCVTNU */
9394 case 0x5b: /* FCVTMU */
9395 case 0x5c: /* FCVTAU */
9396 case 0x7a: /* FCVTPU */
9397 case 0x7b: /* FCVTZU */
9399 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9400 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9401 tcg_temp_free_i32(tcg_shift
);
9404 case 0x18: /* FRINTN */
9405 case 0x19: /* FRINTM */
9406 case 0x38: /* FRINTP */
9407 case 0x39: /* FRINTZ */
9408 case 0x58: /* FRINTA */
9409 case 0x79: /* FRINTI */
9410 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9412 case 0x59: /* FRINTX */
9413 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9415 case 0x1e: /* FRINT32Z */
9416 case 0x5e: /* FRINT32X */
9417 gen_helper_frint32_d(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9419 case 0x1f: /* FRINT64Z */
9420 case 0x5f: /* FRINT64X */
9421 gen_helper_frint64_d(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9424 g_assert_not_reached();
9428 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
9429 bool is_scalar
, bool is_u
, bool is_q
,
9430 int size
, int rn
, int rd
)
9432 bool is_double
= (size
== MO_64
);
9435 if (!fp_access_check(s
)) {
9439 fpst
= get_fpstatus_ptr(size
== MO_16
);
9442 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9443 TCGv_i64 tcg_zero
= tcg_const_i64(0);
9444 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9445 NeonGenTwoDoubleOPFn
*genfn
;
9450 case 0x2e: /* FCMLT (zero) */
9453 case 0x2c: /* FCMGT (zero) */
9454 genfn
= gen_helper_neon_cgt_f64
;
9456 case 0x2d: /* FCMEQ (zero) */
9457 genfn
= gen_helper_neon_ceq_f64
;
9459 case 0x6d: /* FCMLE (zero) */
9462 case 0x6c: /* FCMGE (zero) */
9463 genfn
= gen_helper_neon_cge_f64
;
9466 g_assert_not_reached();
9469 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9470 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9472 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
9474 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
9476 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9478 tcg_temp_free_i64(tcg_res
);
9479 tcg_temp_free_i64(tcg_zero
);
9480 tcg_temp_free_i64(tcg_op
);
9482 clear_vec_high(s
, !is_scalar
, rd
);
9484 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9485 TCGv_i32 tcg_zero
= tcg_const_i32(0);
9486 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9487 NeonGenTwoSingleOPFn
*genfn
;
9489 int pass
, maxpasses
;
9491 if (size
== MO_16
) {
9493 case 0x2e: /* FCMLT (zero) */
9496 case 0x2c: /* FCMGT (zero) */
9497 genfn
= gen_helper_advsimd_cgt_f16
;
9499 case 0x2d: /* FCMEQ (zero) */
9500 genfn
= gen_helper_advsimd_ceq_f16
;
9502 case 0x6d: /* FCMLE (zero) */
9505 case 0x6c: /* FCMGE (zero) */
9506 genfn
= gen_helper_advsimd_cge_f16
;
9509 g_assert_not_reached();
9513 case 0x2e: /* FCMLT (zero) */
9516 case 0x2c: /* FCMGT (zero) */
9517 genfn
= gen_helper_neon_cgt_f32
;
9519 case 0x2d: /* FCMEQ (zero) */
9520 genfn
= gen_helper_neon_ceq_f32
;
9522 case 0x6d: /* FCMLE (zero) */
9525 case 0x6c: /* FCMGE (zero) */
9526 genfn
= gen_helper_neon_cge_f32
;
9529 g_assert_not_reached();
9536 int vector_size
= 8 << is_q
;
9537 maxpasses
= vector_size
>> size
;
9540 for (pass
= 0; pass
< maxpasses
; pass
++) {
9541 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
9543 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
9545 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
9548 write_fp_sreg(s
, rd
, tcg_res
);
9550 write_vec_element_i32(s
, tcg_res
, rd
, pass
, size
);
9553 tcg_temp_free_i32(tcg_res
);
9554 tcg_temp_free_i32(tcg_zero
);
9555 tcg_temp_free_i32(tcg_op
);
9557 clear_vec_high(s
, is_q
, rd
);
9561 tcg_temp_free_ptr(fpst
);
9564 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
9565 bool is_scalar
, bool is_u
, bool is_q
,
9566 int size
, int rn
, int rd
)
9568 bool is_double
= (size
== 3);
9569 TCGv_ptr fpst
= get_fpstatus_ptr(false);
9572 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9573 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9576 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9577 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9579 case 0x3d: /* FRECPE */
9580 gen_helper_recpe_f64(tcg_res
, tcg_op
, fpst
);
9582 case 0x3f: /* FRECPX */
9583 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
9585 case 0x7d: /* FRSQRTE */
9586 gen_helper_rsqrte_f64(tcg_res
, tcg_op
, fpst
);
9589 g_assert_not_reached();
9591 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9593 tcg_temp_free_i64(tcg_res
);
9594 tcg_temp_free_i64(tcg_op
);
9595 clear_vec_high(s
, !is_scalar
, rd
);
9597 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9598 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9599 int pass
, maxpasses
;
9604 maxpasses
= is_q
? 4 : 2;
9607 for (pass
= 0; pass
< maxpasses
; pass
++) {
9608 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
9611 case 0x3c: /* URECPE */
9612 gen_helper_recpe_u32(tcg_res
, tcg_op
, fpst
);
9614 case 0x3d: /* FRECPE */
9615 gen_helper_recpe_f32(tcg_res
, tcg_op
, fpst
);
9617 case 0x3f: /* FRECPX */
9618 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
9620 case 0x7d: /* FRSQRTE */
9621 gen_helper_rsqrte_f32(tcg_res
, tcg_op
, fpst
);
9624 g_assert_not_reached();
9628 write_fp_sreg(s
, rd
, tcg_res
);
9630 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9633 tcg_temp_free_i32(tcg_res
);
9634 tcg_temp_free_i32(tcg_op
);
9636 clear_vec_high(s
, is_q
, rd
);
9639 tcg_temp_free_ptr(fpst
);
9642 static void handle_2misc_narrow(DisasContext
*s
, bool scalar
,
9643 int opcode
, bool u
, bool is_q
,
9644 int size
, int rn
, int rd
)
9646 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
9647 * in the source becomes a size element in the destination).
9650 TCGv_i32 tcg_res
[2];
9651 int destelt
= is_q
? 2 : 0;
9652 int passes
= scalar
? 1 : 2;
9655 tcg_res
[1] = tcg_const_i32(0);
9658 for (pass
= 0; pass
< passes
; pass
++) {
9659 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9660 NeonGenNarrowFn
*genfn
= NULL
;
9661 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
9664 read_vec_element(s
, tcg_op
, rn
, pass
, size
+ 1);
9666 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9668 tcg_res
[pass
] = tcg_temp_new_i32();
9671 case 0x12: /* XTN, SQXTUN */
9673 static NeonGenNarrowFn
* const xtnfns
[3] = {
9674 gen_helper_neon_narrow_u8
,
9675 gen_helper_neon_narrow_u16
,
9676 tcg_gen_extrl_i64_i32
,
9678 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
9679 gen_helper_neon_unarrow_sat8
,
9680 gen_helper_neon_unarrow_sat16
,
9681 gen_helper_neon_unarrow_sat32
,
9684 genenvfn
= sqxtunfns
[size
];
9686 genfn
= xtnfns
[size
];
9690 case 0x14: /* SQXTN, UQXTN */
9692 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
9693 { gen_helper_neon_narrow_sat_s8
,
9694 gen_helper_neon_narrow_sat_u8
},
9695 { gen_helper_neon_narrow_sat_s16
,
9696 gen_helper_neon_narrow_sat_u16
},
9697 { gen_helper_neon_narrow_sat_s32
,
9698 gen_helper_neon_narrow_sat_u32
},
9700 genenvfn
= fns
[size
][u
];
9703 case 0x16: /* FCVTN, FCVTN2 */
9704 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
9706 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
9708 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
9709 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
9710 TCGv_ptr fpst
= get_fpstatus_ptr(false);
9711 TCGv_i32 ahp
= get_ahp_flag();
9713 tcg_gen_extr_i64_i32(tcg_lo
, tcg_hi
, tcg_op
);
9714 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, fpst
, ahp
);
9715 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, fpst
, ahp
);
9716 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
9717 tcg_temp_free_i32(tcg_lo
);
9718 tcg_temp_free_i32(tcg_hi
);
9719 tcg_temp_free_ptr(fpst
);
9720 tcg_temp_free_i32(ahp
);
9723 case 0x56: /* FCVTXN, FCVTXN2 */
9724 /* 64 bit to 32 bit float conversion
9725 * with von Neumann rounding (round to odd)
9728 gen_helper_fcvtx_f64_to_f32(tcg_res
[pass
], tcg_op
, cpu_env
);
9731 g_assert_not_reached();
9735 genfn(tcg_res
[pass
], tcg_op
);
9736 } else if (genenvfn
) {
9737 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
9740 tcg_temp_free_i64(tcg_op
);
9743 for (pass
= 0; pass
< 2; pass
++) {
9744 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
9745 tcg_temp_free_i32(tcg_res
[pass
]);
9747 clear_vec_high(s
, is_q
, rd
);
9750 /* Remaining saturating accumulating ops */
9751 static void handle_2misc_satacc(DisasContext
*s
, bool is_scalar
, bool is_u
,
9752 bool is_q
, int size
, int rn
, int rd
)
9754 bool is_double
= (size
== 3);
9757 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
9758 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
9761 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9762 read_vec_element(s
, tcg_rn
, rn
, pass
, MO_64
);
9763 read_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
9765 if (is_u
) { /* USQADD */
9766 gen_helper_neon_uqadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9767 } else { /* SUQADD */
9768 gen_helper_neon_sqadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9770 write_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
9772 tcg_temp_free_i64(tcg_rd
);
9773 tcg_temp_free_i64(tcg_rn
);
9774 clear_vec_high(s
, !is_scalar
, rd
);
9776 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9777 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
9778 int pass
, maxpasses
;
9783 maxpasses
= is_q
? 4 : 2;
9786 for (pass
= 0; pass
< maxpasses
; pass
++) {
9788 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, size
);
9789 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, size
);
9791 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, MO_32
);
9792 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
9795 if (is_u
) { /* USQADD */
9798 gen_helper_neon_uqadd_s8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9801 gen_helper_neon_uqadd_s16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9804 gen_helper_neon_uqadd_s32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9807 g_assert_not_reached();
9809 } else { /* SUQADD */
9812 gen_helper_neon_sqadd_u8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9815 gen_helper_neon_sqadd_u16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9818 gen_helper_neon_sqadd_u32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9821 g_assert_not_reached();
9826 TCGv_i64 tcg_zero
= tcg_const_i64(0);
9827 write_vec_element(s
, tcg_zero
, rd
, 0, MO_64
);
9828 tcg_temp_free_i64(tcg_zero
);
9830 write_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
9832 tcg_temp_free_i32(tcg_rd
);
9833 tcg_temp_free_i32(tcg_rn
);
9834 clear_vec_high(s
, is_q
, rd
);
9838 /* AdvSIMD scalar two reg misc
9839 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
9840 * +-----+---+-----------+------+-----------+--------+-----+------+------+
9841 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
9842 * +-----+---+-----------+------+-----------+--------+-----+------+------+
9844 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
9846 int rd
= extract32(insn
, 0, 5);
9847 int rn
= extract32(insn
, 5, 5);
9848 int opcode
= extract32(insn
, 12, 5);
9849 int size
= extract32(insn
, 22, 2);
9850 bool u
= extract32(insn
, 29, 1);
9851 bool is_fcvt
= false;
9854 TCGv_ptr tcg_fpstatus
;
9857 case 0x3: /* USQADD / SUQADD*/
9858 if (!fp_access_check(s
)) {
9861 handle_2misc_satacc(s
, true, u
, false, size
, rn
, rd
);
9863 case 0x7: /* SQABS / SQNEG */
9865 case 0xa: /* CMLT */
9867 unallocated_encoding(s
);
9871 case 0x8: /* CMGT, CMGE */
9872 case 0x9: /* CMEQ, CMLE */
9873 case 0xb: /* ABS, NEG */
9875 unallocated_encoding(s
);
9879 case 0x12: /* SQXTUN */
9881 unallocated_encoding(s
);
9885 case 0x14: /* SQXTN, UQXTN */
9887 unallocated_encoding(s
);
9890 if (!fp_access_check(s
)) {
9893 handle_2misc_narrow(s
, true, opcode
, u
, false, size
, rn
, rd
);
9898 /* Floating point: U, size[1] and opcode indicate operation;
9899 * size[0] indicates single or double precision.
9901 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
9902 size
= extract32(size
, 0, 1) ? 3 : 2;
9904 case 0x2c: /* FCMGT (zero) */
9905 case 0x2d: /* FCMEQ (zero) */
9906 case 0x2e: /* FCMLT (zero) */
9907 case 0x6c: /* FCMGE (zero) */
9908 case 0x6d: /* FCMLE (zero) */
9909 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
9911 case 0x1d: /* SCVTF */
9912 case 0x5d: /* UCVTF */
9914 bool is_signed
= (opcode
== 0x1d);
9915 if (!fp_access_check(s
)) {
9918 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
9921 case 0x3d: /* FRECPE */
9922 case 0x3f: /* FRECPX */
9923 case 0x7d: /* FRSQRTE */
9924 if (!fp_access_check(s
)) {
9927 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
9929 case 0x1a: /* FCVTNS */
9930 case 0x1b: /* FCVTMS */
9931 case 0x3a: /* FCVTPS */
9932 case 0x3b: /* FCVTZS */
9933 case 0x5a: /* FCVTNU */
9934 case 0x5b: /* FCVTMU */
9935 case 0x7a: /* FCVTPU */
9936 case 0x7b: /* FCVTZU */
9938 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
9940 case 0x1c: /* FCVTAS */
9941 case 0x5c: /* FCVTAU */
9942 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
9944 rmode
= FPROUNDING_TIEAWAY
;
9946 case 0x56: /* FCVTXN, FCVTXN2 */
9948 unallocated_encoding(s
);
9951 if (!fp_access_check(s
)) {
9954 handle_2misc_narrow(s
, true, opcode
, u
, false, size
- 1, rn
, rd
);
9957 unallocated_encoding(s
);
9962 unallocated_encoding(s
);
9966 if (!fp_access_check(s
)) {
9971 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
9972 tcg_fpstatus
= get_fpstatus_ptr(false);
9973 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
9976 tcg_fpstatus
= NULL
;
9980 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
9981 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
9983 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
9984 write_fp_dreg(s
, rd
, tcg_rd
);
9985 tcg_temp_free_i64(tcg_rd
);
9986 tcg_temp_free_i64(tcg_rn
);
9988 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9989 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
9991 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
9994 case 0x7: /* SQABS, SQNEG */
9996 NeonGenOneOpEnvFn
*genfn
;
9997 static NeonGenOneOpEnvFn
* const fns
[3][2] = {
9998 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
9999 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
10000 { gen_helper_neon_qabs_s32
, gen_helper_neon_qneg_s32
},
10002 genfn
= fns
[size
][u
];
10003 genfn(tcg_rd
, cpu_env
, tcg_rn
);
10006 case 0x1a: /* FCVTNS */
10007 case 0x1b: /* FCVTMS */
10008 case 0x1c: /* FCVTAS */
10009 case 0x3a: /* FCVTPS */
10010 case 0x3b: /* FCVTZS */
10012 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10013 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
10014 tcg_temp_free_i32(tcg_shift
);
10017 case 0x5a: /* FCVTNU */
10018 case 0x5b: /* FCVTMU */
10019 case 0x5c: /* FCVTAU */
10020 case 0x7a: /* FCVTPU */
10021 case 0x7b: /* FCVTZU */
10023 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10024 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
10025 tcg_temp_free_i32(tcg_shift
);
10029 g_assert_not_reached();
10032 write_fp_sreg(s
, rd
, tcg_rd
);
10033 tcg_temp_free_i32(tcg_rd
);
10034 tcg_temp_free_i32(tcg_rn
);
10038 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
10039 tcg_temp_free_i32(tcg_rmode
);
10040 tcg_temp_free_ptr(tcg_fpstatus
);
10044 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
10045 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
10046 int immh
, int immb
, int opcode
, int rn
, int rd
)
10048 int size
= 32 - clz32(immh
) - 1;
10049 int immhb
= immh
<< 3 | immb
;
10050 int shift
= 2 * (8 << size
) - immhb
;
10051 bool accumulate
= false;
10052 int dsize
= is_q
? 128 : 64;
10053 int esize
= 8 << size
;
10054 int elements
= dsize
/esize
;
10055 MemOp memop
= size
| (is_u
? 0 : MO_SIGN
);
10056 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
10057 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
10058 TCGv_i64 tcg_round
;
10059 uint64_t round_const
;
10062 if (extract32(immh
, 3, 1) && !is_q
) {
10063 unallocated_encoding(s
);
10066 tcg_debug_assert(size
<= 3);
10068 if (!fp_access_check(s
)) {
10073 case 0x02: /* SSRA / USRA (accumulate) */
10075 /* Shift count same as element size produces zero to add. */
10076 if (shift
== 8 << size
) {
10079 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &usra_op
[size
]);
10081 /* Shift count same as element size produces all sign to add. */
10082 if (shift
== 8 << size
) {
10085 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &ssra_op
[size
]);
10088 case 0x08: /* SRI */
10089 /* Shift count same as element size is valid but does nothing. */
10090 if (shift
== 8 << size
) {
10093 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &sri_op
[size
]);
10096 case 0x00: /* SSHR / USHR */
10098 if (shift
== 8 << size
) {
10099 /* Shift count the same size as element size produces zero. */
10100 tcg_gen_gvec_dup8i(vec_full_reg_offset(s
, rd
),
10101 is_q
? 16 : 8, vec_full_reg_size(s
), 0);
10103 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_shri
, size
);
10106 /* Shift count the same size as element size produces all sign. */
10107 if (shift
== 8 << size
) {
10110 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_sari
, size
);
10114 case 0x04: /* SRSHR / URSHR (rounding) */
10116 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10120 g_assert_not_reached();
10123 round_const
= 1ULL << (shift
- 1);
10124 tcg_round
= tcg_const_i64(round_const
);
10126 for (i
= 0; i
< elements
; i
++) {
10127 read_vec_element(s
, tcg_rn
, rn
, i
, memop
);
10129 read_vec_element(s
, tcg_rd
, rd
, i
, memop
);
10132 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
10133 accumulate
, is_u
, size
, shift
);
10135 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
10137 tcg_temp_free_i64(tcg_round
);
10140 clear_vec_high(s
, is_q
, rd
);
10143 /* SHL/SLI - Vector shift left */
10144 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
10145 int immh
, int immb
, int opcode
, int rn
, int rd
)
10147 int size
= 32 - clz32(immh
) - 1;
10148 int immhb
= immh
<< 3 | immb
;
10149 int shift
= immhb
- (8 << size
);
10151 /* Range of size is limited by decode: immh is a non-zero 4 bit field */
10152 assert(size
>= 0 && size
<= 3);
10154 if (extract32(immh
, 3, 1) && !is_q
) {
10155 unallocated_encoding(s
);
10159 if (!fp_access_check(s
)) {
10164 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &sli_op
[size
]);
10166 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_shli
, size
);
10170 /* USHLL/SHLL - Vector shift left with widening */
10171 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
10172 int immh
, int immb
, int opcode
, int rn
, int rd
)
10174 int size
= 32 - clz32(immh
) - 1;
10175 int immhb
= immh
<< 3 | immb
;
10176 int shift
= immhb
- (8 << size
);
10178 int esize
= 8 << size
;
10179 int elements
= dsize
/esize
;
10180 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
10181 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
10185 unallocated_encoding(s
);
10189 if (!fp_access_check(s
)) {
10193 /* For the LL variants the store is larger than the load,
10194 * so if rd == rn we would overwrite parts of our input.
10195 * So load everything right now and use shifts in the main loop.
10197 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
10199 for (i
= 0; i
< elements
; i
++) {
10200 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
10201 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
10202 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
10203 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
10207 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
10208 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
10209 int immh
, int immb
, int opcode
, int rn
, int rd
)
10211 int immhb
= immh
<< 3 | immb
;
10212 int size
= 32 - clz32(immh
) - 1;
10214 int esize
= 8 << size
;
10215 int elements
= dsize
/esize
;
10216 int shift
= (2 * esize
) - immhb
;
10217 bool round
= extract32(opcode
, 0, 1);
10218 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
10219 TCGv_i64 tcg_round
;
10222 if (extract32(immh
, 3, 1)) {
10223 unallocated_encoding(s
);
10227 if (!fp_access_check(s
)) {
10231 tcg_rn
= tcg_temp_new_i64();
10232 tcg_rd
= tcg_temp_new_i64();
10233 tcg_final
= tcg_temp_new_i64();
10234 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
10237 uint64_t round_const
= 1ULL << (shift
- 1);
10238 tcg_round
= tcg_const_i64(round_const
);
10243 for (i
= 0; i
< elements
; i
++) {
10244 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
10245 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
10246 false, true, size
+1, shift
);
10248 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
10252 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
10254 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
10257 tcg_temp_free_i64(tcg_round
);
10259 tcg_temp_free_i64(tcg_rn
);
10260 tcg_temp_free_i64(tcg_rd
);
10261 tcg_temp_free_i64(tcg_final
);
10263 clear_vec_high(s
, is_q
, rd
);
10267 /* AdvSIMD shift by immediate
10268 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
10269 * +---+---+---+-------------+------+------+--------+---+------+------+
10270 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
10271 * +---+---+---+-------------+------+------+--------+---+------+------+
10273 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
10275 int rd
= extract32(insn
, 0, 5);
10276 int rn
= extract32(insn
, 5, 5);
10277 int opcode
= extract32(insn
, 11, 5);
10278 int immb
= extract32(insn
, 16, 3);
10279 int immh
= extract32(insn
, 19, 4);
10280 bool is_u
= extract32(insn
, 29, 1);
10281 bool is_q
= extract32(insn
, 30, 1);
10284 case 0x08: /* SRI */
10286 unallocated_encoding(s
);
10290 case 0x00: /* SSHR / USHR */
10291 case 0x02: /* SSRA / USRA (accumulate) */
10292 case 0x04: /* SRSHR / URSHR (rounding) */
10293 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10294 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10296 case 0x0a: /* SHL / SLI */
10297 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10299 case 0x10: /* SHRN */
10300 case 0x11: /* RSHRN / SQRSHRUN */
10302 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
10305 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
10308 case 0x12: /* SQSHRN / UQSHRN */
10309 case 0x13: /* SQRSHRN / UQRSHRN */
10310 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
10313 case 0x14: /* SSHLL / USHLL */
10314 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10316 case 0x1c: /* SCVTF / UCVTF */
10317 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
10320 case 0xc: /* SQSHLU */
10322 unallocated_encoding(s
);
10325 handle_simd_qshl(s
, false, is_q
, false, true, immh
, immb
, rn
, rd
);
10327 case 0xe: /* SQSHL, UQSHL */
10328 handle_simd_qshl(s
, false, is_q
, is_u
, is_u
, immh
, immb
, rn
, rd
);
10330 case 0x1f: /* FCVTZS/ FCVTZU */
10331 handle_simd_shift_fpint_conv(s
, false, is_q
, is_u
, immh
, immb
, rn
, rd
);
10334 unallocated_encoding(s
);
10339 /* Generate code to do a "long" addition or subtraction, ie one done in
10340 * TCGv_i64 on vector lanes twice the width specified by size.
10342 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
10343 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
10345 static NeonGenTwo64OpFn
* const fns
[3][2] = {
10346 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
10347 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
10348 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
10350 NeonGenTwo64OpFn
*genfn
;
10353 genfn
= fns
[size
][is_sub
];
10354 genfn(tcg_res
, tcg_op1
, tcg_op2
);
10357 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
10358 int opcode
, int rd
, int rn
, int rm
)
10360 /* 3-reg-different widening insns: 64 x 64 -> 128 */
10361 TCGv_i64 tcg_res
[2];
10364 tcg_res
[0] = tcg_temp_new_i64();
10365 tcg_res
[1] = tcg_temp_new_i64();
10367 /* Does this op do an adding accumulate, a subtracting accumulate,
10368 * or no accumulate at all?
10386 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
10387 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
10390 /* size == 2 means two 32x32->64 operations; this is worth special
10391 * casing because we can generally handle it inline.
10394 for (pass
= 0; pass
< 2; pass
++) {
10395 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10396 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10397 TCGv_i64 tcg_passres
;
10398 MemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
10400 int elt
= pass
+ is_q
* 2;
10402 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
10403 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
10406 tcg_passres
= tcg_res
[pass
];
10408 tcg_passres
= tcg_temp_new_i64();
10412 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10413 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10415 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10416 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10418 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10419 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10421 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
10422 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
10424 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
10425 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
10426 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
10428 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
10429 tcg_temp_free_i64(tcg_tmp1
);
10430 tcg_temp_free_i64(tcg_tmp2
);
10433 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10434 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10435 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
10436 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10438 case 9: /* SQDMLAL, SQDMLAL2 */
10439 case 11: /* SQDMLSL, SQDMLSL2 */
10440 case 13: /* SQDMULL, SQDMULL2 */
10441 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10442 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
10443 tcg_passres
, tcg_passres
);
10446 g_assert_not_reached();
10449 if (opcode
== 9 || opcode
== 11) {
10450 /* saturating accumulate ops */
10452 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
10454 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
10455 tcg_res
[pass
], tcg_passres
);
10456 } else if (accop
> 0) {
10457 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10458 } else if (accop
< 0) {
10459 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10463 tcg_temp_free_i64(tcg_passres
);
10466 tcg_temp_free_i64(tcg_op1
);
10467 tcg_temp_free_i64(tcg_op2
);
10470 /* size 0 or 1, generally helper functions */
10471 for (pass
= 0; pass
< 2; pass
++) {
10472 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
10473 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10474 TCGv_i64 tcg_passres
;
10475 int elt
= pass
+ is_q
* 2;
10477 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
10478 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
10481 tcg_passres
= tcg_res
[pass
];
10483 tcg_passres
= tcg_temp_new_i64();
10487 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10488 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10490 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
10491 static NeonGenWidenFn
* const widenfns
[2][2] = {
10492 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
10493 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
10495 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
10497 widenfn(tcg_op2_64
, tcg_op2
);
10498 widenfn(tcg_passres
, tcg_op1
);
10499 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
10500 tcg_passres
, tcg_op2_64
);
10501 tcg_temp_free_i64(tcg_op2_64
);
10504 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10505 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10508 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
10510 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10514 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
10516 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
10520 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10521 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10522 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
10525 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
10527 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
10531 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
10533 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10537 case 9: /* SQDMLAL, SQDMLAL2 */
10538 case 11: /* SQDMLSL, SQDMLSL2 */
10539 case 13: /* SQDMULL, SQDMULL2 */
10541 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10542 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
10543 tcg_passres
, tcg_passres
);
10546 g_assert_not_reached();
10548 tcg_temp_free_i32(tcg_op1
);
10549 tcg_temp_free_i32(tcg_op2
);
10552 if (opcode
== 9 || opcode
== 11) {
10553 /* saturating accumulate ops */
10555 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
10557 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
10561 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
10562 tcg_res
[pass
], tcg_passres
);
10564 tcg_temp_free_i64(tcg_passres
);
10569 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
10570 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
10571 tcg_temp_free_i64(tcg_res
[0]);
10572 tcg_temp_free_i64(tcg_res
[1]);
10575 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
10576 int opcode
, int rd
, int rn
, int rm
)
10578 TCGv_i64 tcg_res
[2];
10579 int part
= is_q
? 2 : 0;
10582 for (pass
= 0; pass
< 2; pass
++) {
10583 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10584 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10585 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
10586 static NeonGenWidenFn
* const widenfns
[3][2] = {
10587 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
10588 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
10589 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
10591 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
10593 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
10594 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
10595 widenfn(tcg_op2_wide
, tcg_op2
);
10596 tcg_temp_free_i32(tcg_op2
);
10597 tcg_res
[pass
] = tcg_temp_new_i64();
10598 gen_neon_addl(size
, (opcode
== 3),
10599 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
10600 tcg_temp_free_i64(tcg_op1
);
10601 tcg_temp_free_i64(tcg_op2_wide
);
10604 for (pass
= 0; pass
< 2; pass
++) {
10605 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10606 tcg_temp_free_i64(tcg_res
[pass
]);
10610 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
10612 tcg_gen_addi_i64(in
, in
, 1U << 31);
10613 tcg_gen_extrh_i64_i32(res
, in
);
10616 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
10617 int opcode
, int rd
, int rn
, int rm
)
10619 TCGv_i32 tcg_res
[2];
10620 int part
= is_q
? 2 : 0;
10623 for (pass
= 0; pass
< 2; pass
++) {
10624 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10625 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10626 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
10627 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
10628 { gen_helper_neon_narrow_high_u8
,
10629 gen_helper_neon_narrow_round_high_u8
},
10630 { gen_helper_neon_narrow_high_u16
,
10631 gen_helper_neon_narrow_round_high_u16
},
10632 { tcg_gen_extrh_i64_i32
, do_narrow_round_high_u32
},
10634 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
10636 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
10637 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
10639 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
10641 tcg_temp_free_i64(tcg_op1
);
10642 tcg_temp_free_i64(tcg_op2
);
10644 tcg_res
[pass
] = tcg_temp_new_i32();
10645 gennarrow(tcg_res
[pass
], tcg_wideres
);
10646 tcg_temp_free_i64(tcg_wideres
);
10649 for (pass
= 0; pass
< 2; pass
++) {
10650 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
10651 tcg_temp_free_i32(tcg_res
[pass
]);
10653 clear_vec_high(s
, is_q
, rd
);
10656 /* AdvSIMD three different
10657 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
10658 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
10659 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
10660 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
10662 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
10664 /* Instructions in this group fall into three basic classes
10665 * (in each case with the operation working on each element in
10666 * the input vectors):
10667 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
10669 * (2) wide 64 x 128 -> 128
10670 * (3) narrowing 128 x 128 -> 64
10671 * Here we do initial decode, catch unallocated cases and
10672 * dispatch to separate functions for each class.
10674 int is_q
= extract32(insn
, 30, 1);
10675 int is_u
= extract32(insn
, 29, 1);
10676 int size
= extract32(insn
, 22, 2);
10677 int opcode
= extract32(insn
, 12, 4);
10678 int rm
= extract32(insn
, 16, 5);
10679 int rn
= extract32(insn
, 5, 5);
10680 int rd
= extract32(insn
, 0, 5);
10683 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
10684 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
10685 /* 64 x 128 -> 128 */
10687 unallocated_encoding(s
);
10690 if (!fp_access_check(s
)) {
10693 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10695 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
10696 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
10697 /* 128 x 128 -> 64 */
10699 unallocated_encoding(s
);
10702 if (!fp_access_check(s
)) {
10705 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10707 case 14: /* PMULL, PMULL2 */
10709 unallocated_encoding(s
);
10713 case 0: /* PMULL.P8 */
10714 if (!fp_access_check(s
)) {
10717 /* The Q field specifies lo/hi half input for this insn. */
10718 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, is_q
,
10719 gen_helper_neon_pmull_h
);
10722 case 3: /* PMULL.P64 */
10723 if (!dc_isar_feature(aa64_pmull
, s
)) {
10724 unallocated_encoding(s
);
10727 if (!fp_access_check(s
)) {
10730 /* The Q field specifies lo/hi half input for this insn. */
10731 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, is_q
,
10732 gen_helper_gvec_pmull_q
);
10736 unallocated_encoding(s
);
10740 case 9: /* SQDMLAL, SQDMLAL2 */
10741 case 11: /* SQDMLSL, SQDMLSL2 */
10742 case 13: /* SQDMULL, SQDMULL2 */
10743 if (is_u
|| size
== 0) {
10744 unallocated_encoding(s
);
10748 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10749 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10750 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10751 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10752 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10753 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10754 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
10755 /* 64 x 64 -> 128 */
10757 unallocated_encoding(s
);
10760 if (!fp_access_check(s
)) {
10764 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10767 /* opcode 15 not allocated */
10768 unallocated_encoding(s
);
10773 /* Logic op (opcode == 3) subgroup of C3.6.16. */
10774 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
10776 int rd
= extract32(insn
, 0, 5);
10777 int rn
= extract32(insn
, 5, 5);
10778 int rm
= extract32(insn
, 16, 5);
10779 int size
= extract32(insn
, 22, 2);
10780 bool is_u
= extract32(insn
, 29, 1);
10781 bool is_q
= extract32(insn
, 30, 1);
10783 if (!fp_access_check(s
)) {
10787 switch (size
+ 4 * is_u
) {
10789 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_and
, 0);
10792 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_andc
, 0);
10795 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_or
, 0);
10798 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_orc
, 0);
10801 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_xor
, 0);
10804 case 5: /* BSL bitwise select */
10805 gen_gvec_fn4(s
, is_q
, rd
, rd
, rn
, rm
, tcg_gen_gvec_bitsel
, 0);
10807 case 6: /* BIT, bitwise insert if true */
10808 gen_gvec_fn4(s
, is_q
, rd
, rm
, rn
, rd
, tcg_gen_gvec_bitsel
, 0);
10810 case 7: /* BIF, bitwise insert if false */
10811 gen_gvec_fn4(s
, is_q
, rd
, rm
, rd
, rn
, tcg_gen_gvec_bitsel
, 0);
10815 g_assert_not_reached();
10819 /* Pairwise op subgroup of C3.6.16.
10821 * This is called directly or via the handle_3same_float for float pairwise
10822 * operations where the opcode and size are calculated differently.
10824 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
10825 int size
, int rn
, int rm
, int rd
)
10830 /* Floating point operations need fpst */
10831 if (opcode
>= 0x58) {
10832 fpst
= get_fpstatus_ptr(false);
10837 if (!fp_access_check(s
)) {
10841 /* These operations work on the concatenated rm:rn, with each pair of
10842 * adjacent elements being operated on to produce an element in the result.
10845 TCGv_i64 tcg_res
[2];
10847 for (pass
= 0; pass
< 2; pass
++) {
10848 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10849 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10850 int passreg
= (pass
== 0) ? rn
: rm
;
10852 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
10853 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
10854 tcg_res
[pass
] = tcg_temp_new_i64();
10857 case 0x17: /* ADDP */
10858 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
10860 case 0x58: /* FMAXNMP */
10861 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10863 case 0x5a: /* FADDP */
10864 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10866 case 0x5e: /* FMAXP */
10867 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10869 case 0x78: /* FMINNMP */
10870 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10872 case 0x7e: /* FMINP */
10873 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10876 g_assert_not_reached();
10879 tcg_temp_free_i64(tcg_op1
);
10880 tcg_temp_free_i64(tcg_op2
);
10883 for (pass
= 0; pass
< 2; pass
++) {
10884 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10885 tcg_temp_free_i64(tcg_res
[pass
]);
10888 int maxpass
= is_q
? 4 : 2;
10889 TCGv_i32 tcg_res
[4];
10891 for (pass
= 0; pass
< maxpass
; pass
++) {
10892 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
10893 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10894 NeonGenTwoOpFn
*genfn
= NULL
;
10895 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
10896 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
10898 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
10899 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
10900 tcg_res
[pass
] = tcg_temp_new_i32();
10903 case 0x17: /* ADDP */
10905 static NeonGenTwoOpFn
* const fns
[3] = {
10906 gen_helper_neon_padd_u8
,
10907 gen_helper_neon_padd_u16
,
10913 case 0x14: /* SMAXP, UMAXP */
10915 static NeonGenTwoOpFn
* const fns
[3][2] = {
10916 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
10917 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
10918 { tcg_gen_smax_i32
, tcg_gen_umax_i32
},
10920 genfn
= fns
[size
][u
];
10923 case 0x15: /* SMINP, UMINP */
10925 static NeonGenTwoOpFn
* const fns
[3][2] = {
10926 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
10927 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
10928 { tcg_gen_smin_i32
, tcg_gen_umin_i32
},
10930 genfn
= fns
[size
][u
];
10933 /* The FP operations are all on single floats (32 bit) */
10934 case 0x58: /* FMAXNMP */
10935 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10937 case 0x5a: /* FADDP */
10938 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10940 case 0x5e: /* FMAXP */
10941 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10943 case 0x78: /* FMINNMP */
10944 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10946 case 0x7e: /* FMINP */
10947 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10950 g_assert_not_reached();
10953 /* FP ops called directly, otherwise call now */
10955 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
10958 tcg_temp_free_i32(tcg_op1
);
10959 tcg_temp_free_i32(tcg_op2
);
10962 for (pass
= 0; pass
< maxpass
; pass
++) {
10963 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
10964 tcg_temp_free_i32(tcg_res
[pass
]);
10966 clear_vec_high(s
, is_q
, rd
);
10970 tcg_temp_free_ptr(fpst
);
10974 /* Floating point op subgroup of C3.6.16. */
10975 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
10977 /* For floating point ops, the U, size[1] and opcode bits
10978 * together indicate the operation. size[0] indicates single
10981 int fpopcode
= extract32(insn
, 11, 5)
10982 | (extract32(insn
, 23, 1) << 5)
10983 | (extract32(insn
, 29, 1) << 6);
10984 int is_q
= extract32(insn
, 30, 1);
10985 int size
= extract32(insn
, 22, 1);
10986 int rm
= extract32(insn
, 16, 5);
10987 int rn
= extract32(insn
, 5, 5);
10988 int rd
= extract32(insn
, 0, 5);
10990 int datasize
= is_q
? 128 : 64;
10991 int esize
= 32 << size
;
10992 int elements
= datasize
/ esize
;
10994 if (size
== 1 && !is_q
) {
10995 unallocated_encoding(s
);
10999 switch (fpopcode
) {
11000 case 0x58: /* FMAXNMP */
11001 case 0x5a: /* FADDP */
11002 case 0x5e: /* FMAXP */
11003 case 0x78: /* FMINNMP */
11004 case 0x7e: /* FMINP */
11005 if (size
&& !is_q
) {
11006 unallocated_encoding(s
);
11009 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
11012 case 0x1b: /* FMULX */
11013 case 0x1f: /* FRECPS */
11014 case 0x3f: /* FRSQRTS */
11015 case 0x5d: /* FACGE */
11016 case 0x7d: /* FACGT */
11017 case 0x19: /* FMLA */
11018 case 0x39: /* FMLS */
11019 case 0x18: /* FMAXNM */
11020 case 0x1a: /* FADD */
11021 case 0x1c: /* FCMEQ */
11022 case 0x1e: /* FMAX */
11023 case 0x38: /* FMINNM */
11024 case 0x3a: /* FSUB */
11025 case 0x3e: /* FMIN */
11026 case 0x5b: /* FMUL */
11027 case 0x5c: /* FCMGE */
11028 case 0x5f: /* FDIV */
11029 case 0x7a: /* FABD */
11030 case 0x7c: /* FCMGT */
11031 if (!fp_access_check(s
)) {
11034 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
11037 case 0x1d: /* FMLAL */
11038 case 0x3d: /* FMLSL */
11039 case 0x59: /* FMLAL2 */
11040 case 0x79: /* FMLSL2 */
11041 if (size
& 1 || !dc_isar_feature(aa64_fhm
, s
)) {
11042 unallocated_encoding(s
);
11045 if (fp_access_check(s
)) {
11046 int is_s
= extract32(insn
, 23, 1);
11047 int is_2
= extract32(insn
, 29, 1);
11048 int data
= (is_2
<< 1) | is_s
;
11049 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
11050 vec_full_reg_offset(s
, rn
),
11051 vec_full_reg_offset(s
, rm
), cpu_env
,
11052 is_q
? 16 : 8, vec_full_reg_size(s
),
11053 data
, gen_helper_gvec_fmlal_a64
);
11058 unallocated_encoding(s
);
11063 /* Integer op subgroup of C3.6.16. */
11064 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
11066 int is_q
= extract32(insn
, 30, 1);
11067 int u
= extract32(insn
, 29, 1);
11068 int size
= extract32(insn
, 22, 2);
11069 int opcode
= extract32(insn
, 11, 5);
11070 int rm
= extract32(insn
, 16, 5);
11071 int rn
= extract32(insn
, 5, 5);
11072 int rd
= extract32(insn
, 0, 5);
11077 case 0x13: /* MUL, PMUL */
11078 if (u
&& size
!= 0) {
11079 unallocated_encoding(s
);
11083 case 0x0: /* SHADD, UHADD */
11084 case 0x2: /* SRHADD, URHADD */
11085 case 0x4: /* SHSUB, UHSUB */
11086 case 0xc: /* SMAX, UMAX */
11087 case 0xd: /* SMIN, UMIN */
11088 case 0xe: /* SABD, UABD */
11089 case 0xf: /* SABA, UABA */
11090 case 0x12: /* MLA, MLS */
11092 unallocated_encoding(s
);
11096 case 0x16: /* SQDMULH, SQRDMULH */
11097 if (size
== 0 || size
== 3) {
11098 unallocated_encoding(s
);
11103 if (size
== 3 && !is_q
) {
11104 unallocated_encoding(s
);
11110 if (!fp_access_check(s
)) {
11115 case 0x01: /* SQADD, UQADD */
11116 tcg_gen_gvec_4(vec_full_reg_offset(s
, rd
),
11117 offsetof(CPUARMState
, vfp
.qc
),
11118 vec_full_reg_offset(s
, rn
),
11119 vec_full_reg_offset(s
, rm
),
11120 is_q
? 16 : 8, vec_full_reg_size(s
),
11121 (u
? uqadd_op
: sqadd_op
) + size
);
11123 case 0x05: /* SQSUB, UQSUB */
11124 tcg_gen_gvec_4(vec_full_reg_offset(s
, rd
),
11125 offsetof(CPUARMState
, vfp
.qc
),
11126 vec_full_reg_offset(s
, rn
),
11127 vec_full_reg_offset(s
, rm
),
11128 is_q
? 16 : 8, vec_full_reg_size(s
),
11129 (u
? uqsub_op
: sqsub_op
) + size
);
11131 case 0x08: /* SSHL, USHL */
11132 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
,
11133 u
? &ushl_op
[size
] : &sshl_op
[size
]);
11135 case 0x0c: /* SMAX, UMAX */
11137 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_umax
, size
);
11139 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_smax
, size
);
11142 case 0x0d: /* SMIN, UMIN */
11144 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_umin
, size
);
11146 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_smin
, size
);
11149 case 0x10: /* ADD, SUB */
11151 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_sub
, size
);
11153 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_add
, size
);
11156 case 0x13: /* MUL, PMUL */
11157 if (!u
) { /* MUL */
11158 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_mul
, size
);
11159 } else { /* PMUL */
11160 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, 0, gen_helper_gvec_pmul_b
);
11163 case 0x12: /* MLA, MLS */
11165 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &mls_op
[size
]);
11167 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &mla_op
[size
]);
11171 if (!u
) { /* CMTST */
11172 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &cmtst_op
[size
]);
11176 cond
= TCG_COND_EQ
;
11178 case 0x06: /* CMGT, CMHI */
11179 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
11181 case 0x07: /* CMGE, CMHS */
11182 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
11184 tcg_gen_gvec_cmp(cond
, size
, vec_full_reg_offset(s
, rd
),
11185 vec_full_reg_offset(s
, rn
),
11186 vec_full_reg_offset(s
, rm
),
11187 is_q
? 16 : 8, vec_full_reg_size(s
));
11193 for (pass
= 0; pass
< 2; pass
++) {
11194 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11195 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11196 TCGv_i64 tcg_res
= tcg_temp_new_i64();
11198 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
11199 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
11201 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
11203 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
11205 tcg_temp_free_i64(tcg_res
);
11206 tcg_temp_free_i64(tcg_op1
);
11207 tcg_temp_free_i64(tcg_op2
);
11210 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
11211 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11212 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11213 TCGv_i32 tcg_res
= tcg_temp_new_i32();
11214 NeonGenTwoOpFn
*genfn
= NULL
;
11215 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
11217 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
11218 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
11221 case 0x0: /* SHADD, UHADD */
11223 static NeonGenTwoOpFn
* const fns
[3][2] = {
11224 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
11225 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
11226 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
11228 genfn
= fns
[size
][u
];
11231 case 0x2: /* SRHADD, URHADD */
11233 static NeonGenTwoOpFn
* const fns
[3][2] = {
11234 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
11235 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
11236 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
11238 genfn
= fns
[size
][u
];
11241 case 0x4: /* SHSUB, UHSUB */
11243 static NeonGenTwoOpFn
* const fns
[3][2] = {
11244 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
11245 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
11246 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
11248 genfn
= fns
[size
][u
];
11251 case 0x9: /* SQSHL, UQSHL */
11253 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11254 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
11255 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
11256 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
11258 genenvfn
= fns
[size
][u
];
11261 case 0xa: /* SRSHL, URSHL */
11263 static NeonGenTwoOpFn
* const fns
[3][2] = {
11264 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
11265 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
11266 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
11268 genfn
= fns
[size
][u
];
11271 case 0xb: /* SQRSHL, UQRSHL */
11273 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11274 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
11275 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
11276 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
11278 genenvfn
= fns
[size
][u
];
11281 case 0xe: /* SABD, UABD */
11282 case 0xf: /* SABA, UABA */
11284 static NeonGenTwoOpFn
* const fns
[3][2] = {
11285 { gen_helper_neon_abd_s8
, gen_helper_neon_abd_u8
},
11286 { gen_helper_neon_abd_s16
, gen_helper_neon_abd_u16
},
11287 { gen_helper_neon_abd_s32
, gen_helper_neon_abd_u32
},
11289 genfn
= fns
[size
][u
];
11292 case 0x16: /* SQDMULH, SQRDMULH */
11294 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
11295 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
11296 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
11298 assert(size
== 1 || size
== 2);
11299 genenvfn
= fns
[size
- 1][u
];
11303 g_assert_not_reached();
11307 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
11309 genfn(tcg_res
, tcg_op1
, tcg_op2
);
11312 if (opcode
== 0xf) {
11313 /* SABA, UABA: accumulating ops */
11314 static NeonGenTwoOpFn
* const fns
[3] = {
11315 gen_helper_neon_add_u8
,
11316 gen_helper_neon_add_u16
,
11320 read_vec_element_i32(s
, tcg_op1
, rd
, pass
, MO_32
);
11321 fns
[size
](tcg_res
, tcg_op1
, tcg_res
);
11324 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
11326 tcg_temp_free_i32(tcg_res
);
11327 tcg_temp_free_i32(tcg_op1
);
11328 tcg_temp_free_i32(tcg_op2
);
11331 clear_vec_high(s
, is_q
, rd
);
11334 /* AdvSIMD three same
11335 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
11336 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11337 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
11338 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11340 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
11342 int opcode
= extract32(insn
, 11, 5);
11345 case 0x3: /* logic ops */
11346 disas_simd_3same_logic(s
, insn
);
11348 case 0x17: /* ADDP */
11349 case 0x14: /* SMAXP, UMAXP */
11350 case 0x15: /* SMINP, UMINP */
11352 /* Pairwise operations */
11353 int is_q
= extract32(insn
, 30, 1);
11354 int u
= extract32(insn
, 29, 1);
11355 int size
= extract32(insn
, 22, 2);
11356 int rm
= extract32(insn
, 16, 5);
11357 int rn
= extract32(insn
, 5, 5);
11358 int rd
= extract32(insn
, 0, 5);
11359 if (opcode
== 0x17) {
11360 if (u
|| (size
== 3 && !is_q
)) {
11361 unallocated_encoding(s
);
11366 unallocated_encoding(s
);
11370 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
11373 case 0x18 ... 0x31:
11374 /* floating point ops, sz[1] and U are part of opcode */
11375 disas_simd_3same_float(s
, insn
);
11378 disas_simd_3same_int(s
, insn
);
11384 * Advanced SIMD three same (ARMv8.2 FP16 variants)
11386 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
11387 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11388 * | 0 | Q | U | 0 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
11389 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11391 * This includes FMULX, FCMEQ (register), FRECPS, FRSQRTS, FCMGE
11392 * (register), FACGE, FABD, FCMGT (register) and FACGT.
11395 static void disas_simd_three_reg_same_fp16(DisasContext
*s
, uint32_t insn
)
11397 int opcode
, fpopcode
;
11398 int is_q
, u
, a
, rm
, rn
, rd
;
11399 int datasize
, elements
;
11402 bool pairwise
= false;
11404 if (!dc_isar_feature(aa64_fp16
, s
)) {
11405 unallocated_encoding(s
);
11409 if (!fp_access_check(s
)) {
11413 /* For these floating point ops, the U, a and opcode bits
11414 * together indicate the operation.
11416 opcode
= extract32(insn
, 11, 3);
11417 u
= extract32(insn
, 29, 1);
11418 a
= extract32(insn
, 23, 1);
11419 is_q
= extract32(insn
, 30, 1);
11420 rm
= extract32(insn
, 16, 5);
11421 rn
= extract32(insn
, 5, 5);
11422 rd
= extract32(insn
, 0, 5);
11424 fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
11425 datasize
= is_q
? 128 : 64;
11426 elements
= datasize
/ 16;
11428 switch (fpopcode
) {
11429 case 0x10: /* FMAXNMP */
11430 case 0x12: /* FADDP */
11431 case 0x16: /* FMAXP */
11432 case 0x18: /* FMINNMP */
11433 case 0x1e: /* FMINP */
11438 fpst
= get_fpstatus_ptr(true);
11441 int maxpass
= is_q
? 8 : 4;
11442 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11443 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11444 TCGv_i32 tcg_res
[8];
11446 for (pass
= 0; pass
< maxpass
; pass
++) {
11447 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
11448 int passelt
= (pass
<< 1) & (maxpass
- 1);
11450 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_16
);
11451 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_16
);
11452 tcg_res
[pass
] = tcg_temp_new_i32();
11454 switch (fpopcode
) {
11455 case 0x10: /* FMAXNMP */
11456 gen_helper_advsimd_maxnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
11459 case 0x12: /* FADDP */
11460 gen_helper_advsimd_addh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11462 case 0x16: /* FMAXP */
11463 gen_helper_advsimd_maxh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11465 case 0x18: /* FMINNMP */
11466 gen_helper_advsimd_minnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
11469 case 0x1e: /* FMINP */
11470 gen_helper_advsimd_minh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11473 g_assert_not_reached();
11477 for (pass
= 0; pass
< maxpass
; pass
++) {
11478 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_16
);
11479 tcg_temp_free_i32(tcg_res
[pass
]);
11482 tcg_temp_free_i32(tcg_op1
);
11483 tcg_temp_free_i32(tcg_op2
);
11486 for (pass
= 0; pass
< elements
; pass
++) {
11487 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11488 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11489 TCGv_i32 tcg_res
= tcg_temp_new_i32();
11491 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_16
);
11492 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_16
);
11494 switch (fpopcode
) {
11495 case 0x0: /* FMAXNM */
11496 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11498 case 0x1: /* FMLA */
11499 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11500 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
11503 case 0x2: /* FADD */
11504 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11506 case 0x3: /* FMULX */
11507 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11509 case 0x4: /* FCMEQ */
11510 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11512 case 0x6: /* FMAX */
11513 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11515 case 0x7: /* FRECPS */
11516 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11518 case 0x8: /* FMINNM */
11519 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11521 case 0x9: /* FMLS */
11522 /* As usual for ARM, separate negation for fused multiply-add */
11523 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
11524 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11525 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
11528 case 0xa: /* FSUB */
11529 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11531 case 0xe: /* FMIN */
11532 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11534 case 0xf: /* FRSQRTS */
11535 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11537 case 0x13: /* FMUL */
11538 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11540 case 0x14: /* FCMGE */
11541 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11543 case 0x15: /* FACGE */
11544 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11546 case 0x17: /* FDIV */
11547 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11549 case 0x1a: /* FABD */
11550 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11551 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
11553 case 0x1c: /* FCMGT */
11554 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11556 case 0x1d: /* FACGT */
11557 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11560 fprintf(stderr
, "%s: insn %#04x, fpop %#2x @ %#" PRIx64
"\n",
11561 __func__
, insn
, fpopcode
, s
->pc_curr
);
11562 g_assert_not_reached();
11565 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11566 tcg_temp_free_i32(tcg_res
);
11567 tcg_temp_free_i32(tcg_op1
);
11568 tcg_temp_free_i32(tcg_op2
);
11572 tcg_temp_free_ptr(fpst
);
11574 clear_vec_high(s
, is_q
, rd
);
11577 /* AdvSIMD three same extra
11578 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
11579 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
11580 * | 0 | Q | U | 0 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
11581 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
11583 static void disas_simd_three_reg_same_extra(DisasContext
*s
, uint32_t insn
)
11585 int rd
= extract32(insn
, 0, 5);
11586 int rn
= extract32(insn
, 5, 5);
11587 int opcode
= extract32(insn
, 11, 4);
11588 int rm
= extract32(insn
, 16, 5);
11589 int size
= extract32(insn
, 22, 2);
11590 bool u
= extract32(insn
, 29, 1);
11591 bool is_q
= extract32(insn
, 30, 1);
11595 switch (u
* 16 + opcode
) {
11596 case 0x10: /* SQRDMLAH (vector) */
11597 case 0x11: /* SQRDMLSH (vector) */
11598 if (size
!= 1 && size
!= 2) {
11599 unallocated_encoding(s
);
11602 feature
= dc_isar_feature(aa64_rdm
, s
);
11604 case 0x02: /* SDOT (vector) */
11605 case 0x12: /* UDOT (vector) */
11606 if (size
!= MO_32
) {
11607 unallocated_encoding(s
);
11610 feature
= dc_isar_feature(aa64_dp
, s
);
11612 case 0x18: /* FCMLA, #0 */
11613 case 0x19: /* FCMLA, #90 */
11614 case 0x1a: /* FCMLA, #180 */
11615 case 0x1b: /* FCMLA, #270 */
11616 case 0x1c: /* FCADD, #90 */
11617 case 0x1e: /* FCADD, #270 */
11619 || (size
== 1 && !dc_isar_feature(aa64_fp16
, s
))
11620 || (size
== 3 && !is_q
)) {
11621 unallocated_encoding(s
);
11624 feature
= dc_isar_feature(aa64_fcma
, s
);
11627 unallocated_encoding(s
);
11631 unallocated_encoding(s
);
11634 if (!fp_access_check(s
)) {
11639 case 0x0: /* SQRDMLAH (vector) */
11642 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlah_s16
);
11645 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlah_s32
);
11648 g_assert_not_reached();
11652 case 0x1: /* SQRDMLSH (vector) */
11655 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlsh_s16
);
11658 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlsh_s32
);
11661 g_assert_not_reached();
11665 case 0x2: /* SDOT / UDOT */
11666 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, 0,
11667 u
? gen_helper_gvec_udot_b
: gen_helper_gvec_sdot_b
);
11670 case 0x8: /* FCMLA, #0 */
11671 case 0x9: /* FCMLA, #90 */
11672 case 0xa: /* FCMLA, #180 */
11673 case 0xb: /* FCMLA, #270 */
11674 rot
= extract32(opcode
, 0, 2);
11677 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, true, rot
,
11678 gen_helper_gvec_fcmlah
);
11681 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, false, rot
,
11682 gen_helper_gvec_fcmlas
);
11685 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, false, rot
,
11686 gen_helper_gvec_fcmlad
);
11689 g_assert_not_reached();
11693 case 0xc: /* FCADD, #90 */
11694 case 0xe: /* FCADD, #270 */
11695 rot
= extract32(opcode
, 1, 1);
11698 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11699 gen_helper_gvec_fcaddh
);
11702 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11703 gen_helper_gvec_fcadds
);
11706 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11707 gen_helper_gvec_fcaddd
);
11710 g_assert_not_reached();
11715 g_assert_not_reached();
11719 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
11720 int size
, int rn
, int rd
)
11722 /* Handle 2-reg-misc ops which are widening (so each size element
11723 * in the source becomes a 2*size element in the destination.
11724 * The only instruction like this is FCVTL.
11729 /* 32 -> 64 bit fp conversion */
11730 TCGv_i64 tcg_res
[2];
11731 int srcelt
= is_q
? 2 : 0;
11733 for (pass
= 0; pass
< 2; pass
++) {
11734 TCGv_i32 tcg_op
= tcg_temp_new_i32();
11735 tcg_res
[pass
] = tcg_temp_new_i64();
11737 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
11738 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
11739 tcg_temp_free_i32(tcg_op
);
11741 for (pass
= 0; pass
< 2; pass
++) {
11742 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11743 tcg_temp_free_i64(tcg_res
[pass
]);
11746 /* 16 -> 32 bit fp conversion */
11747 int srcelt
= is_q
? 4 : 0;
11748 TCGv_i32 tcg_res
[4];
11749 TCGv_ptr fpst
= get_fpstatus_ptr(false);
11750 TCGv_i32 ahp
= get_ahp_flag();
11752 for (pass
= 0; pass
< 4; pass
++) {
11753 tcg_res
[pass
] = tcg_temp_new_i32();
11755 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
11756 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
11759 for (pass
= 0; pass
< 4; pass
++) {
11760 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
11761 tcg_temp_free_i32(tcg_res
[pass
]);
11764 tcg_temp_free_ptr(fpst
);
11765 tcg_temp_free_i32(ahp
);
11769 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
11770 bool is_q
, int size
, int rn
, int rd
)
11772 int op
= (opcode
<< 1) | u
;
11773 int opsz
= op
+ size
;
11774 int grp_size
= 3 - opsz
;
11775 int dsize
= is_q
? 128 : 64;
11779 unallocated_encoding(s
);
11783 if (!fp_access_check(s
)) {
11788 /* Special case bytes, use bswap op on each group of elements */
11789 int groups
= dsize
/ (8 << grp_size
);
11791 for (i
= 0; i
< groups
; i
++) {
11792 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
11794 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
11795 switch (grp_size
) {
11797 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
11800 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
11803 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
11806 g_assert_not_reached();
11808 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
11809 tcg_temp_free_i64(tcg_tmp
);
11811 clear_vec_high(s
, is_q
, rd
);
11813 int revmask
= (1 << grp_size
) - 1;
11814 int esize
= 8 << size
;
11815 int elements
= dsize
/ esize
;
11816 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
11817 TCGv_i64 tcg_rd
= tcg_const_i64(0);
11818 TCGv_i64 tcg_rd_hi
= tcg_const_i64(0);
11820 for (i
= 0; i
< elements
; i
++) {
11821 int e_rev
= (i
& 0xf) ^ revmask
;
11822 int off
= e_rev
* esize
;
11823 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
11825 tcg_gen_deposit_i64(tcg_rd_hi
, tcg_rd_hi
,
11826 tcg_rn
, off
- 64, esize
);
11828 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, off
, esize
);
11831 write_vec_element(s
, tcg_rd
, rd
, 0, MO_64
);
11832 write_vec_element(s
, tcg_rd_hi
, rd
, 1, MO_64
);
11834 tcg_temp_free_i64(tcg_rd_hi
);
11835 tcg_temp_free_i64(tcg_rd
);
11836 tcg_temp_free_i64(tcg_rn
);
11840 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
11841 bool is_q
, int size
, int rn
, int rd
)
11843 /* Implement the pairwise operations from 2-misc:
11844 * SADDLP, UADDLP, SADALP, UADALP.
11845 * These all add pairs of elements in the input to produce a
11846 * double-width result element in the output (possibly accumulating).
11848 bool accum
= (opcode
== 0x6);
11849 int maxpass
= is_q
? 2 : 1;
11851 TCGv_i64 tcg_res
[2];
11854 /* 32 + 32 -> 64 op */
11855 MemOp memop
= size
+ (u
? 0 : MO_SIGN
);
11857 for (pass
= 0; pass
< maxpass
; pass
++) {
11858 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11859 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11861 tcg_res
[pass
] = tcg_temp_new_i64();
11863 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
11864 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
11865 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
11867 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
11868 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
11871 tcg_temp_free_i64(tcg_op1
);
11872 tcg_temp_free_i64(tcg_op2
);
11875 for (pass
= 0; pass
< maxpass
; pass
++) {
11876 TCGv_i64 tcg_op
= tcg_temp_new_i64();
11877 NeonGenOneOpFn
*genfn
;
11878 static NeonGenOneOpFn
* const fns
[2][2] = {
11879 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
11880 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
11883 genfn
= fns
[size
][u
];
11885 tcg_res
[pass
] = tcg_temp_new_i64();
11887 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
11888 genfn(tcg_res
[pass
], tcg_op
);
11891 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
11893 gen_helper_neon_addl_u16(tcg_res
[pass
],
11894 tcg_res
[pass
], tcg_op
);
11896 gen_helper_neon_addl_u32(tcg_res
[pass
],
11897 tcg_res
[pass
], tcg_op
);
11900 tcg_temp_free_i64(tcg_op
);
11904 tcg_res
[1] = tcg_const_i64(0);
11906 for (pass
= 0; pass
< 2; pass
++) {
11907 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11908 tcg_temp_free_i64(tcg_res
[pass
]);
11912 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
11914 /* Implement SHLL and SHLL2 */
11916 int part
= is_q
? 2 : 0;
11917 TCGv_i64 tcg_res
[2];
11919 for (pass
= 0; pass
< 2; pass
++) {
11920 static NeonGenWidenFn
* const widenfns
[3] = {
11921 gen_helper_neon_widen_u8
,
11922 gen_helper_neon_widen_u16
,
11923 tcg_gen_extu_i32_i64
,
11925 NeonGenWidenFn
*widenfn
= widenfns
[size
];
11926 TCGv_i32 tcg_op
= tcg_temp_new_i32();
11928 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
11929 tcg_res
[pass
] = tcg_temp_new_i64();
11930 widenfn(tcg_res
[pass
], tcg_op
);
11931 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
11933 tcg_temp_free_i32(tcg_op
);
11936 for (pass
= 0; pass
< 2; pass
++) {
11937 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11938 tcg_temp_free_i64(tcg_res
[pass
]);
11942 /* AdvSIMD two reg misc
11943 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
11944 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
11945 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
11946 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
11948 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
11950 int size
= extract32(insn
, 22, 2);
11951 int opcode
= extract32(insn
, 12, 5);
11952 bool u
= extract32(insn
, 29, 1);
11953 bool is_q
= extract32(insn
, 30, 1);
11954 int rn
= extract32(insn
, 5, 5);
11955 int rd
= extract32(insn
, 0, 5);
11956 bool need_fpstatus
= false;
11957 bool need_rmode
= false;
11959 TCGv_i32 tcg_rmode
;
11960 TCGv_ptr tcg_fpstatus
;
11963 case 0x0: /* REV64, REV32 */
11964 case 0x1: /* REV16 */
11965 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
11967 case 0x5: /* CNT, NOT, RBIT */
11968 if (u
&& size
== 0) {
11971 } else if (u
&& size
== 1) {
11974 } else if (!u
&& size
== 0) {
11978 unallocated_encoding(s
);
11980 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
11981 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
11983 unallocated_encoding(s
);
11986 if (!fp_access_check(s
)) {
11990 handle_2misc_narrow(s
, false, opcode
, u
, is_q
, size
, rn
, rd
);
11992 case 0x4: /* CLS, CLZ */
11994 unallocated_encoding(s
);
11998 case 0x2: /* SADDLP, UADDLP */
11999 case 0x6: /* SADALP, UADALP */
12001 unallocated_encoding(s
);
12004 if (!fp_access_check(s
)) {
12007 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
12009 case 0x13: /* SHLL, SHLL2 */
12010 if (u
== 0 || size
== 3) {
12011 unallocated_encoding(s
);
12014 if (!fp_access_check(s
)) {
12017 handle_shll(s
, is_q
, size
, rn
, rd
);
12019 case 0xa: /* CMLT */
12021 unallocated_encoding(s
);
12025 case 0x8: /* CMGT, CMGE */
12026 case 0x9: /* CMEQ, CMLE */
12027 case 0xb: /* ABS, NEG */
12028 if (size
== 3 && !is_q
) {
12029 unallocated_encoding(s
);
12033 case 0x3: /* SUQADD, USQADD */
12034 if (size
== 3 && !is_q
) {
12035 unallocated_encoding(s
);
12038 if (!fp_access_check(s
)) {
12041 handle_2misc_satacc(s
, false, u
, is_q
, size
, rn
, rd
);
12043 case 0x7: /* SQABS, SQNEG */
12044 if (size
== 3 && !is_q
) {
12045 unallocated_encoding(s
);
12050 case 0x16 ... 0x1f:
12052 /* Floating point: U, size[1] and opcode indicate operation;
12053 * size[0] indicates single or double precision.
12055 int is_double
= extract32(size
, 0, 1);
12056 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
12057 size
= is_double
? 3 : 2;
12059 case 0x2f: /* FABS */
12060 case 0x6f: /* FNEG */
12061 if (size
== 3 && !is_q
) {
12062 unallocated_encoding(s
);
12066 case 0x1d: /* SCVTF */
12067 case 0x5d: /* UCVTF */
12069 bool is_signed
= (opcode
== 0x1d) ? true : false;
12070 int elements
= is_double
? 2 : is_q
? 4 : 2;
12071 if (is_double
&& !is_q
) {
12072 unallocated_encoding(s
);
12075 if (!fp_access_check(s
)) {
12078 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
12081 case 0x2c: /* FCMGT (zero) */
12082 case 0x2d: /* FCMEQ (zero) */
12083 case 0x2e: /* FCMLT (zero) */
12084 case 0x6c: /* FCMGE (zero) */
12085 case 0x6d: /* FCMLE (zero) */
12086 if (size
== 3 && !is_q
) {
12087 unallocated_encoding(s
);
12090 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
12092 case 0x7f: /* FSQRT */
12093 if (size
== 3 && !is_q
) {
12094 unallocated_encoding(s
);
12098 case 0x1a: /* FCVTNS */
12099 case 0x1b: /* FCVTMS */
12100 case 0x3a: /* FCVTPS */
12101 case 0x3b: /* FCVTZS */
12102 case 0x5a: /* FCVTNU */
12103 case 0x5b: /* FCVTMU */
12104 case 0x7a: /* FCVTPU */
12105 case 0x7b: /* FCVTZU */
12106 need_fpstatus
= true;
12108 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
12109 if (size
== 3 && !is_q
) {
12110 unallocated_encoding(s
);
12114 case 0x5c: /* FCVTAU */
12115 case 0x1c: /* FCVTAS */
12116 need_fpstatus
= true;
12118 rmode
= FPROUNDING_TIEAWAY
;
12119 if (size
== 3 && !is_q
) {
12120 unallocated_encoding(s
);
12124 case 0x3c: /* URECPE */
12126 unallocated_encoding(s
);
12130 case 0x3d: /* FRECPE */
12131 case 0x7d: /* FRSQRTE */
12132 if (size
== 3 && !is_q
) {
12133 unallocated_encoding(s
);
12136 if (!fp_access_check(s
)) {
12139 handle_2misc_reciprocal(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
12141 case 0x56: /* FCVTXN, FCVTXN2 */
12143 unallocated_encoding(s
);
12147 case 0x16: /* FCVTN, FCVTN2 */
12148 /* handle_2misc_narrow does a 2*size -> size operation, but these
12149 * instructions encode the source size rather than dest size.
12151 if (!fp_access_check(s
)) {
12154 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
12156 case 0x17: /* FCVTL, FCVTL2 */
12157 if (!fp_access_check(s
)) {
12160 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
12162 case 0x18: /* FRINTN */
12163 case 0x19: /* FRINTM */
12164 case 0x38: /* FRINTP */
12165 case 0x39: /* FRINTZ */
12167 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
12169 case 0x59: /* FRINTX */
12170 case 0x79: /* FRINTI */
12171 need_fpstatus
= true;
12172 if (size
== 3 && !is_q
) {
12173 unallocated_encoding(s
);
12177 case 0x58: /* FRINTA */
12179 rmode
= FPROUNDING_TIEAWAY
;
12180 need_fpstatus
= true;
12181 if (size
== 3 && !is_q
) {
12182 unallocated_encoding(s
);
12186 case 0x7c: /* URSQRTE */
12188 unallocated_encoding(s
);
12191 need_fpstatus
= true;
12193 case 0x1e: /* FRINT32Z */
12194 case 0x1f: /* FRINT64Z */
12196 rmode
= FPROUNDING_ZERO
;
12198 case 0x5e: /* FRINT32X */
12199 case 0x5f: /* FRINT64X */
12200 need_fpstatus
= true;
12201 if ((size
== 3 && !is_q
) || !dc_isar_feature(aa64_frint
, s
)) {
12202 unallocated_encoding(s
);
12207 unallocated_encoding(s
);
12213 unallocated_encoding(s
);
12217 if (!fp_access_check(s
)) {
12221 if (need_fpstatus
|| need_rmode
) {
12222 tcg_fpstatus
= get_fpstatus_ptr(false);
12224 tcg_fpstatus
= NULL
;
12227 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
12228 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12235 if (u
&& size
== 0) { /* NOT */
12236 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_not
, 0);
12241 if (u
) { /* ABS, NEG */
12242 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_neg
, size
);
12244 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_abs
, size
);
12250 /* All 64-bit element operations can be shared with scalar 2misc */
12253 /* Coverity claims (size == 3 && !is_q) has been eliminated
12254 * from all paths leading to here.
12256 tcg_debug_assert(is_q
);
12257 for (pass
= 0; pass
< 2; pass
++) {
12258 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12259 TCGv_i64 tcg_res
= tcg_temp_new_i64();
12261 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12263 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
12264 tcg_rmode
, tcg_fpstatus
);
12266 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12268 tcg_temp_free_i64(tcg_res
);
12269 tcg_temp_free_i64(tcg_op
);
12274 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
12275 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12276 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12279 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
12282 /* Special cases for 32 bit elements */
12284 case 0xa: /* CMLT */
12285 /* 32 bit integer comparison against zero, result is
12286 * test ? (2^32 - 1) : 0. We implement via setcond(test)
12289 cond
= TCG_COND_LT
;
12291 tcg_gen_setcondi_i32(cond
, tcg_res
, tcg_op
, 0);
12292 tcg_gen_neg_i32(tcg_res
, tcg_res
);
12294 case 0x8: /* CMGT, CMGE */
12295 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
12297 case 0x9: /* CMEQ, CMLE */
12298 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
12300 case 0x4: /* CLS */
12302 tcg_gen_clzi_i32(tcg_res
, tcg_op
, 32);
12304 tcg_gen_clrsb_i32(tcg_res
, tcg_op
);
12307 case 0x7: /* SQABS, SQNEG */
12309 gen_helper_neon_qneg_s32(tcg_res
, cpu_env
, tcg_op
);
12311 gen_helper_neon_qabs_s32(tcg_res
, cpu_env
, tcg_op
);
12314 case 0x2f: /* FABS */
12315 gen_helper_vfp_abss(tcg_res
, tcg_op
);
12317 case 0x6f: /* FNEG */
12318 gen_helper_vfp_negs(tcg_res
, tcg_op
);
12320 case 0x7f: /* FSQRT */
12321 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
12323 case 0x1a: /* FCVTNS */
12324 case 0x1b: /* FCVTMS */
12325 case 0x1c: /* FCVTAS */
12326 case 0x3a: /* FCVTPS */
12327 case 0x3b: /* FCVTZS */
12329 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12330 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
12331 tcg_shift
, tcg_fpstatus
);
12332 tcg_temp_free_i32(tcg_shift
);
12335 case 0x5a: /* FCVTNU */
12336 case 0x5b: /* FCVTMU */
12337 case 0x5c: /* FCVTAU */
12338 case 0x7a: /* FCVTPU */
12339 case 0x7b: /* FCVTZU */
12341 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12342 gen_helper_vfp_touls(tcg_res
, tcg_op
,
12343 tcg_shift
, tcg_fpstatus
);
12344 tcg_temp_free_i32(tcg_shift
);
12347 case 0x18: /* FRINTN */
12348 case 0x19: /* FRINTM */
12349 case 0x38: /* FRINTP */
12350 case 0x39: /* FRINTZ */
12351 case 0x58: /* FRINTA */
12352 case 0x79: /* FRINTI */
12353 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
12355 case 0x59: /* FRINTX */
12356 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12358 case 0x7c: /* URSQRTE */
12359 gen_helper_rsqrte_u32(tcg_res
, tcg_op
, tcg_fpstatus
);
12361 case 0x1e: /* FRINT32Z */
12362 case 0x5e: /* FRINT32X */
12363 gen_helper_frint32_s(tcg_res
, tcg_op
, tcg_fpstatus
);
12365 case 0x1f: /* FRINT64Z */
12366 case 0x5f: /* FRINT64X */
12367 gen_helper_frint64_s(tcg_res
, tcg_op
, tcg_fpstatus
);
12370 g_assert_not_reached();
12373 /* Use helpers for 8 and 16 bit elements */
12375 case 0x5: /* CNT, RBIT */
12376 /* For these two insns size is part of the opcode specifier
12377 * (handled earlier); they always operate on byte elements.
12380 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
12382 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
12385 case 0x7: /* SQABS, SQNEG */
12387 NeonGenOneOpEnvFn
*genfn
;
12388 static NeonGenOneOpEnvFn
* const fns
[2][2] = {
12389 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
12390 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
12392 genfn
= fns
[size
][u
];
12393 genfn(tcg_res
, cpu_env
, tcg_op
);
12396 case 0x8: /* CMGT, CMGE */
12397 case 0x9: /* CMEQ, CMLE */
12398 case 0xa: /* CMLT */
12400 static NeonGenTwoOpFn
* const fns
[3][2] = {
12401 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_s16
},
12402 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_s16
},
12403 { gen_helper_neon_ceq_u8
, gen_helper_neon_ceq_u16
},
12405 NeonGenTwoOpFn
*genfn
;
12408 TCGv_i32 tcg_zero
= tcg_const_i32(0);
12410 /* comp = index into [CMGT, CMGE, CMEQ, CMLE, CMLT] */
12411 comp
= (opcode
- 0x8) * 2 + u
;
12412 /* ...but LE, LT are implemented as reverse GE, GT */
12413 reverse
= (comp
> 2);
12417 genfn
= fns
[comp
][size
];
12419 genfn(tcg_res
, tcg_zero
, tcg_op
);
12421 genfn(tcg_res
, tcg_op
, tcg_zero
);
12423 tcg_temp_free_i32(tcg_zero
);
12426 case 0x4: /* CLS, CLZ */
12429 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
12431 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
12435 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
12437 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
12442 g_assert_not_reached();
12446 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
12448 tcg_temp_free_i32(tcg_res
);
12449 tcg_temp_free_i32(tcg_op
);
12452 clear_vec_high(s
, is_q
, rd
);
12455 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12456 tcg_temp_free_i32(tcg_rmode
);
12458 if (need_fpstatus
) {
12459 tcg_temp_free_ptr(tcg_fpstatus
);
12463 /* AdvSIMD [scalar] two register miscellaneous (FP16)
12465 * 31 30 29 28 27 24 23 22 21 17 16 12 11 10 9 5 4 0
12466 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12467 * | 0 | Q | U | S | 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd |
12468 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12469 * mask: 1000 1111 0111 1110 0000 1100 0000 0000 0x8f7e 0c00
12470 * val: 0000 1110 0111 1000 0000 1000 0000 0000 0x0e78 0800
12472 * This actually covers two groups where scalar access is governed by
12473 * bit 28. A bunch of the instructions (float to integral) only exist
12474 * in the vector form and are un-allocated for the scalar decode. Also
12475 * in the scalar decode Q is always 1.
12477 static void disas_simd_two_reg_misc_fp16(DisasContext
*s
, uint32_t insn
)
12479 int fpop
, opcode
, a
, u
;
12483 bool only_in_vector
= false;
12486 TCGv_i32 tcg_rmode
= NULL
;
12487 TCGv_ptr tcg_fpstatus
= NULL
;
12488 bool need_rmode
= false;
12489 bool need_fpst
= true;
12492 if (!dc_isar_feature(aa64_fp16
, s
)) {
12493 unallocated_encoding(s
);
12497 rd
= extract32(insn
, 0, 5);
12498 rn
= extract32(insn
, 5, 5);
12500 a
= extract32(insn
, 23, 1);
12501 u
= extract32(insn
, 29, 1);
12502 is_scalar
= extract32(insn
, 28, 1);
12503 is_q
= extract32(insn
, 30, 1);
12505 opcode
= extract32(insn
, 12, 5);
12506 fpop
= deposit32(opcode
, 5, 1, a
);
12507 fpop
= deposit32(fpop
, 6, 1, u
);
12509 rd
= extract32(insn
, 0, 5);
12510 rn
= extract32(insn
, 5, 5);
12513 case 0x1d: /* SCVTF */
12514 case 0x5d: /* UCVTF */
12521 elements
= (is_q
? 8 : 4);
12524 if (!fp_access_check(s
)) {
12527 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !u
, 0, MO_16
);
12531 case 0x2c: /* FCMGT (zero) */
12532 case 0x2d: /* FCMEQ (zero) */
12533 case 0x2e: /* FCMLT (zero) */
12534 case 0x6c: /* FCMGE (zero) */
12535 case 0x6d: /* FCMLE (zero) */
12536 handle_2misc_fcmp_zero(s
, fpop
, is_scalar
, 0, is_q
, MO_16
, rn
, rd
);
12538 case 0x3d: /* FRECPE */
12539 case 0x3f: /* FRECPX */
12541 case 0x18: /* FRINTN */
12543 only_in_vector
= true;
12544 rmode
= FPROUNDING_TIEEVEN
;
12546 case 0x19: /* FRINTM */
12548 only_in_vector
= true;
12549 rmode
= FPROUNDING_NEGINF
;
12551 case 0x38: /* FRINTP */
12553 only_in_vector
= true;
12554 rmode
= FPROUNDING_POSINF
;
12556 case 0x39: /* FRINTZ */
12558 only_in_vector
= true;
12559 rmode
= FPROUNDING_ZERO
;
12561 case 0x58: /* FRINTA */
12563 only_in_vector
= true;
12564 rmode
= FPROUNDING_TIEAWAY
;
12566 case 0x59: /* FRINTX */
12567 case 0x79: /* FRINTI */
12568 only_in_vector
= true;
12569 /* current rounding mode */
12571 case 0x1a: /* FCVTNS */
12573 rmode
= FPROUNDING_TIEEVEN
;
12575 case 0x1b: /* FCVTMS */
12577 rmode
= FPROUNDING_NEGINF
;
12579 case 0x1c: /* FCVTAS */
12581 rmode
= FPROUNDING_TIEAWAY
;
12583 case 0x3a: /* FCVTPS */
12585 rmode
= FPROUNDING_POSINF
;
12587 case 0x3b: /* FCVTZS */
12589 rmode
= FPROUNDING_ZERO
;
12591 case 0x5a: /* FCVTNU */
12593 rmode
= FPROUNDING_TIEEVEN
;
12595 case 0x5b: /* FCVTMU */
12597 rmode
= FPROUNDING_NEGINF
;
12599 case 0x5c: /* FCVTAU */
12601 rmode
= FPROUNDING_TIEAWAY
;
12603 case 0x7a: /* FCVTPU */
12605 rmode
= FPROUNDING_POSINF
;
12607 case 0x7b: /* FCVTZU */
12609 rmode
= FPROUNDING_ZERO
;
12611 case 0x2f: /* FABS */
12612 case 0x6f: /* FNEG */
12615 case 0x7d: /* FRSQRTE */
12616 case 0x7f: /* FSQRT (vector) */
12619 fprintf(stderr
, "%s: insn %#04x fpop %#2x\n", __func__
, insn
, fpop
);
12620 g_assert_not_reached();
12624 /* Check additional constraints for the scalar encoding */
12627 unallocated_encoding(s
);
12630 /* FRINTxx is only in the vector form */
12631 if (only_in_vector
) {
12632 unallocated_encoding(s
);
12637 if (!fp_access_check(s
)) {
12641 if (need_rmode
|| need_fpst
) {
12642 tcg_fpstatus
= get_fpstatus_ptr(true);
12646 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
12647 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12651 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
12652 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12655 case 0x1a: /* FCVTNS */
12656 case 0x1b: /* FCVTMS */
12657 case 0x1c: /* FCVTAS */
12658 case 0x3a: /* FCVTPS */
12659 case 0x3b: /* FCVTZS */
12660 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12662 case 0x3d: /* FRECPE */
12663 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12665 case 0x3f: /* FRECPX */
12666 gen_helper_frecpx_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12668 case 0x5a: /* FCVTNU */
12669 case 0x5b: /* FCVTMU */
12670 case 0x5c: /* FCVTAU */
12671 case 0x7a: /* FCVTPU */
12672 case 0x7b: /* FCVTZU */
12673 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12675 case 0x6f: /* FNEG */
12676 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
12678 case 0x7d: /* FRSQRTE */
12679 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12682 g_assert_not_reached();
12685 /* limit any sign extension going on */
12686 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0xffff);
12687 write_fp_sreg(s
, rd
, tcg_res
);
12689 tcg_temp_free_i32(tcg_res
);
12690 tcg_temp_free_i32(tcg_op
);
12692 for (pass
= 0; pass
< (is_q
? 8 : 4); pass
++) {
12693 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12694 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12696 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_16
);
12699 case 0x1a: /* FCVTNS */
12700 case 0x1b: /* FCVTMS */
12701 case 0x1c: /* FCVTAS */
12702 case 0x3a: /* FCVTPS */
12703 case 0x3b: /* FCVTZS */
12704 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12706 case 0x3d: /* FRECPE */
12707 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12709 case 0x5a: /* FCVTNU */
12710 case 0x5b: /* FCVTMU */
12711 case 0x5c: /* FCVTAU */
12712 case 0x7a: /* FCVTPU */
12713 case 0x7b: /* FCVTZU */
12714 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12716 case 0x18: /* FRINTN */
12717 case 0x19: /* FRINTM */
12718 case 0x38: /* FRINTP */
12719 case 0x39: /* FRINTZ */
12720 case 0x58: /* FRINTA */
12721 case 0x79: /* FRINTI */
12722 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12724 case 0x59: /* FRINTX */
12725 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12727 case 0x2f: /* FABS */
12728 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
12730 case 0x6f: /* FNEG */
12731 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
12733 case 0x7d: /* FRSQRTE */
12734 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12736 case 0x7f: /* FSQRT */
12737 gen_helper_sqrt_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12740 g_assert_not_reached();
12743 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
12745 tcg_temp_free_i32(tcg_res
);
12746 tcg_temp_free_i32(tcg_op
);
12749 clear_vec_high(s
, is_q
, rd
);
12753 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12754 tcg_temp_free_i32(tcg_rmode
);
12757 if (tcg_fpstatus
) {
12758 tcg_temp_free_ptr(tcg_fpstatus
);
12762 /* AdvSIMD scalar x indexed element
12763 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
12764 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
12765 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
12766 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
12767 * AdvSIMD vector x indexed element
12768 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
12769 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
12770 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
12771 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
12773 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
12775 /* This encoding has two kinds of instruction:
12776 * normal, where we perform elt x idxelt => elt for each
12777 * element in the vector
12778 * long, where we perform elt x idxelt and generate a result of
12779 * double the width of the input element
12780 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
12782 bool is_scalar
= extract32(insn
, 28, 1);
12783 bool is_q
= extract32(insn
, 30, 1);
12784 bool u
= extract32(insn
, 29, 1);
12785 int size
= extract32(insn
, 22, 2);
12786 int l
= extract32(insn
, 21, 1);
12787 int m
= extract32(insn
, 20, 1);
12788 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
12789 int rm
= extract32(insn
, 16, 4);
12790 int opcode
= extract32(insn
, 12, 4);
12791 int h
= extract32(insn
, 11, 1);
12792 int rn
= extract32(insn
, 5, 5);
12793 int rd
= extract32(insn
, 0, 5);
12794 bool is_long
= false;
12796 bool is_fp16
= false;
12800 switch (16 * u
+ opcode
) {
12801 case 0x08: /* MUL */
12802 case 0x10: /* MLA */
12803 case 0x14: /* MLS */
12805 unallocated_encoding(s
);
12809 case 0x02: /* SMLAL, SMLAL2 */
12810 case 0x12: /* UMLAL, UMLAL2 */
12811 case 0x06: /* SMLSL, SMLSL2 */
12812 case 0x16: /* UMLSL, UMLSL2 */
12813 case 0x0a: /* SMULL, SMULL2 */
12814 case 0x1a: /* UMULL, UMULL2 */
12816 unallocated_encoding(s
);
12821 case 0x03: /* SQDMLAL, SQDMLAL2 */
12822 case 0x07: /* SQDMLSL, SQDMLSL2 */
12823 case 0x0b: /* SQDMULL, SQDMULL2 */
12826 case 0x0c: /* SQDMULH */
12827 case 0x0d: /* SQRDMULH */
12829 case 0x01: /* FMLA */
12830 case 0x05: /* FMLS */
12831 case 0x09: /* FMUL */
12832 case 0x19: /* FMULX */
12835 case 0x1d: /* SQRDMLAH */
12836 case 0x1f: /* SQRDMLSH */
12837 if (!dc_isar_feature(aa64_rdm
, s
)) {
12838 unallocated_encoding(s
);
12842 case 0x0e: /* SDOT */
12843 case 0x1e: /* UDOT */
12844 if (is_scalar
|| size
!= MO_32
|| !dc_isar_feature(aa64_dp
, s
)) {
12845 unallocated_encoding(s
);
12849 case 0x11: /* FCMLA #0 */
12850 case 0x13: /* FCMLA #90 */
12851 case 0x15: /* FCMLA #180 */
12852 case 0x17: /* FCMLA #270 */
12853 if (is_scalar
|| !dc_isar_feature(aa64_fcma
, s
)) {
12854 unallocated_encoding(s
);
12859 case 0x00: /* FMLAL */
12860 case 0x04: /* FMLSL */
12861 case 0x18: /* FMLAL2 */
12862 case 0x1c: /* FMLSL2 */
12863 if (is_scalar
|| size
!= MO_32
|| !dc_isar_feature(aa64_fhm
, s
)) {
12864 unallocated_encoding(s
);
12868 /* is_fp, but we pass cpu_env not fp_status. */
12871 unallocated_encoding(s
);
12876 case 1: /* normal fp */
12877 /* convert insn encoded size to MemOp size */
12879 case 0: /* half-precision */
12883 case MO_32
: /* single precision */
12884 case MO_64
: /* double precision */
12887 unallocated_encoding(s
);
12892 case 2: /* complex fp */
12893 /* Each indexable element is a complex pair. */
12898 unallocated_encoding(s
);
12906 unallocated_encoding(s
);
12911 default: /* integer */
12915 unallocated_encoding(s
);
12920 if (is_fp16
&& !dc_isar_feature(aa64_fp16
, s
)) {
12921 unallocated_encoding(s
);
12925 /* Given MemOp size, adjust register and indexing. */
12928 index
= h
<< 2 | l
<< 1 | m
;
12931 index
= h
<< 1 | l
;
12936 unallocated_encoding(s
);
12943 g_assert_not_reached();
12946 if (!fp_access_check(s
)) {
12951 fpst
= get_fpstatus_ptr(is_fp16
);
12956 switch (16 * u
+ opcode
) {
12957 case 0x0e: /* SDOT */
12958 case 0x1e: /* UDOT */
12959 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, index
,
12960 u
? gen_helper_gvec_udot_idx_b
12961 : gen_helper_gvec_sdot_idx_b
);
12963 case 0x11: /* FCMLA #0 */
12964 case 0x13: /* FCMLA #90 */
12965 case 0x15: /* FCMLA #180 */
12966 case 0x17: /* FCMLA #270 */
12968 int rot
= extract32(insn
, 13, 2);
12969 int data
= (index
<< 2) | rot
;
12970 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
12971 vec_full_reg_offset(s
, rn
),
12972 vec_full_reg_offset(s
, rm
), fpst
,
12973 is_q
? 16 : 8, vec_full_reg_size(s
), data
,
12975 ? gen_helper_gvec_fcmlas_idx
12976 : gen_helper_gvec_fcmlah_idx
);
12977 tcg_temp_free_ptr(fpst
);
12981 case 0x00: /* FMLAL */
12982 case 0x04: /* FMLSL */
12983 case 0x18: /* FMLAL2 */
12984 case 0x1c: /* FMLSL2 */
12986 int is_s
= extract32(opcode
, 2, 1);
12988 int data
= (index
<< 2) | (is_2
<< 1) | is_s
;
12989 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
12990 vec_full_reg_offset(s
, rn
),
12991 vec_full_reg_offset(s
, rm
), cpu_env
,
12992 is_q
? 16 : 8, vec_full_reg_size(s
),
12993 data
, gen_helper_gvec_fmlal_idx_a64
);
12999 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
13002 assert(is_fp
&& is_q
&& !is_long
);
13004 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
13006 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13007 TCGv_i64 tcg_op
= tcg_temp_new_i64();
13008 TCGv_i64 tcg_res
= tcg_temp_new_i64();
13010 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
13012 switch (16 * u
+ opcode
) {
13013 case 0x05: /* FMLS */
13014 /* As usual for ARM, separate negation for fused multiply-add */
13015 gen_helper_vfp_negd(tcg_op
, tcg_op
);
13017 case 0x01: /* FMLA */
13018 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
13019 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
13021 case 0x09: /* FMUL */
13022 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13024 case 0x19: /* FMULX */
13025 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13028 g_assert_not_reached();
13031 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
13032 tcg_temp_free_i64(tcg_op
);
13033 tcg_temp_free_i64(tcg_res
);
13036 tcg_temp_free_i64(tcg_idx
);
13037 clear_vec_high(s
, !is_scalar
, rd
);
13038 } else if (!is_long
) {
13039 /* 32 bit floating point, or 16 or 32 bit integer.
13040 * For the 16 bit scalar case we use the usual Neon helpers and
13041 * rely on the fact that 0 op 0 == 0 with no side effects.
13043 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
13044 int pass
, maxpasses
;
13049 maxpasses
= is_q
? 4 : 2;
13052 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
13054 if (size
== 1 && !is_scalar
) {
13055 /* The simplest way to handle the 16x16 indexed ops is to duplicate
13056 * the index into both halves of the 32 bit tcg_idx and then use
13057 * the usual Neon helpers.
13059 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
13062 for (pass
= 0; pass
< maxpasses
; pass
++) {
13063 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13064 TCGv_i32 tcg_res
= tcg_temp_new_i32();
13066 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
13068 switch (16 * u
+ opcode
) {
13069 case 0x08: /* MUL */
13070 case 0x10: /* MLA */
13071 case 0x14: /* MLS */
13073 static NeonGenTwoOpFn
* const fns
[2][2] = {
13074 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
13075 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
13077 NeonGenTwoOpFn
*genfn
;
13078 bool is_sub
= opcode
== 0x4;
13081 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
13083 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
13085 if (opcode
== 0x8) {
13088 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
13089 genfn
= fns
[size
- 1][is_sub
];
13090 genfn(tcg_res
, tcg_op
, tcg_res
);
13093 case 0x05: /* FMLS */
13094 case 0x01: /* FMLA */
13095 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13096 is_scalar
? size
: MO_32
);
13099 if (opcode
== 0x5) {
13100 /* As usual for ARM, separate negation for fused
13102 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80008000);
13105 gen_helper_advsimd_muladdh(tcg_res
, tcg_op
, tcg_idx
,
13108 gen_helper_advsimd_muladd2h(tcg_res
, tcg_op
, tcg_idx
,
13113 if (opcode
== 0x5) {
13114 /* As usual for ARM, separate negation for
13115 * fused multiply-add */
13116 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80000000);
13118 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
,
13122 g_assert_not_reached();
13125 case 0x09: /* FMUL */
13129 gen_helper_advsimd_mulh(tcg_res
, tcg_op
,
13132 gen_helper_advsimd_mul2h(tcg_res
, tcg_op
,
13137 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13140 g_assert_not_reached();
13143 case 0x19: /* FMULX */
13147 gen_helper_advsimd_mulxh(tcg_res
, tcg_op
,
13150 gen_helper_advsimd_mulx2h(tcg_res
, tcg_op
,
13155 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13158 g_assert_not_reached();
13161 case 0x0c: /* SQDMULH */
13163 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
13166 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
13170 case 0x0d: /* SQRDMULH */
13172 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
13175 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
13179 case 0x1d: /* SQRDMLAH */
13180 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13181 is_scalar
? size
: MO_32
);
13183 gen_helper_neon_qrdmlah_s16(tcg_res
, cpu_env
,
13184 tcg_op
, tcg_idx
, tcg_res
);
13186 gen_helper_neon_qrdmlah_s32(tcg_res
, cpu_env
,
13187 tcg_op
, tcg_idx
, tcg_res
);
13190 case 0x1f: /* SQRDMLSH */
13191 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13192 is_scalar
? size
: MO_32
);
13194 gen_helper_neon_qrdmlsh_s16(tcg_res
, cpu_env
,
13195 tcg_op
, tcg_idx
, tcg_res
);
13197 gen_helper_neon_qrdmlsh_s32(tcg_res
, cpu_env
,
13198 tcg_op
, tcg_idx
, tcg_res
);
13202 g_assert_not_reached();
13206 write_fp_sreg(s
, rd
, tcg_res
);
13208 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
13211 tcg_temp_free_i32(tcg_op
);
13212 tcg_temp_free_i32(tcg_res
);
13215 tcg_temp_free_i32(tcg_idx
);
13216 clear_vec_high(s
, is_q
, rd
);
13218 /* long ops: 16x16->32 or 32x32->64 */
13219 TCGv_i64 tcg_res
[2];
13221 bool satop
= extract32(opcode
, 0, 1);
13222 MemOp memop
= MO_32
;
13229 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
13231 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
13233 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13234 TCGv_i64 tcg_op
= tcg_temp_new_i64();
13235 TCGv_i64 tcg_passres
;
13241 passelt
= pass
+ (is_q
* 2);
13244 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
13246 tcg_res
[pass
] = tcg_temp_new_i64();
13248 if (opcode
== 0xa || opcode
== 0xb) {
13249 /* Non-accumulating ops */
13250 tcg_passres
= tcg_res
[pass
];
13252 tcg_passres
= tcg_temp_new_i64();
13255 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
13256 tcg_temp_free_i64(tcg_op
);
13259 /* saturating, doubling */
13260 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
13261 tcg_passres
, tcg_passres
);
13264 if (opcode
== 0xa || opcode
== 0xb) {
13268 /* Accumulating op: handle accumulate step */
13269 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13272 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13273 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13275 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13276 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13278 case 0x7: /* SQDMLSL, SQDMLSL2 */
13279 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
13281 case 0x3: /* SQDMLAL, SQDMLAL2 */
13282 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
13287 g_assert_not_reached();
13289 tcg_temp_free_i64(tcg_passres
);
13291 tcg_temp_free_i64(tcg_idx
);
13293 clear_vec_high(s
, !is_scalar
, rd
);
13295 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
13298 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
13301 /* The simplest way to handle the 16x16 indexed ops is to
13302 * duplicate the index into both halves of the 32 bit tcg_idx
13303 * and then use the usual Neon helpers.
13305 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
13308 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13309 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13310 TCGv_i64 tcg_passres
;
13313 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
13315 read_vec_element_i32(s
, tcg_op
, rn
,
13316 pass
+ (is_q
* 2), MO_32
);
13319 tcg_res
[pass
] = tcg_temp_new_i64();
13321 if (opcode
== 0xa || opcode
== 0xb) {
13322 /* Non-accumulating ops */
13323 tcg_passres
= tcg_res
[pass
];
13325 tcg_passres
= tcg_temp_new_i64();
13328 if (memop
& MO_SIGN
) {
13329 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
13331 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
13334 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
13335 tcg_passres
, tcg_passres
);
13337 tcg_temp_free_i32(tcg_op
);
13339 if (opcode
== 0xa || opcode
== 0xb) {
13343 /* Accumulating op: handle accumulate step */
13344 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13347 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13348 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
13351 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13352 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
13355 case 0x7: /* SQDMLSL, SQDMLSL2 */
13356 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
13358 case 0x3: /* SQDMLAL, SQDMLAL2 */
13359 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
13364 g_assert_not_reached();
13366 tcg_temp_free_i64(tcg_passres
);
13368 tcg_temp_free_i32(tcg_idx
);
13371 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
13376 tcg_res
[1] = tcg_const_i64(0);
13379 for (pass
= 0; pass
< 2; pass
++) {
13380 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13381 tcg_temp_free_i64(tcg_res
[pass
]);
13386 tcg_temp_free_ptr(fpst
);
13391 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
13392 * +-----------------+------+-----------+--------+-----+------+------+
13393 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
13394 * +-----------------+------+-----------+--------+-----+------+------+
13396 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
13398 int size
= extract32(insn
, 22, 2);
13399 int opcode
= extract32(insn
, 12, 5);
13400 int rn
= extract32(insn
, 5, 5);
13401 int rd
= extract32(insn
, 0, 5);
13403 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
13404 TCGv_i32 tcg_decrypt
;
13405 CryptoThreeOpIntFn
*genfn
;
13407 if (!dc_isar_feature(aa64_aes
, s
) || size
!= 0) {
13408 unallocated_encoding(s
);
13413 case 0x4: /* AESE */
13415 genfn
= gen_helper_crypto_aese
;
13417 case 0x6: /* AESMC */
13419 genfn
= gen_helper_crypto_aesmc
;
13421 case 0x5: /* AESD */
13423 genfn
= gen_helper_crypto_aese
;
13425 case 0x7: /* AESIMC */
13427 genfn
= gen_helper_crypto_aesmc
;
13430 unallocated_encoding(s
);
13434 if (!fp_access_check(s
)) {
13438 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13439 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13440 tcg_decrypt
= tcg_const_i32(decrypt
);
13442 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_decrypt
);
13444 tcg_temp_free_ptr(tcg_rd_ptr
);
13445 tcg_temp_free_ptr(tcg_rn_ptr
);
13446 tcg_temp_free_i32(tcg_decrypt
);
13449 /* Crypto three-reg SHA
13450 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
13451 * +-----------------+------+---+------+---+--------+-----+------+------+
13452 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
13453 * +-----------------+------+---+------+---+--------+-----+------+------+
13455 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
13457 int size
= extract32(insn
, 22, 2);
13458 int opcode
= extract32(insn
, 12, 3);
13459 int rm
= extract32(insn
, 16, 5);
13460 int rn
= extract32(insn
, 5, 5);
13461 int rd
= extract32(insn
, 0, 5);
13462 CryptoThreeOpFn
*genfn
;
13463 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
13467 unallocated_encoding(s
);
13472 case 0: /* SHA1C */
13473 case 1: /* SHA1P */
13474 case 2: /* SHA1M */
13475 case 3: /* SHA1SU0 */
13477 feature
= dc_isar_feature(aa64_sha1
, s
);
13479 case 4: /* SHA256H */
13480 genfn
= gen_helper_crypto_sha256h
;
13481 feature
= dc_isar_feature(aa64_sha256
, s
);
13483 case 5: /* SHA256H2 */
13484 genfn
= gen_helper_crypto_sha256h2
;
13485 feature
= dc_isar_feature(aa64_sha256
, s
);
13487 case 6: /* SHA256SU1 */
13488 genfn
= gen_helper_crypto_sha256su1
;
13489 feature
= dc_isar_feature(aa64_sha256
, s
);
13492 unallocated_encoding(s
);
13497 unallocated_encoding(s
);
13501 if (!fp_access_check(s
)) {
13505 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13506 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13507 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
13510 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
);
13512 TCGv_i32 tcg_opcode
= tcg_const_i32(opcode
);
13514 gen_helper_crypto_sha1_3reg(tcg_rd_ptr
, tcg_rn_ptr
,
13515 tcg_rm_ptr
, tcg_opcode
);
13516 tcg_temp_free_i32(tcg_opcode
);
13519 tcg_temp_free_ptr(tcg_rd_ptr
);
13520 tcg_temp_free_ptr(tcg_rn_ptr
);
13521 tcg_temp_free_ptr(tcg_rm_ptr
);
13524 /* Crypto two-reg SHA
13525 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
13526 * +-----------------+------+-----------+--------+-----+------+------+
13527 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
13528 * +-----------------+------+-----------+--------+-----+------+------+
13530 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
13532 int size
= extract32(insn
, 22, 2);
13533 int opcode
= extract32(insn
, 12, 5);
13534 int rn
= extract32(insn
, 5, 5);
13535 int rd
= extract32(insn
, 0, 5);
13536 CryptoTwoOpFn
*genfn
;
13538 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
13541 unallocated_encoding(s
);
13546 case 0: /* SHA1H */
13547 feature
= dc_isar_feature(aa64_sha1
, s
);
13548 genfn
= gen_helper_crypto_sha1h
;
13550 case 1: /* SHA1SU1 */
13551 feature
= dc_isar_feature(aa64_sha1
, s
);
13552 genfn
= gen_helper_crypto_sha1su1
;
13554 case 2: /* SHA256SU0 */
13555 feature
= dc_isar_feature(aa64_sha256
, s
);
13556 genfn
= gen_helper_crypto_sha256su0
;
13559 unallocated_encoding(s
);
13564 unallocated_encoding(s
);
13568 if (!fp_access_check(s
)) {
13572 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13573 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13575 genfn(tcg_rd_ptr
, tcg_rn_ptr
);
13577 tcg_temp_free_ptr(tcg_rd_ptr
);
13578 tcg_temp_free_ptr(tcg_rn_ptr
);
13581 /* Crypto three-reg SHA512
13582 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
13583 * +-----------------------+------+---+---+-----+--------+------+------+
13584 * | 1 1 0 0 1 1 1 0 0 1 1 | Rm | 1 | O | 0 0 | opcode | Rn | Rd |
13585 * +-----------------------+------+---+---+-----+--------+------+------+
13587 static void disas_crypto_three_reg_sha512(DisasContext
*s
, uint32_t insn
)
13589 int opcode
= extract32(insn
, 10, 2);
13590 int o
= extract32(insn
, 14, 1);
13591 int rm
= extract32(insn
, 16, 5);
13592 int rn
= extract32(insn
, 5, 5);
13593 int rd
= extract32(insn
, 0, 5);
13595 CryptoThreeOpFn
*genfn
;
13599 case 0: /* SHA512H */
13600 feature
= dc_isar_feature(aa64_sha512
, s
);
13601 genfn
= gen_helper_crypto_sha512h
;
13603 case 1: /* SHA512H2 */
13604 feature
= dc_isar_feature(aa64_sha512
, s
);
13605 genfn
= gen_helper_crypto_sha512h2
;
13607 case 2: /* SHA512SU1 */
13608 feature
= dc_isar_feature(aa64_sha512
, s
);
13609 genfn
= gen_helper_crypto_sha512su1
;
13612 feature
= dc_isar_feature(aa64_sha3
, s
);
13616 g_assert_not_reached();
13620 case 0: /* SM3PARTW1 */
13621 feature
= dc_isar_feature(aa64_sm3
, s
);
13622 genfn
= gen_helper_crypto_sm3partw1
;
13624 case 1: /* SM3PARTW2 */
13625 feature
= dc_isar_feature(aa64_sm3
, s
);
13626 genfn
= gen_helper_crypto_sm3partw2
;
13628 case 2: /* SM4EKEY */
13629 feature
= dc_isar_feature(aa64_sm4
, s
);
13630 genfn
= gen_helper_crypto_sm4ekey
;
13633 unallocated_encoding(s
);
13639 unallocated_encoding(s
);
13643 if (!fp_access_check(s
)) {
13648 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
13650 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13651 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13652 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
13654 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
);
13656 tcg_temp_free_ptr(tcg_rd_ptr
);
13657 tcg_temp_free_ptr(tcg_rn_ptr
);
13658 tcg_temp_free_ptr(tcg_rm_ptr
);
13660 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
13663 tcg_op1
= tcg_temp_new_i64();
13664 tcg_op2
= tcg_temp_new_i64();
13665 tcg_res
[0] = tcg_temp_new_i64();
13666 tcg_res
[1] = tcg_temp_new_i64();
13668 for (pass
= 0; pass
< 2; pass
++) {
13669 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13670 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13672 tcg_gen_rotli_i64(tcg_res
[pass
], tcg_op2
, 1);
13673 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
13675 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13676 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13678 tcg_temp_free_i64(tcg_op1
);
13679 tcg_temp_free_i64(tcg_op2
);
13680 tcg_temp_free_i64(tcg_res
[0]);
13681 tcg_temp_free_i64(tcg_res
[1]);
13685 /* Crypto two-reg SHA512
13686 * 31 12 11 10 9 5 4 0
13687 * +-----------------------------------------+--------+------+------+
13688 * | 1 1 0 0 1 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 | opcode | Rn | Rd |
13689 * +-----------------------------------------+--------+------+------+
13691 static void disas_crypto_two_reg_sha512(DisasContext
*s
, uint32_t insn
)
13693 int opcode
= extract32(insn
, 10, 2);
13694 int rn
= extract32(insn
, 5, 5);
13695 int rd
= extract32(insn
, 0, 5);
13696 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
13698 CryptoTwoOpFn
*genfn
;
13701 case 0: /* SHA512SU0 */
13702 feature
= dc_isar_feature(aa64_sha512
, s
);
13703 genfn
= gen_helper_crypto_sha512su0
;
13706 feature
= dc_isar_feature(aa64_sm4
, s
);
13707 genfn
= gen_helper_crypto_sm4e
;
13710 unallocated_encoding(s
);
13715 unallocated_encoding(s
);
13719 if (!fp_access_check(s
)) {
13723 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13724 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13726 genfn(tcg_rd_ptr
, tcg_rn_ptr
);
13728 tcg_temp_free_ptr(tcg_rd_ptr
);
13729 tcg_temp_free_ptr(tcg_rn_ptr
);
13732 /* Crypto four-register
13733 * 31 23 22 21 20 16 15 14 10 9 5 4 0
13734 * +-------------------+-----+------+---+------+------+------+
13735 * | 1 1 0 0 1 1 1 0 0 | Op0 | Rm | 0 | Ra | Rn | Rd |
13736 * +-------------------+-----+------+---+------+------+------+
13738 static void disas_crypto_four_reg(DisasContext
*s
, uint32_t insn
)
13740 int op0
= extract32(insn
, 21, 2);
13741 int rm
= extract32(insn
, 16, 5);
13742 int ra
= extract32(insn
, 10, 5);
13743 int rn
= extract32(insn
, 5, 5);
13744 int rd
= extract32(insn
, 0, 5);
13750 feature
= dc_isar_feature(aa64_sha3
, s
);
13752 case 2: /* SM3SS1 */
13753 feature
= dc_isar_feature(aa64_sm3
, s
);
13756 unallocated_encoding(s
);
13761 unallocated_encoding(s
);
13765 if (!fp_access_check(s
)) {
13770 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
[2];
13773 tcg_op1
= tcg_temp_new_i64();
13774 tcg_op2
= tcg_temp_new_i64();
13775 tcg_op3
= tcg_temp_new_i64();
13776 tcg_res
[0] = tcg_temp_new_i64();
13777 tcg_res
[1] = tcg_temp_new_i64();
13779 for (pass
= 0; pass
< 2; pass
++) {
13780 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13781 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13782 read_vec_element(s
, tcg_op3
, ra
, pass
, MO_64
);
13786 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
13789 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
13791 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
13793 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13794 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13796 tcg_temp_free_i64(tcg_op1
);
13797 tcg_temp_free_i64(tcg_op2
);
13798 tcg_temp_free_i64(tcg_op3
);
13799 tcg_temp_free_i64(tcg_res
[0]);
13800 tcg_temp_free_i64(tcg_res
[1]);
13802 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
, tcg_zero
;
13804 tcg_op1
= tcg_temp_new_i32();
13805 tcg_op2
= tcg_temp_new_i32();
13806 tcg_op3
= tcg_temp_new_i32();
13807 tcg_res
= tcg_temp_new_i32();
13808 tcg_zero
= tcg_const_i32(0);
13810 read_vec_element_i32(s
, tcg_op1
, rn
, 3, MO_32
);
13811 read_vec_element_i32(s
, tcg_op2
, rm
, 3, MO_32
);
13812 read_vec_element_i32(s
, tcg_op3
, ra
, 3, MO_32
);
13814 tcg_gen_rotri_i32(tcg_res
, tcg_op1
, 20);
13815 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op2
);
13816 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op3
);
13817 tcg_gen_rotri_i32(tcg_res
, tcg_res
, 25);
13819 write_vec_element_i32(s
, tcg_zero
, rd
, 0, MO_32
);
13820 write_vec_element_i32(s
, tcg_zero
, rd
, 1, MO_32
);
13821 write_vec_element_i32(s
, tcg_zero
, rd
, 2, MO_32
);
13822 write_vec_element_i32(s
, tcg_res
, rd
, 3, MO_32
);
13824 tcg_temp_free_i32(tcg_op1
);
13825 tcg_temp_free_i32(tcg_op2
);
13826 tcg_temp_free_i32(tcg_op3
);
13827 tcg_temp_free_i32(tcg_res
);
13828 tcg_temp_free_i32(tcg_zero
);
13833 * 31 21 20 16 15 10 9 5 4 0
13834 * +-----------------------+------+--------+------+------+
13835 * | 1 1 0 0 1 1 1 0 1 0 0 | Rm | imm6 | Rn | Rd |
13836 * +-----------------------+------+--------+------+------+
13838 static void disas_crypto_xar(DisasContext
*s
, uint32_t insn
)
13840 int rm
= extract32(insn
, 16, 5);
13841 int imm6
= extract32(insn
, 10, 6);
13842 int rn
= extract32(insn
, 5, 5);
13843 int rd
= extract32(insn
, 0, 5);
13844 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
13847 if (!dc_isar_feature(aa64_sha3
, s
)) {
13848 unallocated_encoding(s
);
13852 if (!fp_access_check(s
)) {
13856 tcg_op1
= tcg_temp_new_i64();
13857 tcg_op2
= tcg_temp_new_i64();
13858 tcg_res
[0] = tcg_temp_new_i64();
13859 tcg_res
[1] = tcg_temp_new_i64();
13861 for (pass
= 0; pass
< 2; pass
++) {
13862 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13863 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13865 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
13866 tcg_gen_rotri_i64(tcg_res
[pass
], tcg_res
[pass
], imm6
);
13868 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13869 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13871 tcg_temp_free_i64(tcg_op1
);
13872 tcg_temp_free_i64(tcg_op2
);
13873 tcg_temp_free_i64(tcg_res
[0]);
13874 tcg_temp_free_i64(tcg_res
[1]);
13877 /* Crypto three-reg imm2
13878 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
13879 * +-----------------------+------+-----+------+--------+------+------+
13880 * | 1 1 0 0 1 1 1 0 0 1 0 | Rm | 1 0 | imm2 | opcode | Rn | Rd |
13881 * +-----------------------+------+-----+------+--------+------+------+
13883 static void disas_crypto_three_reg_imm2(DisasContext
*s
, uint32_t insn
)
13885 int opcode
= extract32(insn
, 10, 2);
13886 int imm2
= extract32(insn
, 12, 2);
13887 int rm
= extract32(insn
, 16, 5);
13888 int rn
= extract32(insn
, 5, 5);
13889 int rd
= extract32(insn
, 0, 5);
13890 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
13891 TCGv_i32 tcg_imm2
, tcg_opcode
;
13893 if (!dc_isar_feature(aa64_sm3
, s
)) {
13894 unallocated_encoding(s
);
13898 if (!fp_access_check(s
)) {
13902 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13903 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13904 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
13905 tcg_imm2
= tcg_const_i32(imm2
);
13906 tcg_opcode
= tcg_const_i32(opcode
);
13908 gen_helper_crypto_sm3tt(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
, tcg_imm2
,
13911 tcg_temp_free_ptr(tcg_rd_ptr
);
13912 tcg_temp_free_ptr(tcg_rn_ptr
);
13913 tcg_temp_free_ptr(tcg_rm_ptr
);
13914 tcg_temp_free_i32(tcg_imm2
);
13915 tcg_temp_free_i32(tcg_opcode
);
13918 /* C3.6 Data processing - SIMD, inc Crypto
13920 * As the decode gets a little complex we are using a table based
13921 * approach for this part of the decode.
13923 static const AArch64DecodeTable data_proc_simd
[] = {
13924 /* pattern , mask , fn */
13925 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
13926 { 0x0e008400, 0x9f208400, disas_simd_three_reg_same_extra
},
13927 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
13928 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
13929 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
13930 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
13931 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
13932 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
13933 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
13934 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
13935 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
13936 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
13937 { 0x2e000000, 0xbf208400, disas_simd_ext
},
13938 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
13939 { 0x5e008400, 0xdf208400, disas_simd_scalar_three_reg_same_extra
},
13940 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
13941 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
13942 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
13943 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
13944 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
13945 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
13946 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
13947 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
13948 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
13949 { 0xce608000, 0xffe0b000, disas_crypto_three_reg_sha512
},
13950 { 0xcec08000, 0xfffff000, disas_crypto_two_reg_sha512
},
13951 { 0xce000000, 0xff808000, disas_crypto_four_reg
},
13952 { 0xce800000, 0xffe00000, disas_crypto_xar
},
13953 { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2
},
13954 { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16
},
13955 { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16
},
13956 { 0x5e400400, 0xdf60c400, disas_simd_scalar_three_reg_same_fp16
},
13957 { 0x00000000, 0x00000000, NULL
}
13960 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
13962 /* Note that this is called with all non-FP cases from
13963 * table C3-6 so it must UNDEF for entries not specifically
13964 * allocated to instructions in that table.
13966 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
13970 unallocated_encoding(s
);
13974 /* C3.6 Data processing - SIMD and floating point */
13975 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
13977 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
13978 disas_data_proc_fp(s
, insn
);
13980 /* SIMD, including crypto */
13981 disas_data_proc_simd(s
, insn
);
13987 * @env: The cpu environment
13988 * @s: The DisasContext
13990 * Return true if the page is guarded.
13992 static bool is_guarded_page(CPUARMState
*env
, DisasContext
*s
)
13994 #ifdef CONFIG_USER_ONLY
13995 return false; /* FIXME */
13997 uint64_t addr
= s
->base
.pc_first
;
13998 int mmu_idx
= arm_to_core_mmu_idx(s
->mmu_idx
);
13999 unsigned int index
= tlb_index(env
, mmu_idx
, addr
);
14000 CPUTLBEntry
*entry
= tlb_entry(env
, mmu_idx
, addr
);
14003 * We test this immediately after reading an insn, which means
14004 * that any normal page must be in the TLB. The only exception
14005 * would be for executing from flash or device memory, which
14006 * does not retain the TLB entry.
14008 * FIXME: Assume false for those, for now. We could use
14009 * arm_cpu_get_phys_page_attrs_debug to re-read the page
14010 * table entry even for that case.
14012 return (tlb_hit(entry
->addr_code
, addr
) &&
14013 env_tlb(env
)->d
[mmu_idx
].iotlb
[index
].attrs
.target_tlb_bit0
);
14018 * btype_destination_ok:
14019 * @insn: The instruction at the branch destination
14020 * @bt: SCTLR_ELx.BT
14021 * @btype: PSTATE.BTYPE, and is non-zero
14023 * On a guarded page, there are a limited number of insns
14024 * that may be present at the branch target:
14025 * - branch target identifiers,
14026 * - paciasp, pacibsp,
14029 * Anything else causes a Branch Target Exception.
14031 * Return true if the branch is compatible, false to raise BTITRAP.
14033 static bool btype_destination_ok(uint32_t insn
, bool bt
, int btype
)
14035 if ((insn
& 0xfffff01fu
) == 0xd503201fu
) {
14037 switch (extract32(insn
, 5, 7)) {
14038 case 0b011001: /* PACIASP */
14039 case 0b011011: /* PACIBSP */
14041 * If SCTLR_ELx.BT, then PACI*SP are not compatible
14042 * with btype == 3. Otherwise all btype are ok.
14044 return !bt
|| btype
!= 3;
14045 case 0b100000: /* BTI */
14046 /* Not compatible with any btype. */
14048 case 0b100010: /* BTI c */
14049 /* Not compatible with btype == 3 */
14051 case 0b100100: /* BTI j */
14052 /* Not compatible with btype == 2 */
14054 case 0b100110: /* BTI jc */
14055 /* Compatible with any btype. */
14059 switch (insn
& 0xffe0001fu
) {
14060 case 0xd4200000u
: /* BRK */
14061 case 0xd4400000u
: /* HLT */
14062 /* Give priority to the breakpoint exception. */
14069 /* C3.1 A64 instruction index by encoding */
14070 static void disas_a64_insn(CPUARMState
*env
, DisasContext
*s
)
14074 s
->pc_curr
= s
->base
.pc_next
;
14075 insn
= arm_ldl_code(env
, s
->base
.pc_next
, s
->sctlr_b
);
14077 s
->base
.pc_next
+= 4;
14079 s
->fp_access_checked
= false;
14081 if (dc_isar_feature(aa64_bti
, s
)) {
14082 if (s
->base
.num_insns
== 1) {
14084 * At the first insn of the TB, compute s->guarded_page.
14085 * We delayed computing this until successfully reading
14086 * the first insn of the TB, above. This (mostly) ensures
14087 * that the softmmu tlb entry has been populated, and the
14088 * page table GP bit is available.
14090 * Note that we need to compute this even if btype == 0,
14091 * because this value is used for BR instructions later
14092 * where ENV is not available.
14094 s
->guarded_page
= is_guarded_page(env
, s
);
14096 /* First insn can have btype set to non-zero. */
14097 tcg_debug_assert(s
->btype
>= 0);
14100 * Note that the Branch Target Exception has fairly high
14101 * priority -- below debugging exceptions but above most
14102 * everything else. This allows us to handle this now
14103 * instead of waiting until the insn is otherwise decoded.
14107 && !btype_destination_ok(insn
, s
->bt
, s
->btype
)) {
14108 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
,
14109 syn_btitrap(s
->btype
),
14110 default_exception_el(s
));
14114 /* Not the first insn: btype must be 0. */
14115 tcg_debug_assert(s
->btype
== 0);
14119 switch (extract32(insn
, 25, 4)) {
14120 case 0x0: case 0x1: case 0x3: /* UNALLOCATED */
14121 unallocated_encoding(s
);
14124 if (!dc_isar_feature(aa64_sve
, s
) || !disas_sve(s
, insn
)) {
14125 unallocated_encoding(s
);
14128 case 0x8: case 0x9: /* Data processing - immediate */
14129 disas_data_proc_imm(s
, insn
);
14131 case 0xa: case 0xb: /* Branch, exception generation and system insns */
14132 disas_b_exc_sys(s
, insn
);
14137 case 0xe: /* Loads and stores */
14138 disas_ldst(s
, insn
);
14141 case 0xd: /* Data processing - register */
14142 disas_data_proc_reg(s
, insn
);
14145 case 0xf: /* Data processing - SIMD and floating point */
14146 disas_data_proc_simd_fp(s
, insn
);
14149 assert(FALSE
); /* all 15 cases should be handled above */
14153 /* if we allocated any temporaries, free them here */
14157 * After execution of most insns, btype is reset to 0.
14158 * Note that we set btype == -1 when the insn sets btype.
14160 if (s
->btype
> 0 && s
->base
.is_jmp
!= DISAS_NORETURN
) {
14165 static void aarch64_tr_init_disas_context(DisasContextBase
*dcbase
,
14168 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14169 CPUARMState
*env
= cpu
->env_ptr
;
14170 ARMCPU
*arm_cpu
= env_archcpu(env
);
14171 uint32_t tb_flags
= dc
->base
.tb
->flags
;
14172 int bound
, core_mmu_idx
;
14174 dc
->isar
= &arm_cpu
->isar
;
14178 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
14179 * there is no secure EL1, so we route exceptions to EL3.
14181 dc
->secure_routed_to_el3
= arm_feature(env
, ARM_FEATURE_EL3
) &&
14182 !arm_el_is_aa64(env
, 3);
14185 dc
->be_data
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, BE_DATA
) ? MO_BE
: MO_LE
;
14186 dc
->condexec_mask
= 0;
14187 dc
->condexec_cond
= 0;
14188 core_mmu_idx
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, MMUIDX
);
14189 dc
->mmu_idx
= core_to_arm_mmu_idx(env
, core_mmu_idx
);
14190 dc
->tbii
= FIELD_EX32(tb_flags
, TBFLAG_A64
, TBII
);
14191 dc
->tbid
= FIELD_EX32(tb_flags
, TBFLAG_A64
, TBID
);
14192 dc
->current_el
= arm_mmu_idx_to_el(dc
->mmu_idx
);
14193 #if !defined(CONFIG_USER_ONLY)
14194 dc
->user
= (dc
->current_el
== 0);
14196 dc
->fp_excp_el
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, FPEXC_EL
);
14197 dc
->sve_excp_el
= FIELD_EX32(tb_flags
, TBFLAG_A64
, SVEEXC_EL
);
14198 dc
->sve_len
= (FIELD_EX32(tb_flags
, TBFLAG_A64
, ZCR_LEN
) + 1) * 16;
14199 dc
->pauth_active
= FIELD_EX32(tb_flags
, TBFLAG_A64
, PAUTH_ACTIVE
);
14200 dc
->bt
= FIELD_EX32(tb_flags
, TBFLAG_A64
, BT
);
14201 dc
->btype
= FIELD_EX32(tb_flags
, TBFLAG_A64
, BTYPE
);
14202 dc
->unpriv
= FIELD_EX32(tb_flags
, TBFLAG_A64
, UNPRIV
);
14204 dc
->vec_stride
= 0;
14205 dc
->cp_regs
= arm_cpu
->cp_regs
;
14206 dc
->features
= env
->features
;
14208 /* Single step state. The code-generation logic here is:
14210 * generate code with no special handling for single-stepping (except
14211 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
14212 * this happens anyway because those changes are all system register or
14214 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
14215 * emit code for one insn
14216 * emit code to clear PSTATE.SS
14217 * emit code to generate software step exception for completed step
14218 * end TB (as usual for having generated an exception)
14219 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
14220 * emit code to generate a software step exception
14223 dc
->ss_active
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, SS_ACTIVE
);
14224 dc
->pstate_ss
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, PSTATE_SS
);
14225 dc
->is_ldex
= false;
14226 dc
->debug_target_el
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, DEBUG_TARGET_EL
);
14228 /* Bound the number of insns to execute to those left on the page. */
14229 bound
= -(dc
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
14231 /* If architectural single step active, limit to 1. */
14232 if (dc
->ss_active
) {
14235 dc
->base
.max_insns
= MIN(dc
->base
.max_insns
, bound
);
14237 init_tmp_a64_array(dc
);
14240 static void aarch64_tr_tb_start(DisasContextBase
*db
, CPUState
*cpu
)
14244 static void aarch64_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
14246 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14248 tcg_gen_insn_start(dc
->base
.pc_next
, 0, 0);
14249 dc
->insn_start
= tcg_last_op();
14252 static bool aarch64_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cpu
,
14253 const CPUBreakpoint
*bp
)
14255 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14257 if (bp
->flags
& BP_CPU
) {
14258 gen_a64_set_pc_im(dc
->base
.pc_next
);
14259 gen_helper_check_breakpoints(cpu_env
);
14260 /* End the TB early; it likely won't be executed */
14261 dc
->base
.is_jmp
= DISAS_TOO_MANY
;
14263 gen_exception_internal_insn(dc
, dc
->base
.pc_next
, EXCP_DEBUG
);
14264 /* The address covered by the breakpoint must be
14265 included in [tb->pc, tb->pc + tb->size) in order
14266 to for it to be properly cleared -- thus we
14267 increment the PC here so that the logic setting
14268 tb->size below does the right thing. */
14269 dc
->base
.pc_next
+= 4;
14270 dc
->base
.is_jmp
= DISAS_NORETURN
;
14276 static void aarch64_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
14278 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14279 CPUARMState
*env
= cpu
->env_ptr
;
14281 if (dc
->ss_active
&& !dc
->pstate_ss
) {
14282 /* Singlestep state is Active-pending.
14283 * If we're in this state at the start of a TB then either
14284 * a) we just took an exception to an EL which is being debugged
14285 * and this is the first insn in the exception handler
14286 * b) debug exceptions were masked and we just unmasked them
14287 * without changing EL (eg by clearing PSTATE.D)
14288 * In either case we're going to take a swstep exception in the
14289 * "did not step an insn" case, and so the syndrome ISV and EX
14290 * bits should be zero.
14292 assert(dc
->base
.num_insns
== 1);
14293 gen_swstep_exception(dc
, 0, 0);
14294 dc
->base
.is_jmp
= DISAS_NORETURN
;
14296 disas_a64_insn(env
, dc
);
14299 translator_loop_temp_check(&dc
->base
);
14302 static void aarch64_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
14304 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14306 if (unlikely(dc
->base
.singlestep_enabled
|| dc
->ss_active
)) {
14307 /* Note that this means single stepping WFI doesn't halt the CPU.
14308 * For conditional branch insns this is harmless unreachable code as
14309 * gen_goto_tb() has already handled emitting the debug exception
14310 * (and thus a tb-jump is not possible when singlestepping).
14312 switch (dc
->base
.is_jmp
) {
14314 gen_a64_set_pc_im(dc
->base
.pc_next
);
14318 if (dc
->base
.singlestep_enabled
) {
14319 gen_exception_internal(EXCP_DEBUG
);
14321 gen_step_complete_exception(dc
);
14324 case DISAS_NORETURN
:
14328 switch (dc
->base
.is_jmp
) {
14330 case DISAS_TOO_MANY
:
14331 gen_goto_tb(dc
, 1, dc
->base
.pc_next
);
14335 gen_a64_set_pc_im(dc
->base
.pc_next
);
14338 tcg_gen_exit_tb(NULL
, 0);
14341 tcg_gen_lookup_and_goto_ptr();
14343 case DISAS_NORETURN
:
14347 gen_a64_set_pc_im(dc
->base
.pc_next
);
14348 gen_helper_wfe(cpu_env
);
14351 gen_a64_set_pc_im(dc
->base
.pc_next
);
14352 gen_helper_yield(cpu_env
);
14356 /* This is a special case because we don't want to just halt the CPU
14357 * if trying to debug across a WFI.
14359 TCGv_i32 tmp
= tcg_const_i32(4);
14361 gen_a64_set_pc_im(dc
->base
.pc_next
);
14362 gen_helper_wfi(cpu_env
, tmp
);
14363 tcg_temp_free_i32(tmp
);
14364 /* The helper doesn't necessarily throw an exception, but we
14365 * must go back to the main loop to check for interrupts anyway.
14367 tcg_gen_exit_tb(NULL
, 0);
14374 static void aarch64_tr_disas_log(const DisasContextBase
*dcbase
,
14377 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14379 qemu_log("IN: %s\n", lookup_symbol(dc
->base
.pc_first
));
14380 log_target_disas(cpu
, dc
->base
.pc_first
, dc
->base
.tb
->size
);
14383 const TranslatorOps aarch64_translator_ops
= {
14384 .init_disas_context
= aarch64_tr_init_disas_context
,
14385 .tb_start
= aarch64_tr_tb_start
,
14386 .insn_start
= aarch64_tr_insn_start
,
14387 .breakpoint_check
= aarch64_tr_breakpoint_check
,
14388 .translate_insn
= aarch64_tr_translate_insn
,
14389 .tb_stop
= aarch64_tr_tb_stop
,
14390 .disas_log
= aarch64_tr_disas_log
,