2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Andrzej Zaborowski
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #if defined(__ARM_ARCH_7__) || \
26 defined(__ARM_ARCH_7A__) || \
27 defined(__ARM_ARCH_7EM__) || \
28 defined(__ARM_ARCH_7M__) || \
29 defined(__ARM_ARCH_7R__)
30 #define USE_ARMV7_INSTRUCTIONS
33 #if defined(USE_ARMV7_INSTRUCTIONS) || \
34 defined(__ARM_ARCH_6J__) || \
35 defined(__ARM_ARCH_6K__) || \
36 defined(__ARM_ARCH_6T2__) || \
37 defined(__ARM_ARCH_6Z__) || \
38 defined(__ARM_ARCH_6ZK__)
39 #define USE_ARMV6_INSTRUCTIONS
42 #if defined(USE_ARMV6_INSTRUCTIONS) || \
43 defined(__ARM_ARCH_5T__) || \
44 defined(__ARM_ARCH_5TE__) || \
45 defined(__ARM_ARCH_5TEJ__)
46 #define USE_ARMV5_INSTRUCTIONS
49 #ifdef USE_ARMV5_INSTRUCTIONS
50 static const int use_armv5_instructions
= 1;
52 static const int use_armv5_instructions
= 0;
54 #undef USE_ARMV5_INSTRUCTIONS
56 #ifdef USE_ARMV6_INSTRUCTIONS
57 static const int use_armv6_instructions
= 1;
59 static const int use_armv6_instructions
= 0;
61 #undef USE_ARMV6_INSTRUCTIONS
63 #ifdef USE_ARMV7_INSTRUCTIONS
64 static const int use_armv7_instructions
= 1;
66 static const int use_armv7_instructions
= 0;
68 #undef USE_ARMV7_INSTRUCTIONS
71 static const char * const tcg_target_reg_names
[TCG_TARGET_NB_REGS
] = {
91 static const int tcg_target_reg_alloc_order
[] = {
109 static const int tcg_target_call_iarg_regs
[4] = {
110 TCG_REG_R0
, TCG_REG_R1
, TCG_REG_R2
, TCG_REG_R3
112 static const int tcg_target_call_oarg_regs
[2] = {
113 TCG_REG_R0
, TCG_REG_R1
116 static void patch_reloc(uint8_t *code_ptr
, int type
,
117 tcg_target_long value
, tcg_target_long addend
)
121 *(uint32_t *) code_ptr
= value
;
130 *(uint32_t *) code_ptr
= ((*(uint32_t *) code_ptr
) & 0xff000000) |
131 (((value
- ((tcg_target_long
) code_ptr
+ 8)) >> 2) & 0xffffff);
136 /* maximum number of register used for input function arguments */
137 static inline int tcg_target_get_call_iarg_regs_count(int flags
)
142 /* parse target specific constraints */
143 static int target_parse_constraint(TCGArgConstraint
*ct
, const char **pct_str
)
150 ct
->ct
|= TCG_CT_CONST_ARM
;
154 #ifndef CONFIG_SOFTMMU
160 ct
->ct
|= TCG_CT_REG
;
161 tcg_regset_set32(ct
->u
.regs
, 0, (1 << TCG_TARGET_NB_REGS
) - 1);
164 #ifdef CONFIG_SOFTMMU
165 /* qemu_ld/st inputs (unless 'X', 'd' or 'D') */
167 ct
->ct
|= TCG_CT_REG
;
168 tcg_regset_set32(ct
->u
.regs
, 0, (1 << TCG_TARGET_NB_REGS
) - 1);
169 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R0
);
170 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R1
);
173 /* qemu_ld64 data_reg */
175 ct
->ct
|= TCG_CT_REG
;
176 tcg_regset_set32(ct
->u
.regs
, 0, (1 << TCG_TARGET_NB_REGS
) - 1);
177 /* r1 is still needed to load data_reg2, so don't use it. */
178 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R1
);
181 /* qemu_ld/st64 data_reg2 */
183 ct
->ct
|= TCG_CT_REG
;
184 tcg_regset_set32(ct
->u
.regs
, 0, (1 << TCG_TARGET_NB_REGS
) - 1);
185 /* r0, r1 and optionally r2 will be overwritten by the address
186 * and the low word of data, so don't use these. */
187 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R0
);
188 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R1
);
189 # if TARGET_LONG_BITS == 64
190 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R2
);
194 # if TARGET_LONG_BITS == 64
195 /* qemu_ld/st addr_reg2 */
197 ct
->ct
|= TCG_CT_REG
;
198 tcg_regset_set32(ct
->u
.regs
, 0, (1 << TCG_TARGET_NB_REGS
) - 1);
199 /* r0 will be overwritten by the low word of base, so don't use it. */
200 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R0
);
201 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R1
);
215 static inline uint32_t rotl(uint32_t val
, int n
)
217 return (val
<< n
) | (val
>> (32 - n
));
220 /* ARM immediates for ALU instructions are made of an unsigned 8-bit
221 right-rotated by an even amount between 0 and 30. */
222 static inline int encode_imm(uint32_t imm
)
226 /* simple case, only lower bits */
227 if ((imm
& ~0xff) == 0)
229 /* then try a simple even shift */
230 shift
= ctz32(imm
) & ~1;
231 if (((imm
>> shift
) & ~0xff) == 0)
233 /* now try harder with rotations */
234 if ((rotl(imm
, 2) & ~0xff) == 0)
236 if ((rotl(imm
, 4) & ~0xff) == 0)
238 if ((rotl(imm
, 6) & ~0xff) == 0)
240 /* imm can't be encoded */
244 static inline int check_fit_imm(uint32_t imm
)
246 return encode_imm(imm
) >= 0;
249 /* Test if a constant matches the constraint.
250 * TODO: define constraints for:
252 * ldr/str offset: between -0xfff and 0xfff
253 * ldrh/strh offset: between -0xff and 0xff
254 * mov operand2: values represented with x << (2 * y), x < 0x100
255 * add, sub, eor...: ditto
257 static inline int tcg_target_const_match(tcg_target_long val
,
258 const TCGArgConstraint
*arg_ct
)
262 if (ct
& TCG_CT_CONST
)
264 else if ((ct
& TCG_CT_CONST_ARM
) && check_fit_imm(val
))
270 enum arm_data_opc_e
{
288 #define TO_CPSR(opc) \
289 ((opc == ARITH_CMP || opc == ARITH_CMN || opc == ARITH_TST) << 20)
291 #define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00)
292 #define SHIFT_IMM_LSR(im) (((im) << 7) | 0x20)
293 #define SHIFT_IMM_ASR(im) (((im) << 7) | 0x40)
294 #define SHIFT_IMM_ROR(im) (((im) << 7) | 0x60)
295 #define SHIFT_REG_LSL(rs) (((rs) << 8) | 0x10)
296 #define SHIFT_REG_LSR(rs) (((rs) << 8) | 0x30)
297 #define SHIFT_REG_ASR(rs) (((rs) << 8) | 0x50)
298 #define SHIFT_REG_ROR(rs) (((rs) << 8) | 0x70)
300 enum arm_cond_code_e
{
303 COND_CS
= 0x2, /* Unsigned greater or equal */
304 COND_CC
= 0x3, /* Unsigned less than */
305 COND_MI
= 0x4, /* Negative */
306 COND_PL
= 0x5, /* Zero or greater */
307 COND_VS
= 0x6, /* Overflow */
308 COND_VC
= 0x7, /* No overflow */
309 COND_HI
= 0x8, /* Unsigned greater than */
310 COND_LS
= 0x9, /* Unsigned less or equal */
318 static const uint8_t tcg_cond_to_arm_cond
[10] = {
319 [TCG_COND_EQ
] = COND_EQ
,
320 [TCG_COND_NE
] = COND_NE
,
321 [TCG_COND_LT
] = COND_LT
,
322 [TCG_COND_GE
] = COND_GE
,
323 [TCG_COND_LE
] = COND_LE
,
324 [TCG_COND_GT
] = COND_GT
,
326 [TCG_COND_LTU
] = COND_CC
,
327 [TCG_COND_GEU
] = COND_CS
,
328 [TCG_COND_LEU
] = COND_LS
,
329 [TCG_COND_GTU
] = COND_HI
,
332 static inline void tcg_out_bx(TCGContext
*s
, int cond
, int rn
)
334 tcg_out32(s
, (cond
<< 28) | 0x012fff10 | rn
);
337 static inline void tcg_out_b(TCGContext
*s
, int cond
, int32_t offset
)
339 tcg_out32(s
, (cond
<< 28) | 0x0a000000 |
340 (((offset
- 8) >> 2) & 0x00ffffff));
343 static inline void tcg_out_b_noaddr(TCGContext
*s
, int cond
)
345 #ifdef HOST_WORDS_BIGENDIAN
346 tcg_out8(s
, (cond
<< 4) | 0x0a);
350 tcg_out8(s
, (cond
<< 4) | 0x0a);
354 static inline void tcg_out_bl(TCGContext
*s
, int cond
, int32_t offset
)
356 tcg_out32(s
, (cond
<< 28) | 0x0b000000 |
357 (((offset
- 8) >> 2) & 0x00ffffff));
360 static inline void tcg_out_blx(TCGContext
*s
, int cond
, int rn
)
362 tcg_out32(s
, (cond
<< 28) | 0x012fff30 | rn
);
365 static inline void tcg_out_dat_reg(TCGContext
*s
,
366 int cond
, int opc
, int rd
, int rn
, int rm
, int shift
)
368 tcg_out32(s
, (cond
<< 28) | (0 << 25) | (opc
<< 21) | TO_CPSR(opc
) |
369 (rn
<< 16) | (rd
<< 12) | shift
| rm
);
372 static inline void tcg_out_dat_reg2(TCGContext
*s
,
373 int cond
, int opc0
, int opc1
, int rd0
, int rd1
,
374 int rn0
, int rn1
, int rm0
, int rm1
, int shift
)
376 if (rd0
== rn1
|| rd0
== rm1
) {
377 tcg_out32(s
, (cond
<< 28) | (0 << 25) | (opc0
<< 21) | (1 << 20) |
378 (rn0
<< 16) | (8 << 12) | shift
| rm0
);
379 tcg_out32(s
, (cond
<< 28) | (0 << 25) | (opc1
<< 21) |
380 (rn1
<< 16) | (rd1
<< 12) | shift
| rm1
);
381 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
382 rd0
, 0, TCG_REG_R8
, SHIFT_IMM_LSL(0));
384 tcg_out32(s
, (cond
<< 28) | (0 << 25) | (opc0
<< 21) | (1 << 20) |
385 (rn0
<< 16) | (rd0
<< 12) | shift
| rm0
);
386 tcg_out32(s
, (cond
<< 28) | (0 << 25) | (opc1
<< 21) |
387 (rn1
<< 16) | (rd1
<< 12) | shift
| rm1
);
391 static inline void tcg_out_dat_imm(TCGContext
*s
,
392 int cond
, int opc
, int rd
, int rn
, int im
)
394 tcg_out32(s
, (cond
<< 28) | (1 << 25) | (opc
<< 21) | TO_CPSR(opc
) |
395 (rn
<< 16) | (rd
<< 12) | im
);
398 static inline void tcg_out_movi32(TCGContext
*s
,
399 int cond
, int rd
, int32_t arg
)
401 int offset
= (uint32_t) arg
- ((uint32_t) s
->code_ptr
+ 8);
403 /* TODO: This is very suboptimal, we can easily have a constant
404 * pool somewhere after all the instructions. */
406 if (arg
< 0 && arg
> -0x100)
407 return tcg_out_dat_imm(s
, cond
, ARITH_MVN
, rd
, 0, (~arg
) & 0xff);
409 if (offset
< 0x100 && offset
> -0x100)
411 tcg_out_dat_imm(s
, cond
, ARITH_ADD
, rd
, 15, offset
) :
412 tcg_out_dat_imm(s
, cond
, ARITH_SUB
, rd
, 15, -offset
);
414 if (use_armv7_instructions
) {
417 tcg_out32(s
, (cond
<< 28) | 0x03000000 | (rd
<< 12)
418 | ((arg
<< 4) & 0x000f0000) | (arg
& 0xfff));
419 if (arg
& 0xffff0000)
421 tcg_out32(s
, (cond
<< 28) | 0x03400000 | (rd
<< 12)
422 | ((arg
>> 12) & 0x000f0000) | ((arg
>> 16) & 0xfff));
424 tcg_out_dat_imm(s
, cond
, ARITH_MOV
, rd
, 0, arg
& 0xff);
425 if (arg
& 0x0000ff00)
426 tcg_out_dat_imm(s
, cond
, ARITH_ORR
, rd
, rd
,
427 ((arg
>> 8) & 0xff) | 0xc00);
428 if (arg
& 0x00ff0000)
429 tcg_out_dat_imm(s
, cond
, ARITH_ORR
, rd
, rd
,
430 ((arg
>> 16) & 0xff) | 0x800);
431 if (arg
& 0xff000000)
432 tcg_out_dat_imm(s
, cond
, ARITH_ORR
, rd
, rd
,
433 ((arg
>> 24) & 0xff) | 0x400);
437 static inline void tcg_out_mul32(TCGContext
*s
,
438 int cond
, int rd
, int rs
, int rm
)
441 tcg_out32(s
, (cond
<< 28) | (rd
<< 16) | (0 << 12) |
442 (rs
<< 8) | 0x90 | rm
);
444 tcg_out32(s
, (cond
<< 28) | (rd
<< 16) | (0 << 12) |
445 (rm
<< 8) | 0x90 | rs
);
447 tcg_out32(s
, (cond
<< 28) | ( 8 << 16) | (0 << 12) |
448 (rs
<< 8) | 0x90 | rm
);
449 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
450 rd
, 0, TCG_REG_R8
, SHIFT_IMM_LSL(0));
454 static inline void tcg_out_umull32(TCGContext
*s
,
455 int cond
, int rd0
, int rd1
, int rs
, int rm
)
457 if (rd0
!= rm
&& rd1
!= rm
)
458 tcg_out32(s
, (cond
<< 28) | 0x800090 |
459 (rd1
<< 16) | (rd0
<< 12) | (rs
<< 8) | rm
);
460 else if (rd0
!= rs
&& rd1
!= rs
)
461 tcg_out32(s
, (cond
<< 28) | 0x800090 |
462 (rd1
<< 16) | (rd0
<< 12) | (rm
<< 8) | rs
);
464 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
465 TCG_REG_R8
, 0, rm
, SHIFT_IMM_LSL(0));
466 tcg_out32(s
, (cond
<< 28) | 0x800098 |
467 (rd1
<< 16) | (rd0
<< 12) | (rs
<< 8));
471 static inline void tcg_out_smull32(TCGContext
*s
,
472 int cond
, int rd0
, int rd1
, int rs
, int rm
)
474 if (rd0
!= rm
&& rd1
!= rm
)
475 tcg_out32(s
, (cond
<< 28) | 0xc00090 |
476 (rd1
<< 16) | (rd0
<< 12) | (rs
<< 8) | rm
);
477 else if (rd0
!= rs
&& rd1
!= rs
)
478 tcg_out32(s
, (cond
<< 28) | 0xc00090 |
479 (rd1
<< 16) | (rd0
<< 12) | (rm
<< 8) | rs
);
481 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
482 TCG_REG_R8
, 0, rm
, SHIFT_IMM_LSL(0));
483 tcg_out32(s
, (cond
<< 28) | 0xc00098 |
484 (rd1
<< 16) | (rd0
<< 12) | (rs
<< 8));
488 static inline void tcg_out_ext8s(TCGContext
*s
, int cond
,
491 if (use_armv6_instructions
) {
493 tcg_out32(s
, 0x06af0070 | (cond
<< 28) | (rd
<< 12) | rn
);
495 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
496 rd
, 0, rn
, SHIFT_IMM_LSL(24));
497 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
498 rd
, 0, rd
, SHIFT_IMM_ASR(24));
502 static inline void tcg_out_ext8u(TCGContext
*s
, int cond
,
505 tcg_out_dat_imm(s
, cond
, ARITH_AND
, rd
, rn
, 0xff);
508 static inline void tcg_out_ext16s(TCGContext
*s
, int cond
,
511 if (use_armv6_instructions
) {
513 tcg_out32(s
, 0x06bf0070 | (cond
<< 28) | (rd
<< 12) | rn
);
515 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
516 rd
, 0, rn
, SHIFT_IMM_LSL(16));
517 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
518 rd
, 0, rd
, SHIFT_IMM_ASR(16));
522 static inline void tcg_out_ext16u(TCGContext
*s
, int cond
,
525 if (use_armv6_instructions
) {
527 tcg_out32(s
, 0x06ff0070 | (cond
<< 28) | (rd
<< 12) | rn
);
529 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
530 rd
, 0, rn
, SHIFT_IMM_LSL(16));
531 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
532 rd
, 0, rd
, SHIFT_IMM_LSR(16));
536 static inline void tcg_out_bswap16(TCGContext
*s
, int cond
, int rd
, int rn
)
538 if (use_armv6_instructions
) {
540 tcg_out32(s
, 0x06bf0fb0 | (cond
<< 28) | (rd
<< 12) | rn
);
542 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
543 TCG_REG_R8
, 0, rn
, SHIFT_IMM_LSL(24));
544 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
545 TCG_REG_R8
, 0, TCG_REG_R8
, SHIFT_IMM_LSR(16));
546 tcg_out_dat_reg(s
, cond
, ARITH_ORR
,
547 rd
, TCG_REG_R8
, rn
, SHIFT_IMM_LSR(8));
551 static inline void tcg_out_bswap32(TCGContext
*s
, int cond
, int rd
, int rn
)
553 if (use_armv6_instructions
) {
555 tcg_out32(s
, 0x06bf0f30 | (cond
<< 28) | (rd
<< 12) | rn
);
557 tcg_out_dat_reg(s
, cond
, ARITH_EOR
,
558 TCG_REG_R8
, rn
, rn
, SHIFT_IMM_ROR(16));
559 tcg_out_dat_imm(s
, cond
, ARITH_BIC
,
560 TCG_REG_R8
, TCG_REG_R8
, 0xff | 0x800);
561 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
562 rd
, 0, rn
, SHIFT_IMM_ROR(8));
563 tcg_out_dat_reg(s
, cond
, ARITH_EOR
,
564 rd
, rd
, TCG_REG_R8
, SHIFT_IMM_LSR(8));
568 static inline void tcg_out_ld32_12(TCGContext
*s
, int cond
,
569 int rd
, int rn
, tcg_target_long im
)
572 tcg_out32(s
, (cond
<< 28) | 0x05900000 |
573 (rn
<< 16) | (rd
<< 12) | (im
& 0xfff));
575 tcg_out32(s
, (cond
<< 28) | 0x05100000 |
576 (rn
<< 16) | (rd
<< 12) | ((-im
) & 0xfff));
579 static inline void tcg_out_st32_12(TCGContext
*s
, int cond
,
580 int rd
, int rn
, tcg_target_long im
)
583 tcg_out32(s
, (cond
<< 28) | 0x05800000 |
584 (rn
<< 16) | (rd
<< 12) | (im
& 0xfff));
586 tcg_out32(s
, (cond
<< 28) | 0x05000000 |
587 (rn
<< 16) | (rd
<< 12) | ((-im
) & 0xfff));
590 static inline void tcg_out_ld32_r(TCGContext
*s
, int cond
,
591 int rd
, int rn
, int rm
)
593 tcg_out32(s
, (cond
<< 28) | 0x07900000 |
594 (rn
<< 16) | (rd
<< 12) | rm
);
597 static inline void tcg_out_st32_r(TCGContext
*s
, int cond
,
598 int rd
, int rn
, int rm
)
600 tcg_out32(s
, (cond
<< 28) | 0x07800000 |
601 (rn
<< 16) | (rd
<< 12) | rm
);
604 /* Register pre-increment with base writeback. */
605 static inline void tcg_out_ld32_rwb(TCGContext
*s
, int cond
,
606 int rd
, int rn
, int rm
)
608 tcg_out32(s
, (cond
<< 28) | 0x07b00000 |
609 (rn
<< 16) | (rd
<< 12) | rm
);
612 static inline void tcg_out_st32_rwb(TCGContext
*s
, int cond
,
613 int rd
, int rn
, int rm
)
615 tcg_out32(s
, (cond
<< 28) | 0x07a00000 |
616 (rn
<< 16) | (rd
<< 12) | rm
);
619 static inline void tcg_out_ld16u_8(TCGContext
*s
, int cond
,
620 int rd
, int rn
, tcg_target_long im
)
623 tcg_out32(s
, (cond
<< 28) | 0x01d000b0 |
624 (rn
<< 16) | (rd
<< 12) |
625 ((im
& 0xf0) << 4) | (im
& 0xf));
627 tcg_out32(s
, (cond
<< 28) | 0x015000b0 |
628 (rn
<< 16) | (rd
<< 12) |
629 (((-im
) & 0xf0) << 4) | ((-im
) & 0xf));
632 static inline void tcg_out_st16_8(TCGContext
*s
, int cond
,
633 int rd
, int rn
, tcg_target_long im
)
636 tcg_out32(s
, (cond
<< 28) | 0x01c000b0 |
637 (rn
<< 16) | (rd
<< 12) |
638 ((im
& 0xf0) << 4) | (im
& 0xf));
640 tcg_out32(s
, (cond
<< 28) | 0x014000b0 |
641 (rn
<< 16) | (rd
<< 12) |
642 (((-im
) & 0xf0) << 4) | ((-im
) & 0xf));
645 static inline void tcg_out_ld16u_r(TCGContext
*s
, int cond
,
646 int rd
, int rn
, int rm
)
648 tcg_out32(s
, (cond
<< 28) | 0x019000b0 |
649 (rn
<< 16) | (rd
<< 12) | rm
);
652 static inline void tcg_out_st16_r(TCGContext
*s
, int cond
,
653 int rd
, int rn
, int rm
)
655 tcg_out32(s
, (cond
<< 28) | 0x018000b0 |
656 (rn
<< 16) | (rd
<< 12) | rm
);
659 static inline void tcg_out_ld16s_8(TCGContext
*s
, int cond
,
660 int rd
, int rn
, tcg_target_long im
)
663 tcg_out32(s
, (cond
<< 28) | 0x01d000f0 |
664 (rn
<< 16) | (rd
<< 12) |
665 ((im
& 0xf0) << 4) | (im
& 0xf));
667 tcg_out32(s
, (cond
<< 28) | 0x015000f0 |
668 (rn
<< 16) | (rd
<< 12) |
669 (((-im
) & 0xf0) << 4) | ((-im
) & 0xf));
672 static inline void tcg_out_ld16s_r(TCGContext
*s
, int cond
,
673 int rd
, int rn
, int rm
)
675 tcg_out32(s
, (cond
<< 28) | 0x019000f0 |
676 (rn
<< 16) | (rd
<< 12) | rm
);
679 static inline void tcg_out_ld8_12(TCGContext
*s
, int cond
,
680 int rd
, int rn
, tcg_target_long im
)
683 tcg_out32(s
, (cond
<< 28) | 0x05d00000 |
684 (rn
<< 16) | (rd
<< 12) | (im
& 0xfff));
686 tcg_out32(s
, (cond
<< 28) | 0x05500000 |
687 (rn
<< 16) | (rd
<< 12) | ((-im
) & 0xfff));
690 static inline void tcg_out_st8_12(TCGContext
*s
, int cond
,
691 int rd
, int rn
, tcg_target_long im
)
694 tcg_out32(s
, (cond
<< 28) | 0x05c00000 |
695 (rn
<< 16) | (rd
<< 12) | (im
& 0xfff));
697 tcg_out32(s
, (cond
<< 28) | 0x05400000 |
698 (rn
<< 16) | (rd
<< 12) | ((-im
) & 0xfff));
701 static inline void tcg_out_ld8_r(TCGContext
*s
, int cond
,
702 int rd
, int rn
, int rm
)
704 tcg_out32(s
, (cond
<< 28) | 0x07d00000 |
705 (rn
<< 16) | (rd
<< 12) | rm
);
708 static inline void tcg_out_st8_r(TCGContext
*s
, int cond
,
709 int rd
, int rn
, int rm
)
711 tcg_out32(s
, (cond
<< 28) | 0x07c00000 |
712 (rn
<< 16) | (rd
<< 12) | rm
);
715 static inline void tcg_out_ld8s_8(TCGContext
*s
, int cond
,
716 int rd
, int rn
, tcg_target_long im
)
719 tcg_out32(s
, (cond
<< 28) | 0x01d000d0 |
720 (rn
<< 16) | (rd
<< 12) |
721 ((im
& 0xf0) << 4) | (im
& 0xf));
723 tcg_out32(s
, (cond
<< 28) | 0x015000d0 |
724 (rn
<< 16) | (rd
<< 12) |
725 (((-im
) & 0xf0) << 4) | ((-im
) & 0xf));
728 static inline void tcg_out_ld8s_r(TCGContext
*s
, int cond
,
729 int rd
, int rn
, int rm
)
731 tcg_out32(s
, (cond
<< 28) | 0x019000d0 |
732 (rn
<< 16) | (rd
<< 12) | rm
);
735 static inline void tcg_out_ld32u(TCGContext
*s
, int cond
,
736 int rd
, int rn
, int32_t offset
)
738 if (offset
> 0xfff || offset
< -0xfff) {
739 tcg_out_movi32(s
, cond
, TCG_REG_R8
, offset
);
740 tcg_out_ld32_r(s
, cond
, rd
, rn
, TCG_REG_R8
);
742 tcg_out_ld32_12(s
, cond
, rd
, rn
, offset
);
745 static inline void tcg_out_st32(TCGContext
*s
, int cond
,
746 int rd
, int rn
, int32_t offset
)
748 if (offset
> 0xfff || offset
< -0xfff) {
749 tcg_out_movi32(s
, cond
, TCG_REG_R8
, offset
);
750 tcg_out_st32_r(s
, cond
, rd
, rn
, TCG_REG_R8
);
752 tcg_out_st32_12(s
, cond
, rd
, rn
, offset
);
755 static inline void tcg_out_ld16u(TCGContext
*s
, int cond
,
756 int rd
, int rn
, int32_t offset
)
758 if (offset
> 0xff || offset
< -0xff) {
759 tcg_out_movi32(s
, cond
, TCG_REG_R8
, offset
);
760 tcg_out_ld16u_r(s
, cond
, rd
, rn
, TCG_REG_R8
);
762 tcg_out_ld16u_8(s
, cond
, rd
, rn
, offset
);
765 static inline void tcg_out_ld16s(TCGContext
*s
, int cond
,
766 int rd
, int rn
, int32_t offset
)
768 if (offset
> 0xff || offset
< -0xff) {
769 tcg_out_movi32(s
, cond
, TCG_REG_R8
, offset
);
770 tcg_out_ld16s_r(s
, cond
, rd
, rn
, TCG_REG_R8
);
772 tcg_out_ld16s_8(s
, cond
, rd
, rn
, offset
);
775 static inline void tcg_out_st16(TCGContext
*s
, int cond
,
776 int rd
, int rn
, int32_t offset
)
778 if (offset
> 0xff || offset
< -0xff) {
779 tcg_out_movi32(s
, cond
, TCG_REG_R8
, offset
);
780 tcg_out_st16_r(s
, cond
, rd
, rn
, TCG_REG_R8
);
782 tcg_out_st16_8(s
, cond
, rd
, rn
, offset
);
785 static inline void tcg_out_ld8u(TCGContext
*s
, int cond
,
786 int rd
, int rn
, int32_t offset
)
788 if (offset
> 0xfff || offset
< -0xfff) {
789 tcg_out_movi32(s
, cond
, TCG_REG_R8
, offset
);
790 tcg_out_ld8_r(s
, cond
, rd
, rn
, TCG_REG_R8
);
792 tcg_out_ld8_12(s
, cond
, rd
, rn
, offset
);
795 static inline void tcg_out_ld8s(TCGContext
*s
, int cond
,
796 int rd
, int rn
, int32_t offset
)
798 if (offset
> 0xff || offset
< -0xff) {
799 tcg_out_movi32(s
, cond
, TCG_REG_R8
, offset
);
800 tcg_out_ld8s_r(s
, cond
, rd
, rn
, TCG_REG_R8
);
802 tcg_out_ld8s_8(s
, cond
, rd
, rn
, offset
);
805 static inline void tcg_out_st8(TCGContext
*s
, int cond
,
806 int rd
, int rn
, int32_t offset
)
808 if (offset
> 0xfff || offset
< -0xfff) {
809 tcg_out_movi32(s
, cond
, TCG_REG_R8
, offset
);
810 tcg_out_st8_r(s
, cond
, rd
, rn
, TCG_REG_R8
);
812 tcg_out_st8_12(s
, cond
, rd
, rn
, offset
);
815 static inline void tcg_out_goto(TCGContext
*s
, int cond
, uint32_t addr
)
819 val
= addr
- (tcg_target_long
) s
->code_ptr
;
820 if (val
- 8 < 0x01fffffd && val
- 8 > -0x01fffffd)
821 tcg_out_b(s
, cond
, val
);
826 if (cond
== COND_AL
) {
827 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_PC
, TCG_REG_PC
, -4);
828 tcg_out32(s
, addr
); /* XXX: This is l->u.value, can we use it? */
830 tcg_out_movi32(s
, cond
, TCG_REG_R8
, val
- 8);
831 tcg_out_dat_reg(s
, cond
, ARITH_ADD
,
832 TCG_REG_PC
, TCG_REG_PC
,
833 TCG_REG_R8
, SHIFT_IMM_LSL(0));
839 static inline void tcg_out_call(TCGContext
*s
, int cond
, uint32_t addr
)
843 val
= addr
- (tcg_target_long
) s
->code_ptr
;
844 if (val
< 0x01fffffd && val
> -0x01fffffd)
845 tcg_out_bl(s
, cond
, val
);
850 if (cond
== COND_AL
) {
851 tcg_out_dat_imm(s
, cond
, ARITH_ADD
, TCG_REG_R14
, TCG_REG_PC
, 4);
852 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_PC
, TCG_REG_PC
, -4);
853 tcg_out32(s
, addr
); /* XXX: This is l->u.value, can we use it? */
855 tcg_out_movi32(s
, cond
, TCG_REG_R9
, addr
);
856 tcg_out_dat_reg(s
, cond
, ARITH_MOV
, TCG_REG_R14
, 0,
857 TCG_REG_PC
, SHIFT_IMM_LSL(0));
858 tcg_out_bx(s
, cond
, TCG_REG_R9
);
864 static inline void tcg_out_callr(TCGContext
*s
, int cond
, int arg
)
866 if (use_armv5_instructions
) {
867 tcg_out_blx(s
, cond
, arg
);
869 tcg_out_dat_reg(s
, cond
, ARITH_MOV
, TCG_REG_R14
, 0,
870 TCG_REG_PC
, SHIFT_IMM_LSL(0));
871 tcg_out_bx(s
, cond
, arg
);
875 static inline void tcg_out_goto_label(TCGContext
*s
, int cond
, int label_index
)
877 TCGLabel
*l
= &s
->labels
[label_index
];
880 tcg_out_goto(s
, cond
, l
->u
.value
);
881 else if (cond
== COND_AL
) {
882 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_PC
, TCG_REG_PC
, -4);
883 tcg_out_reloc(s
, s
->code_ptr
, R_ARM_ABS32
, label_index
, 31337);
886 /* Probably this should be preferred even for COND_AL... */
887 tcg_out_reloc(s
, s
->code_ptr
, R_ARM_PC24
, label_index
, 31337);
888 tcg_out_b_noaddr(s
, cond
);
892 #ifdef CONFIG_SOFTMMU
894 #include "../../softmmu_defs.h"
896 static void *qemu_ld_helpers
[4] = {
903 static void *qemu_st_helpers
[4] = {
911 #define TLB_SHIFT (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS)
913 static inline void tcg_out_qemu_ld(TCGContext
*s
, const TCGArg
*args
, int opc
)
915 int addr_reg
, data_reg
, data_reg2
;
916 #ifdef CONFIG_SOFTMMU
917 int mem_index
, s_bits
;
918 # if TARGET_LONG_BITS == 64
928 data_reg2
= 0; /* suppress warning */
930 #ifdef CONFIG_SOFTMMU
931 # if TARGET_LONG_BITS == 64
937 /* Should generate something like the following:
938 * shr r8, addr_reg, #TARGET_PAGE_BITS
939 * and r0, r8, #(CPU_TLB_SIZE - 1) @ Assumption: CPU_TLB_BITS <= 8
940 * add r0, env, r0 lsl #CPU_TLB_ENTRY_BITS
942 # if CPU_TLB_BITS > 8
945 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
, TCG_REG_R8
,
946 0, addr_reg
, SHIFT_IMM_LSR(TARGET_PAGE_BITS
));
947 tcg_out_dat_imm(s
, COND_AL
, ARITH_AND
,
948 TCG_REG_R0
, TCG_REG_R8
, CPU_TLB_SIZE
- 1);
949 tcg_out_dat_reg(s
, COND_AL
, ARITH_ADD
, TCG_REG_R0
, TCG_AREG0
,
950 TCG_REG_R0
, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS
));
952 * ldr r1 [r0, #(offsetof(CPUState, tlb_table[mem_index][0].addr_read))]
953 * below, the offset is likely to exceed 12 bits if mem_index != 0 and
954 * not exceed otherwise, so use an
955 * add r0, r0, #(mem_index * sizeof *CPUState.tlb_table)
959 tcg_out_dat_imm(s
, COND_AL
, ARITH_ADD
, TCG_REG_R0
, TCG_REG_R0
,
960 (mem_index
<< (TLB_SHIFT
& 1)) |
961 ((16 - (TLB_SHIFT
>> 1)) << 8));
962 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_R1
, TCG_REG_R0
,
963 offsetof(CPUState
, tlb_table
[0][0].addr_read
));
964 tcg_out_dat_reg(s
, COND_AL
, ARITH_CMP
, 0, TCG_REG_R1
,
965 TCG_REG_R8
, SHIFT_IMM_LSL(TARGET_PAGE_BITS
));
966 /* Check alignment. */
968 tcg_out_dat_imm(s
, COND_EQ
, ARITH_TST
,
969 0, addr_reg
, (1 << s_bits
) - 1);
970 # if TARGET_LONG_BITS == 64
971 /* XXX: possibly we could use a block data load or writeback in
972 * the first access. */
973 tcg_out_ld32_12(s
, COND_EQ
, TCG_REG_R1
, TCG_REG_R0
,
974 offsetof(CPUState
, tlb_table
[0][0].addr_read
) + 4);
975 tcg_out_dat_reg(s
, COND_EQ
, ARITH_CMP
, 0,
976 TCG_REG_R1
, addr_reg2
, SHIFT_IMM_LSL(0));
978 tcg_out_ld32_12(s
, COND_EQ
, TCG_REG_R1
, TCG_REG_R0
,
979 offsetof(CPUState
, tlb_table
[0][0].addend
));
983 tcg_out_ld8_r(s
, COND_EQ
, data_reg
, addr_reg
, TCG_REG_R1
);
986 tcg_out_ld8s_r(s
, COND_EQ
, data_reg
, addr_reg
, TCG_REG_R1
);
989 tcg_out_ld16u_r(s
, COND_EQ
, data_reg
, addr_reg
, TCG_REG_R1
);
992 tcg_out_ld16s_r(s
, COND_EQ
, data_reg
, addr_reg
, TCG_REG_R1
);
996 tcg_out_ld32_r(s
, COND_EQ
, data_reg
, addr_reg
, TCG_REG_R1
);
999 tcg_out_ld32_rwb(s
, COND_EQ
, data_reg
, TCG_REG_R1
, addr_reg
);
1000 tcg_out_ld32_12(s
, COND_EQ
, data_reg2
, TCG_REG_R1
, 4);
1004 label_ptr
= (void *) s
->code_ptr
;
1005 tcg_out_b(s
, COND_EQ
, 8);
1007 /* TODO: move this code to where the constants pool will be */
1008 if (addr_reg
!= TCG_REG_R0
) {
1009 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1010 TCG_REG_R0
, 0, addr_reg
, SHIFT_IMM_LSL(0));
1012 # if TARGET_LONG_BITS == 32
1013 tcg_out_dat_imm(s
, COND_AL
, ARITH_MOV
, TCG_REG_R1
, 0, mem_index
);
1015 if (addr_reg2
!= TCG_REG_R1
) {
1016 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1017 TCG_REG_R1
, 0, addr_reg2
, SHIFT_IMM_LSL(0));
1019 tcg_out_dat_imm(s
, COND_AL
, ARITH_MOV
, TCG_REG_R2
, 0, mem_index
);
1021 tcg_out_bl(s
, COND_AL
, (tcg_target_long
) qemu_ld_helpers
[s_bits
] -
1022 (tcg_target_long
) s
->code_ptr
);
1026 tcg_out_ext8s(s
, COND_AL
, data_reg
, TCG_REG_R0
);
1029 tcg_out_ext16s(s
, COND_AL
, data_reg
, TCG_REG_R0
);
1035 if (data_reg
!= TCG_REG_R0
) {
1036 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1037 data_reg
, 0, TCG_REG_R0
, SHIFT_IMM_LSL(0));
1041 if (data_reg
!= TCG_REG_R0
) {
1042 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1043 data_reg
, 0, TCG_REG_R0
, SHIFT_IMM_LSL(0));
1045 if (data_reg2
!= TCG_REG_R1
) {
1046 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1047 data_reg2
, 0, TCG_REG_R1
, SHIFT_IMM_LSL(0));
1052 *label_ptr
+= ((void *) s
->code_ptr
- (void *) label_ptr
- 8) >> 2;
1053 #else /* !CONFIG_SOFTMMU */
1055 uint32_t offset
= GUEST_BASE
;
1060 i
= ctz32(offset
) & ~1;
1061 rot
= ((32 - i
) << 7) & 0xf00;
1063 tcg_out_dat_imm(s
, COND_AL
, ARITH_ADD
, TCG_REG_R8
, addr_reg
,
1064 ((offset
>> i
) & 0xff) | rot
);
1065 addr_reg
= TCG_REG_R8
;
1066 offset
&= ~(0xff << i
);
1071 tcg_out_ld8_12(s
, COND_AL
, data_reg
, addr_reg
, 0);
1074 tcg_out_ld8s_8(s
, COND_AL
, data_reg
, addr_reg
, 0);
1077 tcg_out_ld16u_8(s
, COND_AL
, data_reg
, addr_reg
, 0);
1080 tcg_out_ld16s_8(s
, COND_AL
, data_reg
, addr_reg
, 0);
1084 tcg_out_ld32_12(s
, COND_AL
, data_reg
, addr_reg
, 0);
1087 /* TODO: use block load -
1088 * check that data_reg2 > data_reg or the other way */
1089 if (data_reg
== addr_reg
) {
1090 tcg_out_ld32_12(s
, COND_AL
, data_reg2
, addr_reg
, 4);
1091 tcg_out_ld32_12(s
, COND_AL
, data_reg
, addr_reg
, 0);
1093 tcg_out_ld32_12(s
, COND_AL
, data_reg
, addr_reg
, 0);
1094 tcg_out_ld32_12(s
, COND_AL
, data_reg2
, addr_reg
, 4);
1101 static inline void tcg_out_qemu_st(TCGContext
*s
, const TCGArg
*args
, int opc
)
1103 int addr_reg
, data_reg
, data_reg2
;
1104 #ifdef CONFIG_SOFTMMU
1105 int mem_index
, s_bits
;
1106 # if TARGET_LONG_BITS == 64
1109 uint32_t *label_ptr
;
1114 data_reg2
= *args
++;
1116 data_reg2
= 0; /* suppress warning */
1118 #ifdef CONFIG_SOFTMMU
1119 # if TARGET_LONG_BITS == 64
1120 addr_reg2
= *args
++;
1125 /* Should generate something like the following:
1126 * shr r8, addr_reg, #TARGET_PAGE_BITS
1127 * and r0, r8, #(CPU_TLB_SIZE - 1) @ Assumption: CPU_TLB_BITS <= 8
1128 * add r0, env, r0 lsl #CPU_TLB_ENTRY_BITS
1130 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1131 TCG_REG_R8
, 0, addr_reg
, SHIFT_IMM_LSR(TARGET_PAGE_BITS
));
1132 tcg_out_dat_imm(s
, COND_AL
, ARITH_AND
,
1133 TCG_REG_R0
, TCG_REG_R8
, CPU_TLB_SIZE
- 1);
1134 tcg_out_dat_reg(s
, COND_AL
, ARITH_ADD
, TCG_REG_R0
,
1135 TCG_AREG0
, TCG_REG_R0
, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS
));
1137 * ldr r1 [r0, #(offsetof(CPUState, tlb_table[mem_index][0].addr_write))]
1138 * below, the offset is likely to exceed 12 bits if mem_index != 0 and
1139 * not exceed otherwise, so use an
1140 * add r0, r0, #(mem_index * sizeof *CPUState.tlb_table)
1144 tcg_out_dat_imm(s
, COND_AL
, ARITH_ADD
, TCG_REG_R0
, TCG_REG_R0
,
1145 (mem_index
<< (TLB_SHIFT
& 1)) |
1146 ((16 - (TLB_SHIFT
>> 1)) << 8));
1147 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_R1
, TCG_REG_R0
,
1148 offsetof(CPUState
, tlb_table
[0][0].addr_write
));
1149 tcg_out_dat_reg(s
, COND_AL
, ARITH_CMP
, 0, TCG_REG_R1
,
1150 TCG_REG_R8
, SHIFT_IMM_LSL(TARGET_PAGE_BITS
));
1151 /* Check alignment. */
1153 tcg_out_dat_imm(s
, COND_EQ
, ARITH_TST
,
1154 0, addr_reg
, (1 << s_bits
) - 1);
1155 # if TARGET_LONG_BITS == 64
1156 /* XXX: possibly we could use a block data load or writeback in
1157 * the first access. */
1158 tcg_out_ld32_12(s
, COND_EQ
, TCG_REG_R1
, TCG_REG_R0
,
1159 offsetof(CPUState
, tlb_table
[0][0].addr_write
) + 4);
1160 tcg_out_dat_reg(s
, COND_EQ
, ARITH_CMP
, 0,
1161 TCG_REG_R1
, addr_reg2
, SHIFT_IMM_LSL(0));
1163 tcg_out_ld32_12(s
, COND_EQ
, TCG_REG_R1
, TCG_REG_R0
,
1164 offsetof(CPUState
, tlb_table
[0][0].addend
));
1168 tcg_out_st8_r(s
, COND_EQ
, data_reg
, addr_reg
, TCG_REG_R1
);
1171 tcg_out_st16_r(s
, COND_EQ
, data_reg
, addr_reg
, TCG_REG_R1
);
1175 tcg_out_st32_r(s
, COND_EQ
, data_reg
, addr_reg
, TCG_REG_R1
);
1178 tcg_out_st32_rwb(s
, COND_EQ
, data_reg
, TCG_REG_R1
, addr_reg
);
1179 tcg_out_st32_12(s
, COND_EQ
, data_reg2
, TCG_REG_R1
, 4);
1183 label_ptr
= (void *) s
->code_ptr
;
1184 tcg_out_b(s
, COND_EQ
, 8);
1186 /* TODO: move this code to where the constants pool will be */
1187 if (addr_reg
!= TCG_REG_R0
) {
1188 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1189 TCG_REG_R0
, 0, addr_reg
, SHIFT_IMM_LSL(0));
1191 # if TARGET_LONG_BITS == 32
1194 tcg_out_ext8u(s
, COND_AL
, TCG_REG_R1
, data_reg
);
1195 tcg_out_dat_imm(s
, COND_AL
, ARITH_MOV
, TCG_REG_R2
, 0, mem_index
);
1198 tcg_out_ext16u(s
, COND_AL
, TCG_REG_R1
, data_reg
);
1199 tcg_out_dat_imm(s
, COND_AL
, ARITH_MOV
, TCG_REG_R2
, 0, mem_index
);
1202 if (data_reg
!= TCG_REG_R1
) {
1203 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1204 TCG_REG_R1
, 0, data_reg
, SHIFT_IMM_LSL(0));
1206 tcg_out_dat_imm(s
, COND_AL
, ARITH_MOV
, TCG_REG_R2
, 0, mem_index
);
1209 if (data_reg
!= TCG_REG_R1
) {
1210 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1211 TCG_REG_R1
, 0, data_reg
, SHIFT_IMM_LSL(0));
1213 if (data_reg2
!= TCG_REG_R2
) {
1214 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1215 TCG_REG_R2
, 0, data_reg2
, SHIFT_IMM_LSL(0));
1217 tcg_out_dat_imm(s
, COND_AL
, ARITH_MOV
, TCG_REG_R3
, 0, mem_index
);
1221 if (addr_reg2
!= TCG_REG_R1
) {
1222 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1223 TCG_REG_R1
, 0, addr_reg2
, SHIFT_IMM_LSL(0));
1227 tcg_out_ext8u(s
, COND_AL
, TCG_REG_R2
, data_reg
);
1228 tcg_out_dat_imm(s
, COND_AL
, ARITH_MOV
, TCG_REG_R3
, 0, mem_index
);
1231 tcg_out_ext16u(s
, COND_AL
, TCG_REG_R2
, data_reg
);
1232 tcg_out_dat_imm(s
, COND_AL
, ARITH_MOV
, TCG_REG_R3
, 0, mem_index
);
1235 if (data_reg
!= TCG_REG_R2
) {
1236 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1237 TCG_REG_R2
, 0, data_reg
, SHIFT_IMM_LSL(0));
1239 tcg_out_dat_imm(s
, COND_AL
, ARITH_MOV
, TCG_REG_R3
, 0, mem_index
);
1242 tcg_out_dat_imm(s
, COND_AL
, ARITH_MOV
, TCG_REG_R8
, 0, mem_index
);
1243 tcg_out32(s
, (COND_AL
<< 28) | 0x052d8010); /* str r8, [sp, #-0x10]! */
1244 if (data_reg
!= TCG_REG_R2
) {
1245 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1246 TCG_REG_R2
, 0, data_reg
, SHIFT_IMM_LSL(0));
1248 if (data_reg2
!= TCG_REG_R3
) {
1249 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1250 TCG_REG_R3
, 0, data_reg2
, SHIFT_IMM_LSL(0));
1256 tcg_out_bl(s
, COND_AL
, (tcg_target_long
) qemu_st_helpers
[s_bits
] -
1257 (tcg_target_long
) s
->code_ptr
);
1258 # if TARGET_LONG_BITS == 64
1260 tcg_out_dat_imm(s
, COND_AL
, ARITH_ADD
, TCG_REG_R13
, TCG_REG_R13
, 0x10);
1263 *label_ptr
+= ((void *) s
->code_ptr
- (void *) label_ptr
- 8) >> 2;
1264 #else /* !CONFIG_SOFTMMU */
1266 uint32_t offset
= GUEST_BASE
;
1271 i
= ctz32(offset
) & ~1;
1272 rot
= ((32 - i
) << 7) & 0xf00;
1274 tcg_out_dat_imm(s
, COND_AL
, ARITH_ADD
, TCG_REG_R8
, addr_reg
,
1275 ((offset
>> i
) & 0xff) | rot
);
1276 addr_reg
= TCG_REG_R8
;
1277 offset
&= ~(0xff << i
);
1282 tcg_out_st8_12(s
, COND_AL
, data_reg
, addr_reg
, 0);
1285 tcg_out_st16_8(s
, COND_AL
, data_reg
, addr_reg
, 0);
1289 tcg_out_st32_12(s
, COND_AL
, data_reg
, addr_reg
, 0);
1292 /* TODO: use block store -
1293 * check that data_reg2 > data_reg or the other way */
1294 tcg_out_st32_12(s
, COND_AL
, data_reg
, addr_reg
, 0);
1295 tcg_out_st32_12(s
, COND_AL
, data_reg2
, addr_reg
, 4);
1301 static uint8_t *tb_ret_addr
;
1303 static inline void tcg_out_op(TCGContext
*s
, TCGOpcode opc
,
1304 const TCGArg
*args
, const int *const_args
)
1309 case INDEX_op_exit_tb
:
1311 uint8_t *ld_ptr
= s
->code_ptr
;
1313 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_R0
, TCG_REG_PC
, 0);
1315 tcg_out_dat_imm(s
, COND_AL
, ARITH_MOV
, TCG_REG_R0
, 0, args
[0]);
1316 tcg_out_goto(s
, COND_AL
, (tcg_target_ulong
) tb_ret_addr
);
1318 *ld_ptr
= (uint8_t) (s
->code_ptr
- ld_ptr
) - 8;
1319 tcg_out32(s
, args
[0]);
1323 case INDEX_op_goto_tb
:
1324 if (s
->tb_jmp_offset
) {
1325 /* Direct jump method */
1326 #if defined(USE_DIRECT_JUMP)
1327 s
->tb_jmp_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
1328 tcg_out_b(s
, COND_AL
, 8);
1330 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_PC
, TCG_REG_PC
, -4);
1331 s
->tb_jmp_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
1335 /* Indirect jump method */
1337 c
= (int) (s
->tb_next
+ args
[0]) - ((int) s
->code_ptr
+ 8);
1338 if (c
> 0xfff || c
< -0xfff) {
1339 tcg_out_movi32(s
, COND_AL
, TCG_REG_R0
,
1340 (tcg_target_long
) (s
->tb_next
+ args
[0]));
1341 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_PC
, TCG_REG_R0
, 0);
1343 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_PC
, TCG_REG_PC
, c
);
1345 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_R0
, TCG_REG_PC
, 0);
1346 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_PC
, TCG_REG_R0
, 0);
1347 tcg_out32(s
, (tcg_target_long
) (s
->tb_next
+ args
[0]));
1350 s
->tb_next_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
1354 tcg_out_call(s
, COND_AL
, args
[0]);
1356 tcg_out_callr(s
, COND_AL
, args
[0]);
1360 tcg_out_goto(s
, COND_AL
, args
[0]);
1362 tcg_out_bx(s
, COND_AL
, args
[0]);
1365 tcg_out_goto_label(s
, COND_AL
, args
[0]);
1368 case INDEX_op_ld8u_i32
:
1369 tcg_out_ld8u(s
, COND_AL
, args
[0], args
[1], args
[2]);
1371 case INDEX_op_ld8s_i32
:
1372 tcg_out_ld8s(s
, COND_AL
, args
[0], args
[1], args
[2]);
1374 case INDEX_op_ld16u_i32
:
1375 tcg_out_ld16u(s
, COND_AL
, args
[0], args
[1], args
[2]);
1377 case INDEX_op_ld16s_i32
:
1378 tcg_out_ld16s(s
, COND_AL
, args
[0], args
[1], args
[2]);
1380 case INDEX_op_ld_i32
:
1381 tcg_out_ld32u(s
, COND_AL
, args
[0], args
[1], args
[2]);
1383 case INDEX_op_st8_i32
:
1384 tcg_out_st8(s
, COND_AL
, args
[0], args
[1], args
[2]);
1386 case INDEX_op_st16_i32
:
1387 tcg_out_st16(s
, COND_AL
, args
[0], args
[1], args
[2]);
1389 case INDEX_op_st_i32
:
1390 tcg_out_st32(s
, COND_AL
, args
[0], args
[1], args
[2]);
1393 case INDEX_op_mov_i32
:
1394 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
,
1395 args
[0], 0, args
[1], SHIFT_IMM_LSL(0));
1397 case INDEX_op_movi_i32
:
1398 tcg_out_movi32(s
, COND_AL
, args
[0], args
[1]);
1400 case INDEX_op_add_i32
:
1403 case INDEX_op_sub_i32
:
1406 case INDEX_op_and_i32
:
1409 case INDEX_op_andc_i32
:
1412 case INDEX_op_or_i32
:
1415 case INDEX_op_xor_i32
:
1419 if (const_args
[2]) {
1421 rot
= encode_imm(args
[2]);
1422 tcg_out_dat_imm(s
, COND_AL
, c
,
1423 args
[0], args
[1], rotl(args
[2], rot
) | (rot
<< 7));
1425 tcg_out_dat_reg(s
, COND_AL
, c
,
1426 args
[0], args
[1], args
[2], SHIFT_IMM_LSL(0));
1428 case INDEX_op_add2_i32
:
1429 tcg_out_dat_reg2(s
, COND_AL
, ARITH_ADD
, ARITH_ADC
,
1430 args
[0], args
[1], args
[2], args
[3],
1431 args
[4], args
[5], SHIFT_IMM_LSL(0));
1433 case INDEX_op_sub2_i32
:
1434 tcg_out_dat_reg2(s
, COND_AL
, ARITH_SUB
, ARITH_SBC
,
1435 args
[0], args
[1], args
[2], args
[3],
1436 args
[4], args
[5], SHIFT_IMM_LSL(0));
1438 case INDEX_op_neg_i32
:
1439 tcg_out_dat_imm(s
, COND_AL
, ARITH_RSB
, args
[0], args
[1], 0);
1441 case INDEX_op_not_i32
:
1442 tcg_out_dat_reg(s
, COND_AL
,
1443 ARITH_MVN
, args
[0], 0, args
[1], SHIFT_IMM_LSL(0));
1445 case INDEX_op_mul_i32
:
1446 tcg_out_mul32(s
, COND_AL
, args
[0], args
[1], args
[2]);
1448 case INDEX_op_mulu2_i32
:
1449 tcg_out_umull32(s
, COND_AL
, args
[0], args
[1], args
[2], args
[3]);
1451 /* XXX: Perhaps args[2] & 0x1f is wrong */
1452 case INDEX_op_shl_i32
:
1454 SHIFT_IMM_LSL(args
[2] & 0x1f) : SHIFT_REG_LSL(args
[2]);
1456 case INDEX_op_shr_i32
:
1457 c
= const_args
[2] ? (args
[2] & 0x1f) ? SHIFT_IMM_LSR(args
[2] & 0x1f) :
1458 SHIFT_IMM_LSL(0) : SHIFT_REG_LSR(args
[2]);
1460 case INDEX_op_sar_i32
:
1461 c
= const_args
[2] ? (args
[2] & 0x1f) ? SHIFT_IMM_ASR(args
[2] & 0x1f) :
1462 SHIFT_IMM_LSL(0) : SHIFT_REG_ASR(args
[2]);
1464 case INDEX_op_rotr_i32
:
1465 c
= const_args
[2] ? (args
[2] & 0x1f) ? SHIFT_IMM_ROR(args
[2] & 0x1f) :
1466 SHIFT_IMM_LSL(0) : SHIFT_REG_ROR(args
[2]);
1469 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
, args
[0], 0, args
[1], c
);
1472 case INDEX_op_rotl_i32
:
1473 if (const_args
[2]) {
1474 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
, args
[0], 0, args
[1],
1475 ((0x20 - args
[2]) & 0x1f) ?
1476 SHIFT_IMM_ROR((0x20 - args
[2]) & 0x1f) :
1479 tcg_out_dat_imm(s
, COND_AL
, ARITH_RSB
, TCG_REG_R8
, args
[1], 0x20);
1480 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
, args
[0], 0, args
[1],
1481 SHIFT_REG_ROR(TCG_REG_R8
));
1485 case INDEX_op_brcond_i32
:
1486 if (const_args
[1]) {
1488 rot
= encode_imm(args
[1]);
1489 tcg_out_dat_imm(s
, COND_AL
, ARITH_CMP
, 0,
1490 args
[0], rotl(args
[1], rot
) | (rot
<< 7));
1492 tcg_out_dat_reg(s
, COND_AL
, ARITH_CMP
, 0,
1493 args
[0], args
[1], SHIFT_IMM_LSL(0));
1495 tcg_out_goto_label(s
, tcg_cond_to_arm_cond
[args
[2]], args
[3]);
1497 case INDEX_op_brcond2_i32
:
1498 /* The resulting conditions are:
1499 * TCG_COND_EQ --> a0 == a2 && a1 == a3,
1500 * TCG_COND_NE --> (a0 != a2 && a1 == a3) || a1 != a3,
1501 * TCG_COND_LT(U) --> (a0 < a2 && a1 == a3) || a1 < a3,
1502 * TCG_COND_GE(U) --> (a0 >= a2 && a1 == a3) || (a1 >= a3 && a1 != a3),
1503 * TCG_COND_LE(U) --> (a0 <= a2 && a1 == a3) || (a1 <= a3 && a1 != a3),
1504 * TCG_COND_GT(U) --> (a0 > a2 && a1 == a3) || a1 > a3,
1506 tcg_out_dat_reg(s
, COND_AL
, ARITH_CMP
, 0,
1507 args
[1], args
[3], SHIFT_IMM_LSL(0));
1508 tcg_out_dat_reg(s
, COND_EQ
, ARITH_CMP
, 0,
1509 args
[0], args
[2], SHIFT_IMM_LSL(0));
1510 tcg_out_goto_label(s
, tcg_cond_to_arm_cond
[args
[4]], args
[5]);
1512 case INDEX_op_setcond_i32
:
1513 if (const_args
[2]) {
1515 rot
= encode_imm(args
[2]);
1516 tcg_out_dat_imm(s
, COND_AL
, ARITH_CMP
, 0,
1517 args
[1], rotl(args
[2], rot
) | (rot
<< 7));
1519 tcg_out_dat_reg(s
, COND_AL
, ARITH_CMP
, 0,
1520 args
[1], args
[2], SHIFT_IMM_LSL(0));
1522 tcg_out_dat_imm(s
, tcg_cond_to_arm_cond
[args
[3]],
1523 ARITH_MOV
, args
[0], 0, 1);
1524 tcg_out_dat_imm(s
, tcg_cond_to_arm_cond
[tcg_invert_cond(args
[3])],
1525 ARITH_MOV
, args
[0], 0, 0);
1527 case INDEX_op_setcond2_i32
:
1528 /* See brcond2_i32 comment */
1529 tcg_out_dat_reg(s
, COND_AL
, ARITH_CMP
, 0,
1530 args
[2], args
[4], SHIFT_IMM_LSL(0));
1531 tcg_out_dat_reg(s
, COND_EQ
, ARITH_CMP
, 0,
1532 args
[1], args
[3], SHIFT_IMM_LSL(0));
1533 tcg_out_dat_imm(s
, tcg_cond_to_arm_cond
[args
[5]],
1534 ARITH_MOV
, args
[0], 0, 1);
1535 tcg_out_dat_imm(s
, tcg_cond_to_arm_cond
[tcg_invert_cond(args
[5])],
1536 ARITH_MOV
, args
[0], 0, 0);
1539 case INDEX_op_qemu_ld8u
:
1540 tcg_out_qemu_ld(s
, args
, 0);
1542 case INDEX_op_qemu_ld8s
:
1543 tcg_out_qemu_ld(s
, args
, 0 | 4);
1545 case INDEX_op_qemu_ld16u
:
1546 tcg_out_qemu_ld(s
, args
, 1);
1548 case INDEX_op_qemu_ld16s
:
1549 tcg_out_qemu_ld(s
, args
, 1 | 4);
1551 case INDEX_op_qemu_ld32
:
1552 tcg_out_qemu_ld(s
, args
, 2);
1554 case INDEX_op_qemu_ld64
:
1555 tcg_out_qemu_ld(s
, args
, 3);
1558 case INDEX_op_qemu_st8
:
1559 tcg_out_qemu_st(s
, args
, 0);
1561 case INDEX_op_qemu_st16
:
1562 tcg_out_qemu_st(s
, args
, 1);
1564 case INDEX_op_qemu_st32
:
1565 tcg_out_qemu_st(s
, args
, 2);
1567 case INDEX_op_qemu_st64
:
1568 tcg_out_qemu_st(s
, args
, 3);
1571 case INDEX_op_bswap16_i32
:
1572 tcg_out_bswap16(s
, COND_AL
, args
[0], args
[1]);
1574 case INDEX_op_bswap32_i32
:
1575 tcg_out_bswap32(s
, COND_AL
, args
[0], args
[1]);
1578 case INDEX_op_ext8s_i32
:
1579 tcg_out_ext8s(s
, COND_AL
, args
[0], args
[1]);
1581 case INDEX_op_ext16s_i32
:
1582 tcg_out_ext16s(s
, COND_AL
, args
[0], args
[1]);
1584 case INDEX_op_ext16u_i32
:
1585 tcg_out_ext16u(s
, COND_AL
, args
[0], args
[1]);
1593 static const TCGTargetOpDef arm_op_defs
[] = {
1594 { INDEX_op_exit_tb
, { } },
1595 { INDEX_op_goto_tb
, { } },
1596 { INDEX_op_call
, { "ri" } },
1597 { INDEX_op_jmp
, { "ri" } },
1598 { INDEX_op_br
, { } },
1600 { INDEX_op_mov_i32
, { "r", "r" } },
1601 { INDEX_op_movi_i32
, { "r" } },
1603 { INDEX_op_ld8u_i32
, { "r", "r" } },
1604 { INDEX_op_ld8s_i32
, { "r", "r" } },
1605 { INDEX_op_ld16u_i32
, { "r", "r" } },
1606 { INDEX_op_ld16s_i32
, { "r", "r" } },
1607 { INDEX_op_ld_i32
, { "r", "r" } },
1608 { INDEX_op_st8_i32
, { "r", "r" } },
1609 { INDEX_op_st16_i32
, { "r", "r" } },
1610 { INDEX_op_st_i32
, { "r", "r" } },
1612 /* TODO: "r", "r", "ri" */
1613 { INDEX_op_add_i32
, { "r", "r", "rI" } },
1614 { INDEX_op_sub_i32
, { "r", "r", "rI" } },
1615 { INDEX_op_mul_i32
, { "r", "r", "r" } },
1616 { INDEX_op_mulu2_i32
, { "r", "r", "r", "r" } },
1617 { INDEX_op_and_i32
, { "r", "r", "rI" } },
1618 { INDEX_op_andc_i32
, { "r", "r", "rI" } },
1619 { INDEX_op_or_i32
, { "r", "r", "rI" } },
1620 { INDEX_op_xor_i32
, { "r", "r", "rI" } },
1621 { INDEX_op_neg_i32
, { "r", "r" } },
1622 { INDEX_op_not_i32
, { "r", "r" } },
1624 { INDEX_op_shl_i32
, { "r", "r", "ri" } },
1625 { INDEX_op_shr_i32
, { "r", "r", "ri" } },
1626 { INDEX_op_sar_i32
, { "r", "r", "ri" } },
1627 { INDEX_op_rotl_i32
, { "r", "r", "ri" } },
1628 { INDEX_op_rotr_i32
, { "r", "r", "ri" } },
1630 { INDEX_op_brcond_i32
, { "r", "rI" } },
1631 { INDEX_op_setcond_i32
, { "r", "r", "rI" } },
1633 /* TODO: "r", "r", "r", "r", "ri", "ri" */
1634 { INDEX_op_add2_i32
, { "r", "r", "r", "r", "r", "r" } },
1635 { INDEX_op_sub2_i32
, { "r", "r", "r", "r", "r", "r" } },
1636 { INDEX_op_brcond2_i32
, { "r", "r", "r", "r" } },
1637 { INDEX_op_setcond2_i32
, { "r", "r", "r", "r", "r" } },
1639 #if TARGET_LONG_BITS == 32
1640 { INDEX_op_qemu_ld8u
, { "r", "x" } },
1641 { INDEX_op_qemu_ld8s
, { "r", "x" } },
1642 { INDEX_op_qemu_ld16u
, { "r", "x" } },
1643 { INDEX_op_qemu_ld16s
, { "r", "x" } },
1644 { INDEX_op_qemu_ld32
, { "r", "x" } },
1645 { INDEX_op_qemu_ld64
, { "d", "r", "x" } },
1647 { INDEX_op_qemu_st8
, { "x", "x" } },
1648 { INDEX_op_qemu_st16
, { "x", "x" } },
1649 { INDEX_op_qemu_st32
, { "x", "x" } },
1650 { INDEX_op_qemu_st64
, { "x", "D", "x" } },
1652 { INDEX_op_qemu_ld8u
, { "r", "x", "X" } },
1653 { INDEX_op_qemu_ld8s
, { "r", "x", "X" } },
1654 { INDEX_op_qemu_ld16u
, { "r", "x", "X" } },
1655 { INDEX_op_qemu_ld16s
, { "r", "x", "X" } },
1656 { INDEX_op_qemu_ld32
, { "r", "x", "X" } },
1657 { INDEX_op_qemu_ld64
, { "d", "r", "x", "X" } },
1659 { INDEX_op_qemu_st8
, { "x", "x", "X" } },
1660 { INDEX_op_qemu_st16
, { "x", "x", "X" } },
1661 { INDEX_op_qemu_st32
, { "x", "x", "X" } },
1662 { INDEX_op_qemu_st64
, { "x", "D", "x", "X" } },
1665 { INDEX_op_bswap16_i32
, { "r", "r" } },
1666 { INDEX_op_bswap32_i32
, { "r", "r" } },
1668 { INDEX_op_ext8s_i32
, { "r", "r" } },
1669 { INDEX_op_ext16s_i32
, { "r", "r" } },
1670 { INDEX_op_ext16u_i32
, { "r", "r" } },
1675 void tcg_target_init(TCGContext
*s
)
1677 #if !defined(CONFIG_USER_ONLY)
1679 if ((1 << CPU_TLB_ENTRY_BITS
) != sizeof(CPUTLBEntry
))
1683 tcg_regset_set32(tcg_target_available_regs
[TCG_TYPE_I32
], 0, 0xffff);
1684 tcg_regset_set32(tcg_target_call_clobber_regs
, 0,
1689 (1 << TCG_REG_R12
) |
1690 (1 << TCG_REG_R14
));
1692 tcg_regset_clear(s
->reserved_regs
);
1693 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_CALL_STACK
);
1694 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R8
);
1695 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_PC
);
1697 tcg_add_target_add_op_defs(arm_op_defs
);
1700 static inline void tcg_out_ld(TCGContext
*s
, TCGType type
, int arg
,
1701 int arg1
, tcg_target_long arg2
)
1703 tcg_out_ld32u(s
, COND_AL
, arg
, arg1
, arg2
);
1706 static inline void tcg_out_st(TCGContext
*s
, TCGType type
, int arg
,
1707 int arg1
, tcg_target_long arg2
)
1709 tcg_out_st32(s
, COND_AL
, arg
, arg1
, arg2
);
1712 static void tcg_out_addi(TCGContext
*s
, int reg
, tcg_target_long val
)
1716 tcg_out_dat_imm(s
, COND_AL
, ARITH_ADD
, reg
, reg
, val
);
1721 tcg_out_dat_imm(s
, COND_AL
, ARITH_SUB
, reg
, reg
, -val
);
1727 static inline void tcg_out_mov(TCGContext
*s
, int ret
, int arg
)
1729 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
, ret
, 0, arg
, SHIFT_IMM_LSL(0));
1732 static inline void tcg_out_movi(TCGContext
*s
, TCGType type
,
1733 int ret
, tcg_target_long arg
)
1735 tcg_out_movi32(s
, COND_AL
, ret
, arg
);
1738 void tcg_target_qemu_prologue(TCGContext
*s
)
1740 /* There is no need to save r7, it is used to store the address
1741 of the env structure and is not modified by GCC. */
1743 /* stmdb sp!, { r4 - r6, r8 - r11, lr } */
1744 tcg_out32(s
, (COND_AL
<< 28) | 0x092d4f70);
1746 tcg_out_bx(s
, COND_AL
, TCG_REG_R0
);
1747 tb_ret_addr
= s
->code_ptr
;
1749 /* ldmia sp!, { r4 - r6, r8 - r11, pc } */
1750 tcg_out32(s
, (COND_AL
<< 28) | 0x08bd8f70);