hw/ide/mmio.c

   1 /*
   2  * QEMU IDE Emulation: mmio support (for embedded).
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  * Copyright (c) 2006 Openedhand Ltd.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include <hw/hw.h>
  26 #include "block.h"
  27 #include "dma.h"
  28
  29 #include <hw/ide/internal.h>
  30
  31 /***********************************************************/
  32 /* MMIO based ide port
  33  * This emulates IDE device connected directly to the CPU bus without
  34  * dedicated ide controller, which is often seen on embedded boards.
  35  */
  36
  37 typedef struct {
  38     IDEBus bus;
  39     int shift;
  40 } MMIOState;
  41
  42 static void mmio_ide_reset(void *opaque)
  43 {
  44     MMIOState *s = opaque;
  45
  46     ide_bus_reset(&s->bus);
  47 }
  48
  49 static uint32_t mmio_ide_read (void *opaque, target_phys_addr_t addr)
  50 {
  51     MMIOState *s = opaque;
  52     addr >>= s->shift;
  53     if (addr & 7)
  54         return ide_ioport_read(&s->bus, addr);
  55     else
  56         return ide_data_readw(&s->bus, 0);
  57 }
  58
  59 static void mmio_ide_write (void *opaque, target_phys_addr_t addr,
  60         uint32_t val)
  61 {
  62     MMIOState *s = opaque;
  63     addr >>= s->shift;
  64     if (addr & 7)
  65         ide_ioport_write(&s->bus, addr, val);
  66     else
  67         ide_data_writew(&s->bus, 0, val);
  68 }
  69
  70 static CPUReadMemoryFunc * const mmio_ide_reads[] = {
  71     mmio_ide_read,
  72     mmio_ide_read,
  73     mmio_ide_read,
  74 };
  75
  76 static CPUWriteMemoryFunc * const mmio_ide_writes[] = {
  77     mmio_ide_write,
  78     mmio_ide_write,
  79     mmio_ide_write,
  80 };
  81
  82 static uint32_t mmio_ide_status_read (void *opaque, target_phys_addr_t addr)
  83 {
  84     MMIOState *s= opaque;
  85     return ide_status_read(&s->bus, 0);
  86 }
  87
  88 static void mmio_ide_cmd_write (void *opaque, target_phys_addr_t addr,
  89         uint32_t val)
  90 {
  91     MMIOState *s = opaque;
  92     ide_cmd_write(&s->bus, 0, val);
  93 }
  94
  95 static CPUReadMemoryFunc * const mmio_ide_status[] = {
  96     mmio_ide_status_read,
  97     mmio_ide_status_read,
  98     mmio_ide_status_read,
  99 };
 100
 101 static CPUWriteMemoryFunc * const mmio_ide_cmd[] = {
 102     mmio_ide_cmd_write,
 103     mmio_ide_cmd_write,
 104     mmio_ide_cmd_write,
 105 };
 106
 107 static const VMStateDescription vmstate_ide_mmio = {
 108     .name = "mmio-ide",
 109     .version_id = 3,
 110     .minimum_version_id = 0,
 111     .minimum_version_id_old = 0,
 112     .fields      = (VMStateField []) {
 113         VMSTATE_IDE_BUS(bus, MMIOState),
 114         VMSTATE_IDE_DRIVES(bus.ifs, MMIOState),
 115         VMSTATE_END_OF_LIST()
 116     }
 117 };
 118
 119 void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2,
 120                     qemu_irq irq, int shift,
 121                     DriveInfo *hd0, DriveInfo *hd1)
 122 {
 123     MMIOState *s = g_malloc0(sizeof(MMIOState));
 124     int mem1, mem2;
 125
 126     ide_init2_with_non_qdev_drives(&s->bus, hd0, hd1, irq);
 127
 128     s->shift = shift;
 129
 130     mem1 = cpu_register_io_memory(mmio_ide_reads, mmio_ide_writes, s,
 131                                   DEVICE_NATIVE_ENDIAN);
 132     mem2 = cpu_register_io_memory(mmio_ide_status, mmio_ide_cmd, s,
 133                                   DEVICE_NATIVE_ENDIAN);
 134     cpu_register_physical_memory(membase, 16 << shift, mem1);
 135     cpu_register_physical_memory(membase2, 2 << shift, mem2);
 136     vmstate_register(NULL, 0, &vmstate_ide_mmio, s);
 137     qemu_register_reset(mmio_ide_reset, s);
 138 }
 139