2 * QEMU 8253/8254 - common bits of emulated and KVM kernel model
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 * Copyright (c) 2012 Jan Kiszka, Siemens AG
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "qemu/osdep.h"
28 #include "hw/isa/isa.h"
29 #include "qemu/module.h"
30 #include "qemu/timer.h"
31 #include "hw/timer/i8254.h"
32 #include "hw/timer/i8254_internal.h"
34 /* val must be 0 or 1 */
35 void pit_set_gate(ISADevice
*dev
, int channel
, int val
)
37 PITCommonState
*pit
= PIT_COMMON(dev
);
38 PITChannelState
*s
= &pit
->channels
[channel
];
39 PITCommonClass
*c
= PIT_COMMON_GET_CLASS(pit
);
41 c
->set_channel_gate(pit
, s
, val
);
44 /* get pit output bit */
45 int pit_get_out(PITChannelState
*s
, int64_t current_time
)
50 d
= muldiv64(current_time
- s
->count_load_time
, PIT_FREQ
,
51 NANOSECONDS_PER_SECOND
);
55 out
= (d
>= s
->count
);
61 if ((d
% s
->count
) == 0 && d
!= 0) {
68 out
= (d
% s
->count
) < ((s
->count
+ 1) >> 1);
72 out
= (d
== s
->count
);
78 /* return -1 if no transition will occur. */
79 int64_t pit_get_next_transition_time(PITChannelState
*s
, int64_t current_time
)
81 uint64_t d
, next_time
, base
;
84 d
= muldiv64(current_time
- s
->count_load_time
, PIT_FREQ
,
85 NANOSECONDS_PER_SECOND
);
97 base
= QEMU_ALIGN_DOWN(d
, s
->count
);
98 if ((d
- base
) == 0 && d
!= 0) {
99 next_time
= base
+ s
->count
;
101 next_time
= base
+ s
->count
+ 1;
105 base
= QEMU_ALIGN_DOWN(d
, s
->count
);
106 period2
= ((s
->count
+ 1) >> 1);
107 if ((d
- base
) < period2
) {
108 next_time
= base
+ period2
;
110 next_time
= base
+ s
->count
;
116 next_time
= s
->count
;
117 } else if (d
== s
->count
) {
118 next_time
= s
->count
+ 1;
124 /* convert to timer units */
125 next_time
= s
->count_load_time
+ muldiv64(next_time
, NANOSECONDS_PER_SECOND
,
127 /* fix potential rounding problems */
128 /* XXX: better solution: use a clock at PIT_FREQ Hz */
129 if (next_time
<= current_time
) {
130 next_time
= current_time
+ 1;
135 void pit_get_channel_info_common(PITCommonState
*s
, PITChannelState
*sc
,
136 PITChannelInfo
*info
)
138 info
->gate
= sc
->gate
;
139 info
->mode
= sc
->mode
;
140 info
->initial_count
= sc
->count
;
141 info
->out
= pit_get_out(sc
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
));
144 void pit_get_channel_info(ISADevice
*dev
, int channel
, PITChannelInfo
*info
)
146 PITCommonState
*pit
= PIT_COMMON(dev
);
147 PITChannelState
*s
= &pit
->channels
[channel
];
148 PITCommonClass
*c
= PIT_COMMON_GET_CLASS(pit
);
150 c
->get_channel_info(pit
, s
, info
);
153 void pit_reset_common(PITCommonState
*pit
)
158 for (i
= 0; i
< 3; i
++) {
159 s
= &pit
->channels
[i
];
162 s
->count_load_time
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
164 if (i
== 0 && !s
->irq_disabled
) {
165 s
->next_transition_time
=
166 pit_get_next_transition_time(s
, s
->count_load_time
);
171 static void pit_common_realize(DeviceState
*dev
, Error
**errp
)
173 ISADevice
*isadev
= ISA_DEVICE(dev
);
174 PITCommonState
*pit
= PIT_COMMON(dev
);
176 isa_register_ioport(isadev
, &pit
->ioports
, pit
->iobase
);
178 qdev_set_legacy_instance_id(dev
, pit
->iobase
, 2);
181 static const VMStateDescription vmstate_pit_channel
= {
182 .name
= "pit channel",
184 .minimum_version_id
= 2,
185 .fields
= (VMStateField
[]) {
186 VMSTATE_INT32(count
, PITChannelState
),
187 VMSTATE_UINT16(latched_count
, PITChannelState
),
188 VMSTATE_UINT8(count_latched
, PITChannelState
),
189 VMSTATE_UINT8(status_latched
, PITChannelState
),
190 VMSTATE_UINT8(status
, PITChannelState
),
191 VMSTATE_UINT8(read_state
, PITChannelState
),
192 VMSTATE_UINT8(write_state
, PITChannelState
),
193 VMSTATE_UINT8(write_latch
, PITChannelState
),
194 VMSTATE_UINT8(rw_mode
, PITChannelState
),
195 VMSTATE_UINT8(mode
, PITChannelState
),
196 VMSTATE_UINT8(bcd
, PITChannelState
),
197 VMSTATE_UINT8(gate
, PITChannelState
),
198 VMSTATE_INT64(count_load_time
, PITChannelState
),
199 VMSTATE_INT64(next_transition_time
, PITChannelState
),
200 VMSTATE_END_OF_LIST()
204 static int pit_load_old(QEMUFile
*f
, void *opaque
, int version_id
)
206 PITCommonState
*pit
= opaque
;
207 PITCommonClass
*c
= PIT_COMMON_GET_CLASS(pit
);
211 if (version_id
!= 1) {
215 for (i
= 0; i
< 3; i
++) {
216 s
= &pit
->channels
[i
];
217 s
->count
= qemu_get_be32(f
);
218 qemu_get_be16s(f
, &s
->latched_count
);
219 qemu_get_8s(f
, &s
->count_latched
);
220 qemu_get_8s(f
, &s
->status_latched
);
221 qemu_get_8s(f
, &s
->status
);
222 qemu_get_8s(f
, &s
->read_state
);
223 qemu_get_8s(f
, &s
->write_state
);
224 qemu_get_8s(f
, &s
->write_latch
);
225 qemu_get_8s(f
, &s
->rw_mode
);
226 qemu_get_8s(f
, &s
->mode
);
227 qemu_get_8s(f
, &s
->bcd
);
228 qemu_get_8s(f
, &s
->gate
);
229 s
->count_load_time
= qemu_get_be64(f
);
232 s
->next_transition_time
= qemu_get_be64(f
);
241 static int pit_dispatch_pre_save(void *opaque
)
243 PITCommonState
*s
= opaque
;
244 PITCommonClass
*c
= PIT_COMMON_GET_CLASS(s
);
253 static int pit_dispatch_post_load(void *opaque
, int version_id
)
255 PITCommonState
*s
= opaque
;
256 PITCommonClass
*c
= PIT_COMMON_GET_CLASS(s
);
264 static const VMStateDescription vmstate_pit_common
= {
267 .minimum_version_id
= 2,
268 .minimum_version_id_old
= 1,
269 .load_state_old
= pit_load_old
,
270 .pre_save
= pit_dispatch_pre_save
,
271 .post_load
= pit_dispatch_post_load
,
272 .fields
= (VMStateField
[]) {
273 VMSTATE_UINT32_V(channels
[0].irq_disabled
, PITCommonState
, 3),
274 VMSTATE_STRUCT_ARRAY(channels
, PITCommonState
, 3, 2,
275 vmstate_pit_channel
, PITChannelState
),
276 VMSTATE_INT64(channels
[0].next_transition_time
,
277 PITCommonState
), /* formerly irq_timer */
278 VMSTATE_END_OF_LIST()
282 static void pit_common_class_init(ObjectClass
*klass
, void *data
)
284 DeviceClass
*dc
= DEVICE_CLASS(klass
);
286 dc
->realize
= pit_common_realize
;
287 dc
->vmsd
= &vmstate_pit_common
;
289 * Reason: unlike ordinary ISA devices, the PIT may need to be
290 * wired to the HPET, and because of that, some wiring is always
291 * done by board code.
293 dc
->user_creatable
= false;
296 static const TypeInfo pit_common_type
= {
297 .name
= TYPE_PIT_COMMON
,
298 .parent
= TYPE_ISA_DEVICE
,
299 .instance_size
= sizeof(PITCommonState
),
300 .class_size
= sizeof(PITCommonClass
),
301 .class_init
= pit_common_class_init
,
305 static void register_devices(void)
307 type_register_static(&pit_common_type
);
310 type_init(register_devices
);