4 * Copyright (c) 2010 qiaochong@loongson.cn
5 * Copyright (c) 2010 Roland Elek <elek.roland@gmail.com>
6 * Copyright (c) 2010 Sebastian Herbszt <herbszt@gmx.de>
7 * Copyright (c) 2010 Alexander Graf <agraf@suse.de>
9 * This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public
11 * License as published by the Free Software Foundation; either
12 * version 2 of the License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * Lesser General Public License for more details.
19 * You should have received a copy of the GNU Lesser General Public
20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
24 #include "qemu/osdep.h"
26 #include "hw/pci/msi.h"
27 #include "hw/pci/pci.h"
29 #include "qemu/error-report.h"
31 #include "qemu/module.h"
32 #include "sysemu/block-backend.h"
33 #include "sysemu/dma.h"
34 #include "hw/ide/internal.h"
35 #include "hw/ide/pci.h"
36 #include "ahci_internal.h"
40 static void check_cmd(AHCIState
*s
, int port
);
41 static int handle_cmd(AHCIState
*s
, int port
, uint8_t slot
);
42 static void ahci_reset_port(AHCIState
*s
, int port
);
43 static bool ahci_write_fis_d2h(AHCIDevice
*ad
);
44 static void ahci_init_d2h(AHCIDevice
*ad
);
45 static int ahci_dma_prepare_buf(IDEDMA
*dma
, int32_t limit
);
46 static bool ahci_map_clb_address(AHCIDevice
*ad
);
47 static bool ahci_map_fis_address(AHCIDevice
*ad
);
48 static void ahci_unmap_clb_address(AHCIDevice
*ad
);
49 static void ahci_unmap_fis_address(AHCIDevice
*ad
);
51 static const char *AHCIHostReg_lookup
[AHCI_HOST_REG__COUNT
] = {
52 [AHCI_HOST_REG_CAP
] = "CAP",
53 [AHCI_HOST_REG_CTL
] = "GHC",
54 [AHCI_HOST_REG_IRQ_STAT
] = "IS",
55 [AHCI_HOST_REG_PORTS_IMPL
] = "PI",
56 [AHCI_HOST_REG_VERSION
] = "VS",
57 [AHCI_HOST_REG_CCC_CTL
] = "CCC_CTL",
58 [AHCI_HOST_REG_CCC_PORTS
] = "CCC_PORTS",
59 [AHCI_HOST_REG_EM_LOC
] = "EM_LOC",
60 [AHCI_HOST_REG_EM_CTL
] = "EM_CTL",
61 [AHCI_HOST_REG_CAP2
] = "CAP2",
62 [AHCI_HOST_REG_BOHC
] = "BOHC",
65 static const char *AHCIPortReg_lookup
[AHCI_PORT_REG__COUNT
] = {
66 [AHCI_PORT_REG_LST_ADDR
] = "PxCLB",
67 [AHCI_PORT_REG_LST_ADDR_HI
] = "PxCLBU",
68 [AHCI_PORT_REG_FIS_ADDR
] = "PxFB",
69 [AHCI_PORT_REG_FIS_ADDR_HI
] = "PxFBU",
70 [AHCI_PORT_REG_IRQ_STAT
] = "PxIS",
71 [AHCI_PORT_REG_IRQ_MASK
] = "PXIE",
72 [AHCI_PORT_REG_CMD
] = "PxCMD",
74 [AHCI_PORT_REG_TFDATA
] = "PxTFD",
75 [AHCI_PORT_REG_SIG
] = "PxSIG",
76 [AHCI_PORT_REG_SCR_STAT
] = "PxSSTS",
77 [AHCI_PORT_REG_SCR_CTL
] = "PxSCTL",
78 [AHCI_PORT_REG_SCR_ERR
] = "PxSERR",
79 [AHCI_PORT_REG_SCR_ACT
] = "PxSACT",
80 [AHCI_PORT_REG_CMD_ISSUE
] = "PxCI",
81 [AHCI_PORT_REG_SCR_NOTIF
] = "PxSNTF",
82 [AHCI_PORT_REG_FIS_CTL
] = "PxFBS",
83 [AHCI_PORT_REG_DEV_SLEEP
] = "PxDEVSLP",
84 [18 ... 27] = "Reserved",
85 [AHCI_PORT_REG_VENDOR_1
...
86 AHCI_PORT_REG_VENDOR_4
] = "PxVS",
89 static const char *AHCIPortIRQ_lookup
[AHCI_PORT_IRQ__COUNT
] = {
90 [AHCI_PORT_IRQ_BIT_DHRS
] = "DHRS",
91 [AHCI_PORT_IRQ_BIT_PSS
] = "PSS",
92 [AHCI_PORT_IRQ_BIT_DSS
] = "DSS",
93 [AHCI_PORT_IRQ_BIT_SDBS
] = "SDBS",
94 [AHCI_PORT_IRQ_BIT_UFS
] = "UFS",
95 [AHCI_PORT_IRQ_BIT_DPS
] = "DPS",
96 [AHCI_PORT_IRQ_BIT_PCS
] = "PCS",
97 [AHCI_PORT_IRQ_BIT_DMPS
] = "DMPS",
98 [8 ... 21] = "RESERVED",
99 [AHCI_PORT_IRQ_BIT_PRCS
] = "PRCS",
100 [AHCI_PORT_IRQ_BIT_IPMS
] = "IPMS",
101 [AHCI_PORT_IRQ_BIT_OFS
] = "OFS",
103 [AHCI_PORT_IRQ_BIT_INFS
] = "INFS",
104 [AHCI_PORT_IRQ_BIT_IFS
] = "IFS",
105 [AHCI_PORT_IRQ_BIT_HBDS
] = "HBDS",
106 [AHCI_PORT_IRQ_BIT_HBFS
] = "HBFS",
107 [AHCI_PORT_IRQ_BIT_TFES
] = "TFES",
108 [AHCI_PORT_IRQ_BIT_CPDS
] = "CPDS"
111 static uint32_t ahci_port_read(AHCIState
*s
, int port
, int offset
)
114 AHCIPortRegs
*pr
= &s
->dev
[port
].port_regs
;
115 enum AHCIPortReg regnum
= offset
/ sizeof(uint32_t);
116 assert(regnum
< (AHCI_PORT_ADDR_OFFSET_LEN
/ sizeof(uint32_t)));
119 case AHCI_PORT_REG_LST_ADDR
:
122 case AHCI_PORT_REG_LST_ADDR_HI
:
123 val
= pr
->lst_addr_hi
;
125 case AHCI_PORT_REG_FIS_ADDR
:
128 case AHCI_PORT_REG_FIS_ADDR_HI
:
129 val
= pr
->fis_addr_hi
;
131 case AHCI_PORT_REG_IRQ_STAT
:
134 case AHCI_PORT_REG_IRQ_MASK
:
137 case AHCI_PORT_REG_CMD
:
140 case AHCI_PORT_REG_TFDATA
:
143 case AHCI_PORT_REG_SIG
:
146 case AHCI_PORT_REG_SCR_STAT
:
147 if (s
->dev
[port
].port
.ifs
[0].blk
) {
148 val
= SATA_SCR_SSTATUS_DET_DEV_PRESENT_PHY_UP
|
149 SATA_SCR_SSTATUS_SPD_GEN1
| SATA_SCR_SSTATUS_IPM_ACTIVE
;
151 val
= SATA_SCR_SSTATUS_DET_NODEV
;
154 case AHCI_PORT_REG_SCR_CTL
:
157 case AHCI_PORT_REG_SCR_ERR
:
160 case AHCI_PORT_REG_SCR_ACT
:
163 case AHCI_PORT_REG_CMD_ISSUE
:
167 trace_ahci_port_read_default(s
, port
, AHCIPortReg_lookup
[regnum
],
172 trace_ahci_port_read(s
, port
, AHCIPortReg_lookup
[regnum
], offset
, val
);
176 static void ahci_irq_raise(AHCIState
*s
)
178 DeviceState
*dev_state
= s
->container
;
179 PCIDevice
*pci_dev
= (PCIDevice
*) object_dynamic_cast(OBJECT(dev_state
),
182 trace_ahci_irq_raise(s
);
184 if (pci_dev
&& msi_enabled(pci_dev
)) {
185 msi_notify(pci_dev
, 0);
187 qemu_irq_raise(s
->irq
);
191 static void ahci_irq_lower(AHCIState
*s
)
193 DeviceState
*dev_state
= s
->container
;
194 PCIDevice
*pci_dev
= (PCIDevice
*) object_dynamic_cast(OBJECT(dev_state
),
197 trace_ahci_irq_lower(s
);
199 if (!pci_dev
|| !msi_enabled(pci_dev
)) {
200 qemu_irq_lower(s
->irq
);
204 static void ahci_check_irq(AHCIState
*s
)
207 uint32_t old_irq
= s
->control_regs
.irqstatus
;
209 s
->control_regs
.irqstatus
= 0;
210 for (i
= 0; i
< s
->ports
; i
++) {
211 AHCIPortRegs
*pr
= &s
->dev
[i
].port_regs
;
212 if (pr
->irq_stat
& pr
->irq_mask
) {
213 s
->control_regs
.irqstatus
|= (1 << i
);
216 trace_ahci_check_irq(s
, old_irq
, s
->control_regs
.irqstatus
);
217 if (s
->control_regs
.irqstatus
&&
218 (s
->control_regs
.ghc
& HOST_CTL_IRQ_EN
)) {
225 static void ahci_trigger_irq(AHCIState
*s
, AHCIDevice
*d
,
226 enum AHCIPortIRQ irqbit
)
228 g_assert((unsigned)irqbit
< 32);
229 uint32_t irq
= 1U << irqbit
;
230 uint32_t irqstat
= d
->port_regs
.irq_stat
| irq
;
232 trace_ahci_trigger_irq(s
, d
->port_no
,
233 AHCIPortIRQ_lookup
[irqbit
], irq
,
234 d
->port_regs
.irq_stat
, irqstat
,
235 irqstat
& d
->port_regs
.irq_mask
);
237 d
->port_regs
.irq_stat
= irqstat
;
241 static void map_page(AddressSpace
*as
, uint8_t **ptr
, uint64_t addr
,
247 dma_memory_unmap(as
, *ptr
, len
, DMA_DIRECTION_FROM_DEVICE
, len
);
250 *ptr
= dma_memory_map(as
, addr
, &len
, DMA_DIRECTION_FROM_DEVICE
);
252 dma_memory_unmap(as
, *ptr
, len
, DMA_DIRECTION_FROM_DEVICE
, len
);
258 * Check the cmd register to see if we should start or stop
259 * the DMA or FIS RX engines.
261 * @ad: Device to dis/engage.
263 * @return 0 on success, -1 on error.
265 static int ahci_cond_start_engines(AHCIDevice
*ad
)
267 AHCIPortRegs
*pr
= &ad
->port_regs
;
268 bool cmd_start
= pr
->cmd
& PORT_CMD_START
;
269 bool cmd_on
= pr
->cmd
& PORT_CMD_LIST_ON
;
270 bool fis_start
= pr
->cmd
& PORT_CMD_FIS_RX
;
271 bool fis_on
= pr
->cmd
& PORT_CMD_FIS_ON
;
273 if (cmd_start
&& !cmd_on
) {
274 if (!ahci_map_clb_address(ad
)) {
275 pr
->cmd
&= ~PORT_CMD_START
;
276 error_report("AHCI: Failed to start DMA engine: "
277 "bad command list buffer address");
280 } else if (!cmd_start
&& cmd_on
) {
281 ahci_unmap_clb_address(ad
);
284 if (fis_start
&& !fis_on
) {
285 if (!ahci_map_fis_address(ad
)) {
286 pr
->cmd
&= ~PORT_CMD_FIS_RX
;
287 error_report("AHCI: Failed to start FIS receive engine: "
288 "bad FIS receive buffer address");
291 } else if (!fis_start
&& fis_on
) {
292 ahci_unmap_fis_address(ad
);
298 static void ahci_port_write(AHCIState
*s
, int port
, int offset
, uint32_t val
)
300 AHCIPortRegs
*pr
= &s
->dev
[port
].port_regs
;
301 enum AHCIPortReg regnum
= offset
/ sizeof(uint32_t);
302 assert(regnum
< (AHCI_PORT_ADDR_OFFSET_LEN
/ sizeof(uint32_t)));
303 trace_ahci_port_write(s
, port
, AHCIPortReg_lookup
[regnum
], offset
, val
);
306 case AHCI_PORT_REG_LST_ADDR
:
309 case AHCI_PORT_REG_LST_ADDR_HI
:
310 pr
->lst_addr_hi
= val
;
312 case AHCI_PORT_REG_FIS_ADDR
:
315 case AHCI_PORT_REG_FIS_ADDR_HI
:
316 pr
->fis_addr_hi
= val
;
318 case AHCI_PORT_REG_IRQ_STAT
:
319 pr
->irq_stat
&= ~val
;
322 case AHCI_PORT_REG_IRQ_MASK
:
323 pr
->irq_mask
= val
& 0xfdc000ff;
326 case AHCI_PORT_REG_CMD
:
327 /* Block any Read-only fields from being set;
328 * including LIST_ON and FIS_ON.
329 * The spec requires to set ICC bits to zero after the ICC change
330 * is done. We don't support ICC state changes, therefore always
331 * force the ICC bits to zero.
333 pr
->cmd
= (pr
->cmd
& PORT_CMD_RO_MASK
) |
334 (val
& ~(PORT_CMD_RO_MASK
| PORT_CMD_ICC_MASK
));
336 /* Check FIS RX and CLB engines */
337 ahci_cond_start_engines(&s
->dev
[port
]);
339 /* XXX usually the FIS would be pending on the bus here and
340 issuing deferred until the OS enables FIS receival.
341 Instead, we only submit it once - which works in most
342 cases, but is a hack. */
343 if ((pr
->cmd
& PORT_CMD_FIS_ON
) &&
344 !s
->dev
[port
].init_d2h_sent
) {
345 ahci_init_d2h(&s
->dev
[port
]);
350 case AHCI_PORT_REG_TFDATA
:
351 case AHCI_PORT_REG_SIG
:
352 case AHCI_PORT_REG_SCR_STAT
:
355 case AHCI_PORT_REG_SCR_CTL
:
356 if (((pr
->scr_ctl
& AHCI_SCR_SCTL_DET
) == 1) &&
357 ((val
& AHCI_SCR_SCTL_DET
) == 0)) {
358 ahci_reset_port(s
, port
);
362 case AHCI_PORT_REG_SCR_ERR
:
365 case AHCI_PORT_REG_SCR_ACT
:
369 case AHCI_PORT_REG_CMD_ISSUE
:
370 pr
->cmd_issue
|= val
;
374 trace_ahci_port_write_unimpl(s
, port
, AHCIPortReg_lookup
[regnum
],
376 qemu_log_mask(LOG_UNIMP
, "Attempted write to unimplemented register: "
377 "AHCI port %d register %s, offset 0x%x: 0x%"PRIx32
,
378 port
, AHCIPortReg_lookup
[regnum
], offset
, val
);
383 static uint64_t ahci_mem_read_32(void *opaque
, hwaddr addr
)
385 AHCIState
*s
= opaque
;
388 if (addr
< AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR
) {
389 enum AHCIHostReg regnum
= addr
/ 4;
390 assert(regnum
< AHCI_HOST_REG__COUNT
);
393 case AHCI_HOST_REG_CAP
:
394 val
= s
->control_regs
.cap
;
396 case AHCI_HOST_REG_CTL
:
397 val
= s
->control_regs
.ghc
;
399 case AHCI_HOST_REG_IRQ_STAT
:
400 val
= s
->control_regs
.irqstatus
;
402 case AHCI_HOST_REG_PORTS_IMPL
:
403 val
= s
->control_regs
.impl
;
405 case AHCI_HOST_REG_VERSION
:
406 val
= s
->control_regs
.version
;
409 trace_ahci_mem_read_32_host_default(s
, AHCIHostReg_lookup
[regnum
],
412 trace_ahci_mem_read_32_host(s
, AHCIHostReg_lookup
[regnum
], addr
, val
);
413 } else if ((addr
>= AHCI_PORT_REGS_START_ADDR
) &&
414 (addr
< (AHCI_PORT_REGS_START_ADDR
+
415 (s
->ports
* AHCI_PORT_ADDR_OFFSET_LEN
)))) {
416 val
= ahci_port_read(s
, (addr
- AHCI_PORT_REGS_START_ADDR
) >> 7,
417 addr
& AHCI_PORT_ADDR_OFFSET_MASK
);
419 trace_ahci_mem_read_32_default(s
, addr
, val
);
422 trace_ahci_mem_read_32(s
, addr
, val
);
428 * AHCI 1.3 section 3 ("HBA Memory Registers")
429 * Support unaligned 8/16/32 bit reads, and 64 bit aligned reads.
430 * Caller is responsible for masking unwanted higher order bytes.
432 static uint64_t ahci_mem_read(void *opaque
, hwaddr addr
, unsigned size
)
434 hwaddr aligned
= addr
& ~0x3;
435 int ofst
= addr
- aligned
;
436 uint64_t lo
= ahci_mem_read_32(opaque
, aligned
);
440 /* if < 8 byte read does not cross 4 byte boundary */
441 if (ofst
+ size
<= 4) {
442 val
= lo
>> (ofst
* 8);
446 /* If the 64bit read is unaligned, we will produce undefined
447 * results. AHCI does not support unaligned 64bit reads. */
448 hi
= ahci_mem_read_32(opaque
, aligned
+ 4);
449 val
= (hi
<< 32 | lo
) >> (ofst
* 8);
452 trace_ahci_mem_read(opaque
, size
, addr
, val
);
457 static void ahci_mem_write(void *opaque
, hwaddr addr
,
458 uint64_t val
, unsigned size
)
460 AHCIState
*s
= opaque
;
462 trace_ahci_mem_write(s
, size
, addr
, val
);
464 /* Only aligned reads are allowed on AHCI */
466 fprintf(stderr
, "ahci: Mis-aligned write to addr 0x"
467 TARGET_FMT_plx
"\n", addr
);
471 if (addr
< AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR
) {
472 enum AHCIHostReg regnum
= addr
/ 4;
473 assert(regnum
< AHCI_HOST_REG__COUNT
);
476 case AHCI_HOST_REG_CAP
: /* R/WO, RO */
477 /* FIXME handle R/WO */
479 case AHCI_HOST_REG_CTL
: /* R/W */
480 if (val
& HOST_CTL_RESET
) {
483 s
->control_regs
.ghc
= (val
& 0x3) | HOST_CTL_AHCI_EN
;
487 case AHCI_HOST_REG_IRQ_STAT
: /* R/WC, RO */
488 s
->control_regs
.irqstatus
&= ~val
;
491 case AHCI_HOST_REG_PORTS_IMPL
: /* R/WO, RO */
492 /* FIXME handle R/WO */
494 case AHCI_HOST_REG_VERSION
: /* RO */
495 /* FIXME report write? */
498 qemu_log_mask(LOG_UNIMP
,
499 "Attempted write to unimplemented register: "
500 "AHCI host register %s, "
501 "offset 0x%"PRIx64
": 0x%"PRIx64
,
502 AHCIHostReg_lookup
[regnum
], addr
, val
);
503 trace_ahci_mem_write_host_unimpl(s
, size
,
504 AHCIHostReg_lookup
[regnum
], addr
);
506 trace_ahci_mem_write_host(s
, size
, AHCIHostReg_lookup
[regnum
],
508 } else if ((addr
>= AHCI_PORT_REGS_START_ADDR
) &&
509 (addr
< (AHCI_PORT_REGS_START_ADDR
+
510 (s
->ports
* AHCI_PORT_ADDR_OFFSET_LEN
)))) {
511 ahci_port_write(s
, (addr
- AHCI_PORT_REGS_START_ADDR
) >> 7,
512 addr
& AHCI_PORT_ADDR_OFFSET_MASK
, val
);
514 qemu_log_mask(LOG_UNIMP
, "Attempted write to unimplemented register: "
515 "AHCI global register at offset 0x%"PRIx64
": 0x%"PRIx64
,
517 trace_ahci_mem_write_unimpl(s
, size
, addr
, val
);
521 static const MemoryRegionOps ahci_mem_ops
= {
522 .read
= ahci_mem_read
,
523 .write
= ahci_mem_write
,
524 .endianness
= DEVICE_LITTLE_ENDIAN
,
527 static uint64_t ahci_idp_read(void *opaque
, hwaddr addr
,
530 AHCIState
*s
= opaque
;
532 if (addr
== s
->idp_offset
) {
535 } else if (addr
== s
->idp_offset
+ 4) {
536 /* data register - do memory read at location selected by index */
537 return ahci_mem_read(opaque
, s
->idp_index
, size
);
543 static void ahci_idp_write(void *opaque
, hwaddr addr
,
544 uint64_t val
, unsigned size
)
546 AHCIState
*s
= opaque
;
548 if (addr
== s
->idp_offset
) {
549 /* index register - mask off reserved bits */
550 s
->idp_index
= (uint32_t)val
& ((AHCI_MEM_BAR_SIZE
- 1) & ~3);
551 } else if (addr
== s
->idp_offset
+ 4) {
552 /* data register - do memory write at location selected by index */
553 ahci_mem_write(opaque
, s
->idp_index
, val
, size
);
557 static const MemoryRegionOps ahci_idp_ops
= {
558 .read
= ahci_idp_read
,
559 .write
= ahci_idp_write
,
560 .endianness
= DEVICE_LITTLE_ENDIAN
,
564 static void ahci_reg_init(AHCIState
*s
)
568 s
->control_regs
.cap
= (s
->ports
- 1) |
569 (AHCI_NUM_COMMAND_SLOTS
<< 8) |
570 (AHCI_SUPPORTED_SPEED_GEN1
<< AHCI_SUPPORTED_SPEED
) |
571 HOST_CAP_NCQ
| HOST_CAP_AHCI
| HOST_CAP_64
;
573 s
->control_regs
.impl
= (1 << s
->ports
) - 1;
575 s
->control_regs
.version
= AHCI_VERSION_1_0
;
577 for (i
= 0; i
< s
->ports
; i
++) {
578 s
->dev
[i
].port_state
= STATE_RUN
;
582 static void check_cmd(AHCIState
*s
, int port
)
584 AHCIPortRegs
*pr
= &s
->dev
[port
].port_regs
;
587 if ((pr
->cmd
& PORT_CMD_START
) && pr
->cmd_issue
) {
588 for (slot
= 0; (slot
< 32) && pr
->cmd_issue
; slot
++) {
589 if ((pr
->cmd_issue
& (1U << slot
)) &&
590 !handle_cmd(s
, port
, slot
)) {
591 pr
->cmd_issue
&= ~(1U << slot
);
597 static void ahci_check_cmd_bh(void *opaque
)
599 AHCIDevice
*ad
= opaque
;
601 qemu_bh_delete(ad
->check_bh
);
604 check_cmd(ad
->hba
, ad
->port_no
);
607 static void ahci_init_d2h(AHCIDevice
*ad
)
609 IDEState
*ide_state
= &ad
->port
.ifs
[0];
610 AHCIPortRegs
*pr
= &ad
->port_regs
;
612 if (ad
->init_d2h_sent
) {
616 if (ahci_write_fis_d2h(ad
)) {
617 ad
->init_d2h_sent
= true;
618 /* We're emulating receiving the first Reg H2D Fis from the device;
619 * Update the SIG register, but otherwise proceed as normal. */
620 pr
->sig
= ((uint32_t)ide_state
->hcyl
<< 24) |
621 (ide_state
->lcyl
<< 16) |
622 (ide_state
->sector
<< 8) |
623 (ide_state
->nsector
& 0xFF);
627 static void ahci_set_signature(AHCIDevice
*ad
, uint32_t sig
)
629 IDEState
*s
= &ad
->port
.ifs
[0];
630 s
->hcyl
= sig
>> 24 & 0xFF;
631 s
->lcyl
= sig
>> 16 & 0xFF;
632 s
->sector
= sig
>> 8 & 0xFF;
633 s
->nsector
= sig
& 0xFF;
635 trace_ahci_set_signature(ad
->hba
, ad
->port_no
, s
->nsector
, s
->sector
,
636 s
->lcyl
, s
->hcyl
, sig
);
639 static void ahci_reset_port(AHCIState
*s
, int port
)
641 AHCIDevice
*d
= &s
->dev
[port
];
642 AHCIPortRegs
*pr
= &d
->port_regs
;
643 IDEState
*ide_state
= &d
->port
.ifs
[0];
646 trace_ahci_reset_port(s
, port
);
648 ide_bus_reset(&d
->port
);
649 ide_state
->ncq_queues
= AHCI_MAX_CMDS
;
655 pr
->sig
= 0xFFFFFFFF;
657 d
->init_d2h_sent
= false;
659 ide_state
= &s
->dev
[port
].port
.ifs
[0];
660 if (!ide_state
->blk
) {
664 /* reset ncq queue */
665 for (i
= 0; i
< AHCI_MAX_CMDS
; i
++) {
666 NCQTransferState
*ncq_tfs
= &s
->dev
[port
].ncq_tfs
[i
];
667 ncq_tfs
->halt
= false;
668 if (!ncq_tfs
->used
) {
672 if (ncq_tfs
->aiocb
) {
673 blk_aio_cancel(ncq_tfs
->aiocb
);
674 ncq_tfs
->aiocb
= NULL
;
677 /* Maybe we just finished the request thanks to blk_aio_cancel() */
678 if (!ncq_tfs
->used
) {
682 qemu_sglist_destroy(&ncq_tfs
->sglist
);
686 s
->dev
[port
].port_state
= STATE_RUN
;
687 if (ide_state
->drive_kind
== IDE_CD
) {
688 ahci_set_signature(d
, SATA_SIGNATURE_CDROM
);\
689 ide_state
->status
= SEEK_STAT
| WRERR_STAT
| READY_STAT
;
691 ahci_set_signature(d
, SATA_SIGNATURE_DISK
);
692 ide_state
->status
= SEEK_STAT
| WRERR_STAT
;
695 ide_state
->error
= 1;
699 /* Buffer pretty output based on a raw FIS structure. */
700 static char *ahci_pretty_buffer_fis(uint8_t *fis
, int cmd_len
)
703 GString
*s
= g_string_new("FIS:");
705 for (i
= 0; i
< cmd_len
; i
++) {
706 if ((i
& 0xf) == 0) {
707 g_string_append_printf(s
, "\n0x%02x: ", i
);
709 g_string_append_printf(s
, "%02x ", fis
[i
]);
711 g_string_append_c(s
, '\n');
713 return g_string_free(s
, FALSE
);
716 static bool ahci_map_fis_address(AHCIDevice
*ad
)
718 AHCIPortRegs
*pr
= &ad
->port_regs
;
719 map_page(ad
->hba
->as
, &ad
->res_fis
,
720 ((uint64_t)pr
->fis_addr_hi
<< 32) | pr
->fis_addr
, 256);
721 if (ad
->res_fis
!= NULL
) {
722 pr
->cmd
|= PORT_CMD_FIS_ON
;
726 pr
->cmd
&= ~PORT_CMD_FIS_ON
;
730 static void ahci_unmap_fis_address(AHCIDevice
*ad
)
732 if (ad
->res_fis
== NULL
) {
733 trace_ahci_unmap_fis_address_null(ad
->hba
, ad
->port_no
);
736 ad
->port_regs
.cmd
&= ~PORT_CMD_FIS_ON
;
737 dma_memory_unmap(ad
->hba
->as
, ad
->res_fis
, 256,
738 DMA_DIRECTION_FROM_DEVICE
, 256);
742 static bool ahci_map_clb_address(AHCIDevice
*ad
)
744 AHCIPortRegs
*pr
= &ad
->port_regs
;
746 map_page(ad
->hba
->as
, &ad
->lst
,
747 ((uint64_t)pr
->lst_addr_hi
<< 32) | pr
->lst_addr
, 1024);
748 if (ad
->lst
!= NULL
) {
749 pr
->cmd
|= PORT_CMD_LIST_ON
;
753 pr
->cmd
&= ~PORT_CMD_LIST_ON
;
757 static void ahci_unmap_clb_address(AHCIDevice
*ad
)
759 if (ad
->lst
== NULL
) {
760 trace_ahci_unmap_clb_address_null(ad
->hba
, ad
->port_no
);
763 ad
->port_regs
.cmd
&= ~PORT_CMD_LIST_ON
;
764 dma_memory_unmap(ad
->hba
->as
, ad
->lst
, 1024,
765 DMA_DIRECTION_FROM_DEVICE
, 1024);
769 static void ahci_write_fis_sdb(AHCIState
*s
, NCQTransferState
*ncq_tfs
)
771 AHCIDevice
*ad
= ncq_tfs
->drive
;
772 AHCIPortRegs
*pr
= &ad
->port_regs
;
777 !(pr
->cmd
& PORT_CMD_FIS_RX
)) {
781 sdb_fis
= (SDBFIS
*)&ad
->res_fis
[RES_FIS_SDBFIS
];
782 ide_state
= &ad
->port
.ifs
[0];
784 sdb_fis
->type
= SATA_FIS_TYPE_SDB
;
785 /* Interrupt pending & Notification bit */
786 sdb_fis
->flags
= 0x40; /* Interrupt bit, always 1 for NCQ */
787 sdb_fis
->status
= ide_state
->status
& 0x77;
788 sdb_fis
->error
= ide_state
->error
;
789 /* update SAct field in SDB_FIS */
790 sdb_fis
->payload
= cpu_to_le32(ad
->finished
);
792 /* Update shadow registers (except BSY 0x80 and DRQ 0x08) */
793 pr
->tfdata
= (ad
->port
.ifs
[0].error
<< 8) |
794 (ad
->port
.ifs
[0].status
& 0x77) |
796 pr
->scr_act
&= ~ad
->finished
;
799 /* Trigger IRQ if interrupt bit is set (which currently, it always is) */
800 if (sdb_fis
->flags
& 0x40) {
801 ahci_trigger_irq(s
, ad
, AHCI_PORT_IRQ_BIT_SDBS
);
805 static void ahci_write_fis_pio(AHCIDevice
*ad
, uint16_t len
, bool pio_fis_i
)
807 AHCIPortRegs
*pr
= &ad
->port_regs
;
809 IDEState
*s
= &ad
->port
.ifs
[0];
811 if (!ad
->res_fis
|| !(pr
->cmd
& PORT_CMD_FIS_RX
)) {
815 pio_fis
= &ad
->res_fis
[RES_FIS_PSFIS
];
817 pio_fis
[0] = SATA_FIS_TYPE_PIO_SETUP
;
818 pio_fis
[1] = (pio_fis_i
? (1 << 6) : 0);
819 pio_fis
[2] = s
->status
;
820 pio_fis
[3] = s
->error
;
822 pio_fis
[4] = s
->sector
;
823 pio_fis
[5] = s
->lcyl
;
824 pio_fis
[6] = s
->hcyl
;
825 pio_fis
[7] = s
->select
;
826 pio_fis
[8] = s
->hob_sector
;
827 pio_fis
[9] = s
->hob_lcyl
;
828 pio_fis
[10] = s
->hob_hcyl
;
830 pio_fis
[12] = s
->nsector
& 0xFF;
831 pio_fis
[13] = (s
->nsector
>> 8) & 0xFF;
833 pio_fis
[15] = s
->status
;
834 pio_fis
[16] = len
& 255;
835 pio_fis
[17] = len
>> 8;
839 /* Update shadow registers: */
840 pr
->tfdata
= (ad
->port
.ifs
[0].error
<< 8) |
841 ad
->port
.ifs
[0].status
;
843 if (pio_fis
[2] & ERR_STAT
) {
844 ahci_trigger_irq(ad
->hba
, ad
, AHCI_PORT_IRQ_BIT_TFES
);
848 static bool ahci_write_fis_d2h(AHCIDevice
*ad
)
850 AHCIPortRegs
*pr
= &ad
->port_regs
;
853 IDEState
*s
= &ad
->port
.ifs
[0];
855 if (!ad
->res_fis
|| !(pr
->cmd
& PORT_CMD_FIS_RX
)) {
859 d2h_fis
= &ad
->res_fis
[RES_FIS_RFIS
];
861 d2h_fis
[0] = SATA_FIS_TYPE_REGISTER_D2H
;
862 d2h_fis
[1] = (1 << 6); /* interrupt bit */
863 d2h_fis
[2] = s
->status
;
864 d2h_fis
[3] = s
->error
;
866 d2h_fis
[4] = s
->sector
;
867 d2h_fis
[5] = s
->lcyl
;
868 d2h_fis
[6] = s
->hcyl
;
869 d2h_fis
[7] = s
->select
;
870 d2h_fis
[8] = s
->hob_sector
;
871 d2h_fis
[9] = s
->hob_lcyl
;
872 d2h_fis
[10] = s
->hob_hcyl
;
874 d2h_fis
[12] = s
->nsector
& 0xFF;
875 d2h_fis
[13] = (s
->nsector
>> 8) & 0xFF;
876 for (i
= 14; i
< 20; i
++) {
880 /* Update shadow registers: */
881 pr
->tfdata
= (ad
->port
.ifs
[0].error
<< 8) |
882 ad
->port
.ifs
[0].status
;
884 if (d2h_fis
[2] & ERR_STAT
) {
885 ahci_trigger_irq(ad
->hba
, ad
, AHCI_PORT_IRQ_BIT_TFES
);
888 ahci_trigger_irq(ad
->hba
, ad
, AHCI_PORT_IRQ_BIT_DHRS
);
892 static int prdt_tbl_entry_size(const AHCI_SG
*tbl
)
894 /* flags_size is zero-based */
895 return (le32_to_cpu(tbl
->flags_size
) & AHCI_PRDT_SIZE_MASK
) + 1;
899 * Fetch entries in a guest-provided PRDT and convert it into a QEMU SGlist.
900 * @ad: The AHCIDevice for whom we are building the SGList.
901 * @sglist: The SGList target to add PRD entries to.
902 * @cmd: The AHCI Command Header that describes where the PRDT is.
903 * @limit: The remaining size of the S/ATA transaction, in bytes.
904 * @offset: The number of bytes already transferred, in bytes.
906 * The AHCI PRDT can describe up to 256GiB. S/ATA only support transactions of
907 * up to 32MiB as of ATA8-ACS3 rev 1b, assuming a 512 byte sector size. We stop
908 * building the sglist from the PRDT as soon as we hit @limit bytes,
909 * which is <= INT32_MAX/2GiB.
911 static int ahci_populate_sglist(AHCIDevice
*ad
, QEMUSGList
*sglist
,
912 AHCICmdHdr
*cmd
, int64_t limit
, uint64_t offset
)
914 uint16_t opts
= le16_to_cpu(cmd
->opts
);
915 uint16_t prdtl
= le16_to_cpu(cmd
->prdtl
);
916 uint64_t cfis_addr
= le64_to_cpu(cmd
->tbl_addr
);
917 uint64_t prdt_addr
= cfis_addr
+ 0x80;
918 dma_addr_t prdt_len
= (prdtl
* sizeof(AHCI_SG
));
919 dma_addr_t real_prdt_len
= prdt_len
;
925 int64_t off_pos
= -1;
927 IDEBus
*bus
= &ad
->port
;
928 BusState
*qbus
= BUS(bus
);
930 trace_ahci_populate_sglist(ad
->hba
, ad
->port_no
);
933 trace_ahci_populate_sglist_no_prdtl(ad
->hba
, ad
->port_no
, opts
);
938 if (!(prdt
= dma_memory_map(ad
->hba
->as
, prdt_addr
, &prdt_len
,
939 DMA_DIRECTION_TO_DEVICE
))){
940 trace_ahci_populate_sglist_no_map(ad
->hba
, ad
->port_no
);
944 if (prdt_len
< real_prdt_len
) {
945 trace_ahci_populate_sglist_short_map(ad
->hba
, ad
->port_no
);
950 /* Get entries in the PRDT, init a qemu sglist accordingly */
952 AHCI_SG
*tbl
= (AHCI_SG
*)prdt
;
954 for (i
= 0; i
< prdtl
; i
++) {
955 tbl_entry_size
= prdt_tbl_entry_size(&tbl
[i
]);
956 if (offset
< (sum
+ tbl_entry_size
)) {
958 off_pos
= offset
- sum
;
961 sum
+= tbl_entry_size
;
963 if ((off_idx
== -1) || (off_pos
< 0) || (off_pos
> tbl_entry_size
)) {
964 trace_ahci_populate_sglist_bad_offset(ad
->hba
, ad
->port_no
,
970 qemu_sglist_init(sglist
, qbus
->parent
, (prdtl
- off_idx
),
972 qemu_sglist_add(sglist
, le64_to_cpu(tbl
[off_idx
].addr
) + off_pos
,
973 MIN(prdt_tbl_entry_size(&tbl
[off_idx
]) - off_pos
,
976 for (i
= off_idx
+ 1; i
< prdtl
&& sglist
->size
< limit
; i
++) {
977 qemu_sglist_add(sglist
, le64_to_cpu(tbl
[i
].addr
),
978 MIN(prdt_tbl_entry_size(&tbl
[i
]),
979 limit
- sglist
->size
));
984 dma_memory_unmap(ad
->hba
->as
, prdt
, prdt_len
,
985 DMA_DIRECTION_TO_DEVICE
, prdt_len
);
989 static void ncq_err(NCQTransferState
*ncq_tfs
)
991 IDEState
*ide_state
= &ncq_tfs
->drive
->port
.ifs
[0];
993 ide_state
->error
= ABRT_ERR
;
994 ide_state
->status
= READY_STAT
| ERR_STAT
;
995 ncq_tfs
->drive
->port_regs
.scr_err
|= (1 << ncq_tfs
->tag
);
996 qemu_sglist_destroy(&ncq_tfs
->sglist
);
1000 static void ncq_finish(NCQTransferState
*ncq_tfs
)
1002 /* If we didn't error out, set our finished bit. Errored commands
1003 * do not get a bit set for the SDB FIS ACT register, nor do they
1004 * clear the outstanding bit in scr_act (PxSACT). */
1005 if (!(ncq_tfs
->drive
->port_regs
.scr_err
& (1 << ncq_tfs
->tag
))) {
1006 ncq_tfs
->drive
->finished
|= (1 << ncq_tfs
->tag
);
1009 ahci_write_fis_sdb(ncq_tfs
->drive
->hba
, ncq_tfs
);
1011 trace_ncq_finish(ncq_tfs
->drive
->hba
, ncq_tfs
->drive
->port_no
,
1014 block_acct_done(blk_get_stats(ncq_tfs
->drive
->port
.ifs
[0].blk
),
1016 qemu_sglist_destroy(&ncq_tfs
->sglist
);
1020 static void ncq_cb(void *opaque
, int ret
)
1022 NCQTransferState
*ncq_tfs
= (NCQTransferState
*)opaque
;
1023 IDEState
*ide_state
= &ncq_tfs
->drive
->port
.ifs
[0];
1025 ncq_tfs
->aiocb
= NULL
;
1026 if (ret
== -ECANCELED
) {
1031 bool is_read
= ncq_tfs
->cmd
== READ_FPDMA_QUEUED
;
1032 BlockErrorAction action
= blk_get_error_action(ide_state
->blk
,
1034 if (action
== BLOCK_ERROR_ACTION_STOP
) {
1035 ncq_tfs
->halt
= true;
1036 ide_state
->bus
->error_status
= IDE_RETRY_HBA
;
1037 } else if (action
== BLOCK_ERROR_ACTION_REPORT
) {
1040 blk_error_action(ide_state
->blk
, action
, is_read
, -ret
);
1042 ide_state
->status
= READY_STAT
| SEEK_STAT
;
1045 if (!ncq_tfs
->halt
) {
1046 ncq_finish(ncq_tfs
);
1050 static int is_ncq(uint8_t ata_cmd
)
1052 /* Based on SATA 3.2 section 13.6.3.2 */
1054 case READ_FPDMA_QUEUED
:
1055 case WRITE_FPDMA_QUEUED
:
1057 case RECEIVE_FPDMA_QUEUED
:
1058 case SEND_FPDMA_QUEUED
:
1065 static void execute_ncq_command(NCQTransferState
*ncq_tfs
)
1067 AHCIDevice
*ad
= ncq_tfs
->drive
;
1068 IDEState
*ide_state
= &ad
->port
.ifs
[0];
1069 int port
= ad
->port_no
;
1071 g_assert(is_ncq(ncq_tfs
->cmd
));
1072 ncq_tfs
->halt
= false;
1074 switch (ncq_tfs
->cmd
) {
1075 case READ_FPDMA_QUEUED
:
1076 trace_execute_ncq_command_read(ad
->hba
, port
, ncq_tfs
->tag
,
1077 ncq_tfs
->sector_count
, ncq_tfs
->lba
);
1078 dma_acct_start(ide_state
->blk
, &ncq_tfs
->acct
,
1079 &ncq_tfs
->sglist
, BLOCK_ACCT_READ
);
1080 ncq_tfs
->aiocb
= dma_blk_read(ide_state
->blk
, &ncq_tfs
->sglist
,
1081 ncq_tfs
->lba
<< BDRV_SECTOR_BITS
,
1085 case WRITE_FPDMA_QUEUED
:
1086 trace_execute_ncq_command_read(ad
->hba
, port
, ncq_tfs
->tag
,
1087 ncq_tfs
->sector_count
, ncq_tfs
->lba
);
1088 dma_acct_start(ide_state
->blk
, &ncq_tfs
->acct
,
1089 &ncq_tfs
->sglist
, BLOCK_ACCT_WRITE
);
1090 ncq_tfs
->aiocb
= dma_blk_write(ide_state
->blk
, &ncq_tfs
->sglist
,
1091 ncq_tfs
->lba
<< BDRV_SECTOR_BITS
,
1096 trace_execute_ncq_command_unsup(ad
->hba
, port
,
1097 ncq_tfs
->tag
, ncq_tfs
->cmd
);
1103 static void process_ncq_command(AHCIState
*s
, int port
, uint8_t *cmd_fis
,
1106 AHCIDevice
*ad
= &s
->dev
[port
];
1107 NCQFrame
*ncq_fis
= (NCQFrame
*)cmd_fis
;
1108 uint8_t tag
= ncq_fis
->tag
>> 3;
1109 NCQTransferState
*ncq_tfs
= &ad
->ncq_tfs
[tag
];
1112 g_assert(is_ncq(ncq_fis
->command
));
1113 if (ncq_tfs
->used
) {
1114 /* error - already in use */
1115 fprintf(stderr
, "%s: tag %d already used\n", __func__
, tag
);
1120 ncq_tfs
->drive
= ad
;
1121 ncq_tfs
->slot
= slot
;
1122 ncq_tfs
->cmdh
= &((AHCICmdHdr
*)ad
->lst
)[slot
];
1123 ncq_tfs
->cmd
= ncq_fis
->command
;
1124 ncq_tfs
->lba
= ((uint64_t)ncq_fis
->lba5
<< 40) |
1125 ((uint64_t)ncq_fis
->lba4
<< 32) |
1126 ((uint64_t)ncq_fis
->lba3
<< 24) |
1127 ((uint64_t)ncq_fis
->lba2
<< 16) |
1128 ((uint64_t)ncq_fis
->lba1
<< 8) |
1129 (uint64_t)ncq_fis
->lba0
;
1132 /* Sanity-check the NCQ packet */
1134 trace_process_ncq_command_mismatch(s
, port
, tag
, slot
);
1137 if (ncq_fis
->aux0
|| ncq_fis
->aux1
|| ncq_fis
->aux2
|| ncq_fis
->aux3
) {
1138 trace_process_ncq_command_aux(s
, port
, tag
);
1140 if (ncq_fis
->prio
|| ncq_fis
->icc
) {
1141 trace_process_ncq_command_prioicc(s
, port
, tag
);
1143 if (ncq_fis
->fua
& NCQ_FIS_FUA_MASK
) {
1144 trace_process_ncq_command_fua(s
, port
, tag
);
1146 if (ncq_fis
->tag
& NCQ_FIS_RARC_MASK
) {
1147 trace_process_ncq_command_rarc(s
, port
, tag
);
1150 ncq_tfs
->sector_count
= ((ncq_fis
->sector_count_high
<< 8) |
1151 ncq_fis
->sector_count_low
);
1152 if (!ncq_tfs
->sector_count
) {
1153 ncq_tfs
->sector_count
= 0x10000;
1155 size
= ncq_tfs
->sector_count
* 512;
1156 ahci_populate_sglist(ad
, &ncq_tfs
->sglist
, ncq_tfs
->cmdh
, size
, 0);
1158 if (ncq_tfs
->sglist
.size
< size
) {
1159 error_report("ahci: PRDT length for NCQ command (0x%zx) "
1160 "is smaller than the requested size (0x%zx)",
1161 ncq_tfs
->sglist
.size
, size
);
1163 ahci_trigger_irq(ad
->hba
, ad
, AHCI_PORT_IRQ_BIT_OFS
);
1165 } else if (ncq_tfs
->sglist
.size
!= size
) {
1166 trace_process_ncq_command_large(s
, port
, tag
,
1167 ncq_tfs
->sglist
.size
, size
);
1170 trace_process_ncq_command(s
, port
, tag
,
1173 ncq_tfs
->lba
+ ncq_tfs
->sector_count
- 1);
1174 execute_ncq_command(ncq_tfs
);
1177 static AHCICmdHdr
*get_cmd_header(AHCIState
*s
, uint8_t port
, uint8_t slot
)
1179 if (port
>= s
->ports
|| slot
>= AHCI_MAX_CMDS
) {
1183 return s
->dev
[port
].lst
? &((AHCICmdHdr
*)s
->dev
[port
].lst
)[slot
] : NULL
;
1186 static void handle_reg_h2d_fis(AHCIState
*s
, int port
,
1187 uint8_t slot
, uint8_t *cmd_fis
)
1189 IDEState
*ide_state
= &s
->dev
[port
].port
.ifs
[0];
1190 AHCICmdHdr
*cmd
= get_cmd_header(s
, port
, slot
);
1191 uint16_t opts
= le16_to_cpu(cmd
->opts
);
1193 if (cmd_fis
[1] & 0x0F) {
1194 trace_handle_reg_h2d_fis_pmp(s
, port
, cmd_fis
[1],
1195 cmd_fis
[2], cmd_fis
[3]);
1199 if (cmd_fis
[1] & 0x70) {
1200 trace_handle_reg_h2d_fis_res(s
, port
, cmd_fis
[1],
1201 cmd_fis
[2], cmd_fis
[3]);
1205 if (!(cmd_fis
[1] & SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER
)) {
1206 switch (s
->dev
[port
].port_state
) {
1208 if (cmd_fis
[15] & ATA_SRST
) {
1209 s
->dev
[port
].port_state
= STATE_RESET
;
1213 if (!(cmd_fis
[15] & ATA_SRST
)) {
1214 ahci_reset_port(s
, port
);
1221 /* Check for NCQ command */
1222 if (is_ncq(cmd_fis
[2])) {
1223 process_ncq_command(s
, port
, cmd_fis
, slot
);
1227 /* Decompose the FIS:
1228 * AHCI does not interpret FIS packets, it only forwards them.
1229 * SATA 1.0 describes how to decode LBA28 and CHS FIS packets.
1230 * Later specifications, e.g, SATA 3.2, describe LBA48 FIS packets.
1232 * ATA4 describes sector number for LBA28/CHS commands.
1233 * ATA6 describes sector number for LBA48 commands.
1234 * ATA8 deprecates CHS fully, describing only LBA28/48.
1236 * We dutifully convert the FIS into IDE registers, and allow the
1237 * core layer to interpret them as needed. */
1238 ide_state
->feature
= cmd_fis
[3];
1239 ide_state
->sector
= cmd_fis
[4]; /* LBA 7:0 */
1240 ide_state
->lcyl
= cmd_fis
[5]; /* LBA 15:8 */
1241 ide_state
->hcyl
= cmd_fis
[6]; /* LBA 23:16 */
1242 ide_state
->select
= cmd_fis
[7]; /* LBA 27:24 (LBA28) */
1243 ide_state
->hob_sector
= cmd_fis
[8]; /* LBA 31:24 */
1244 ide_state
->hob_lcyl
= cmd_fis
[9]; /* LBA 39:32 */
1245 ide_state
->hob_hcyl
= cmd_fis
[10]; /* LBA 47:40 */
1246 ide_state
->hob_feature
= cmd_fis
[11];
1247 ide_state
->nsector
= (int64_t)((cmd_fis
[13] << 8) | cmd_fis
[12]);
1248 /* 14, 16, 17, 18, 19: Reserved (SATA 1.0) */
1249 /* 15: Only valid when UPDATE_COMMAND not set. */
1251 /* Copy the ACMD field (ATAPI packet, if any) from the AHCI command
1252 * table to ide_state->io_buffer */
1253 if (opts
& AHCI_CMD_ATAPI
) {
1254 memcpy(ide_state
->io_buffer
, &cmd_fis
[AHCI_COMMAND_TABLE_ACMD
], 0x10);
1255 if (trace_event_get_state_backends(TRACE_HANDLE_REG_H2D_FIS_DUMP
)) {
1256 char *pretty_fis
= ahci_pretty_buffer_fis(ide_state
->io_buffer
, 0x10);
1257 trace_handle_reg_h2d_fis_dump(s
, port
, pretty_fis
);
1262 ide_state
->error
= 0;
1263 s
->dev
[port
].done_first_drq
= false;
1264 /* Reset transferred byte counter */
1267 /* We're ready to process the command in FIS byte 2. */
1268 ide_exec_cmd(&s
->dev
[port
].port
, cmd_fis
[2]);
1271 static int handle_cmd(AHCIState
*s
, int port
, uint8_t slot
)
1273 IDEState
*ide_state
;
1279 if (s
->dev
[port
].port
.ifs
[0].status
& (BUSY_STAT
|DRQ_STAT
)) {
1280 /* Engine currently busy, try again later */
1281 trace_handle_cmd_busy(s
, port
);
1285 if (!s
->dev
[port
].lst
) {
1286 trace_handle_cmd_nolist(s
, port
);
1289 cmd
= get_cmd_header(s
, port
, slot
);
1290 /* remember current slot handle for later */
1291 s
->dev
[port
].cur_cmd
= cmd
;
1293 /* The device we are working for */
1294 ide_state
= &s
->dev
[port
].port
.ifs
[0];
1295 if (!ide_state
->blk
) {
1296 trace_handle_cmd_badport(s
, port
);
1300 tbl_addr
= le64_to_cpu(cmd
->tbl_addr
);
1302 cmd_fis
= dma_memory_map(s
->as
, tbl_addr
, &cmd_len
,
1303 DMA_DIRECTION_FROM_DEVICE
);
1305 trace_handle_cmd_badfis(s
, port
);
1307 } else if (cmd_len
!= 0x80) {
1308 ahci_trigger_irq(s
, &s
->dev
[port
], AHCI_PORT_IRQ_BIT_HBFS
);
1309 trace_handle_cmd_badmap(s
, port
, cmd_len
);
1312 if (trace_event_get_state_backends(TRACE_HANDLE_CMD_FIS_DUMP
)) {
1313 char *pretty_fis
= ahci_pretty_buffer_fis(cmd_fis
, 0x80);
1314 trace_handle_cmd_fis_dump(s
, port
, pretty_fis
);
1317 switch (cmd_fis
[0]) {
1318 case SATA_FIS_TYPE_REGISTER_H2D
:
1319 handle_reg_h2d_fis(s
, port
, slot
, cmd_fis
);
1322 trace_handle_cmd_unhandled_fis(s
, port
,
1323 cmd_fis
[0], cmd_fis
[1], cmd_fis
[2]);
1328 dma_memory_unmap(s
->as
, cmd_fis
, cmd_len
, DMA_DIRECTION_FROM_DEVICE
,
1331 if (s
->dev
[port
].port
.ifs
[0].status
& (BUSY_STAT
|DRQ_STAT
)) {
1332 /* async command, complete later */
1333 s
->dev
[port
].busy_slot
= slot
;
1337 /* done handling the command */
1341 /* Transfer PIO data between RAM and device */
1342 static void ahci_pio_transfer(IDEDMA
*dma
)
1344 AHCIDevice
*ad
= DO_UPCAST(AHCIDevice
, dma
, dma
);
1345 IDEState
*s
= &ad
->port
.ifs
[0];
1346 uint32_t size
= (uint32_t)(s
->data_end
- s
->data_ptr
);
1347 /* write == ram -> device */
1348 uint16_t opts
= le16_to_cpu(ad
->cur_cmd
->opts
);
1349 int is_write
= opts
& AHCI_CMD_WRITE
;
1350 int is_atapi
= opts
& AHCI_CMD_ATAPI
;
1354 /* The PIO Setup FIS is received prior to transfer, but the interrupt
1355 * is only triggered after data is received.
1357 * The device only sets the 'I' bit in the PIO Setup FIS for device->host
1358 * requests (see "DPIOI1" in the SATA spec), or for host->device DRQs after
1359 * the first (see "DPIOO1"). The latter is consistent with the spec's
1360 * description of the PACKET protocol, where the command part of ATAPI requests
1361 * ("DPKT0") has the 'I' bit clear, while the data part of PIO ATAPI requests
1362 * ("DPKT4a" and "DPKT7") has the 'I' bit set for both directions for all DRQs.
1364 pio_fis_i
= ad
->done_first_drq
|| (!is_atapi
&& !is_write
);
1365 ahci_write_fis_pio(ad
, size
, pio_fis_i
);
1367 if (is_atapi
&& !ad
->done_first_drq
) {
1368 /* already prepopulated iobuffer */
1372 if (ahci_dma_prepare_buf(dma
, size
)) {
1376 trace_ahci_pio_transfer(ad
->hba
, ad
->port_no
, is_write
? "writ" : "read",
1377 size
, is_atapi
? "atapi" : "ata",
1378 has_sglist
? "" : "o");
1380 if (has_sglist
&& size
) {
1382 dma_buf_write(s
->data_ptr
, size
, &s
->sg
);
1384 dma_buf_read(s
->data_ptr
, size
, &s
->sg
);
1388 /* Update number of transferred bytes, destroy sglist */
1389 dma_buf_commit(s
, size
);
1392 /* declare that we processed everything */
1393 s
->data_ptr
= s
->data_end
;
1395 ad
->done_first_drq
= true;
1397 ahci_trigger_irq(ad
->hba
, ad
, AHCI_PORT_IRQ_BIT_PSS
);
1401 static void ahci_start_dma(IDEDMA
*dma
, IDEState
*s
,
1402 BlockCompletionFunc
*dma_cb
)
1404 AHCIDevice
*ad
= DO_UPCAST(AHCIDevice
, dma
, dma
);
1405 trace_ahci_start_dma(ad
->hba
, ad
->port_no
);
1406 s
->io_buffer_offset
= 0;
1410 static void ahci_restart_dma(IDEDMA
*dma
)
1412 /* Nothing to do, ahci_start_dma already resets s->io_buffer_offset. */
1416 * IDE/PIO restarts are handled by the core layer, but NCQ commands
1417 * need an extra kick from the AHCI HBA.
1419 static void ahci_restart(IDEDMA
*dma
)
1421 AHCIDevice
*ad
= DO_UPCAST(AHCIDevice
, dma
, dma
);
1424 for (i
= 0; i
< AHCI_MAX_CMDS
; i
++) {
1425 NCQTransferState
*ncq_tfs
= &ad
->ncq_tfs
[i
];
1426 if (ncq_tfs
->halt
) {
1427 execute_ncq_command(ncq_tfs
);
1433 * Called in DMA and PIO R/W chains to read the PRDT.
1434 * Not shared with NCQ pathways.
1436 static int32_t ahci_dma_prepare_buf(IDEDMA
*dma
, int32_t limit
)
1438 AHCIDevice
*ad
= DO_UPCAST(AHCIDevice
, dma
, dma
);
1439 IDEState
*s
= &ad
->port
.ifs
[0];
1441 if (ahci_populate_sglist(ad
, &s
->sg
, ad
->cur_cmd
,
1442 limit
, s
->io_buffer_offset
) == -1) {
1443 trace_ahci_dma_prepare_buf_fail(ad
->hba
, ad
->port_no
);
1446 s
->io_buffer_size
= s
->sg
.size
;
1448 trace_ahci_dma_prepare_buf(ad
->hba
, ad
->port_no
, limit
, s
->io_buffer_size
);
1449 return s
->io_buffer_size
;
1453 * Updates the command header with a bytes-read value.
1454 * Called via dma_buf_commit, for both DMA and PIO paths.
1455 * sglist destruction is handled within dma_buf_commit.
1457 static void ahci_commit_buf(IDEDMA
*dma
, uint32_t tx_bytes
)
1459 AHCIDevice
*ad
= DO_UPCAST(AHCIDevice
, dma
, dma
);
1461 tx_bytes
+= le32_to_cpu(ad
->cur_cmd
->status
);
1462 ad
->cur_cmd
->status
= cpu_to_le32(tx_bytes
);
1465 static int ahci_dma_rw_buf(IDEDMA
*dma
, int is_write
)
1467 AHCIDevice
*ad
= DO_UPCAST(AHCIDevice
, dma
, dma
);
1468 IDEState
*s
= &ad
->port
.ifs
[0];
1469 uint8_t *p
= s
->io_buffer
+ s
->io_buffer_index
;
1470 int l
= s
->io_buffer_size
- s
->io_buffer_index
;
1472 if (ahci_populate_sglist(ad
, &s
->sg
, ad
->cur_cmd
, l
, s
->io_buffer_offset
)) {
1477 dma_buf_read(p
, l
, &s
->sg
);
1479 dma_buf_write(p
, l
, &s
->sg
);
1482 /* free sglist, update byte count */
1483 dma_buf_commit(s
, l
);
1484 s
->io_buffer_index
+= l
;
1486 trace_ahci_dma_rw_buf(ad
->hba
, ad
->port_no
, l
);
1490 static void ahci_cmd_done(IDEDMA
*dma
)
1492 AHCIDevice
*ad
= DO_UPCAST(AHCIDevice
, dma
, dma
);
1494 trace_ahci_cmd_done(ad
->hba
, ad
->port_no
);
1496 /* no longer busy */
1497 if (ad
->busy_slot
!= -1) {
1498 ad
->port_regs
.cmd_issue
&= ~(1 << ad
->busy_slot
);
1502 /* update d2h status */
1503 ahci_write_fis_d2h(ad
);
1505 if (ad
->port_regs
.cmd_issue
&& !ad
->check_bh
) {
1506 ad
->check_bh
= qemu_bh_new(ahci_check_cmd_bh
, ad
);
1507 qemu_bh_schedule(ad
->check_bh
);
1511 static void ahci_irq_set(void *opaque
, int n
, int level
)
1515 static const IDEDMAOps ahci_dma_ops
= {
1516 .start_dma
= ahci_start_dma
,
1517 .restart
= ahci_restart
,
1518 .restart_dma
= ahci_restart_dma
,
1519 .pio_transfer
= ahci_pio_transfer
,
1520 .prepare_buf
= ahci_dma_prepare_buf
,
1521 .commit_buf
= ahci_commit_buf
,
1522 .rw_buf
= ahci_dma_rw_buf
,
1523 .cmd_done
= ahci_cmd_done
,
1526 void ahci_init(AHCIState
*s
, DeviceState
*qdev
)
1528 s
->container
= qdev
;
1529 /* XXX BAR size should be 1k, but that breaks, so bump it to 4k for now */
1530 memory_region_init_io(&s
->mem
, OBJECT(qdev
), &ahci_mem_ops
, s
,
1531 "ahci", AHCI_MEM_BAR_SIZE
);
1532 memory_region_init_io(&s
->idp
, OBJECT(qdev
), &ahci_idp_ops
, s
,
1536 void ahci_realize(AHCIState
*s
, DeviceState
*qdev
, AddressSpace
*as
, int ports
)
1543 s
->dev
= g_new0(AHCIDevice
, ports
);
1545 irqs
= qemu_allocate_irqs(ahci_irq_set
, s
, s
->ports
);
1546 for (i
= 0; i
< s
->ports
; i
++) {
1547 AHCIDevice
*ad
= &s
->dev
[i
];
1549 ide_bus_new(&ad
->port
, sizeof(ad
->port
), qdev
, i
, 1);
1550 ide_init2(&ad
->port
, irqs
[i
]);
1554 ad
->port
.dma
= &ad
->dma
;
1555 ad
->port
.dma
->ops
= &ahci_dma_ops
;
1556 ide_register_restart_cb(&ad
->port
);
1561 void ahci_uninit(AHCIState
*s
)
1565 for (i
= 0; i
< s
->ports
; i
++) {
1566 AHCIDevice
*ad
= &s
->dev
[i
];
1568 for (j
= 0; j
< 2; j
++) {
1569 IDEState
*s
= &ad
->port
.ifs
[j
];
1573 object_unparent(OBJECT(&ad
->port
));
1579 void ahci_reset(AHCIState
*s
)
1584 trace_ahci_reset(s
);
1586 s
->control_regs
.irqstatus
= 0;
1588 * The implementation of this bit is dependent upon the value of the
1589 * CAP.SAM bit. If CAP.SAM is '0', then GHC.AE shall be read-write and
1590 * shall have a reset value of '0'. If CAP.SAM is '1', then AE shall be
1591 * read-only and shall have a reset value of '1'.
1593 * We set HOST_CAP_AHCI so we must enable AHCI at reset.
1595 s
->control_regs
.ghc
= HOST_CTL_AHCI_EN
;
1597 for (i
= 0; i
< s
->ports
; i
++) {
1598 pr
= &s
->dev
[i
].port_regs
;
1602 pr
->cmd
= PORT_CMD_SPIN_UP
| PORT_CMD_POWER_ON
;
1603 ahci_reset_port(s
, i
);
1607 static const VMStateDescription vmstate_ncq_tfs
= {
1608 .name
= "ncq state",
1610 .fields
= (VMStateField
[]) {
1611 VMSTATE_UINT32(sector_count
, NCQTransferState
),
1612 VMSTATE_UINT64(lba
, NCQTransferState
),
1613 VMSTATE_UINT8(tag
, NCQTransferState
),
1614 VMSTATE_UINT8(cmd
, NCQTransferState
),
1615 VMSTATE_UINT8(slot
, NCQTransferState
),
1616 VMSTATE_BOOL(used
, NCQTransferState
),
1617 VMSTATE_BOOL(halt
, NCQTransferState
),
1618 VMSTATE_END_OF_LIST()
1622 static const VMStateDescription vmstate_ahci_device
= {
1623 .name
= "ahci port",
1625 .fields
= (VMStateField
[]) {
1626 VMSTATE_IDE_BUS(port
, AHCIDevice
),
1627 VMSTATE_IDE_DRIVE(port
.ifs
[0], AHCIDevice
),
1628 VMSTATE_UINT32(port_state
, AHCIDevice
),
1629 VMSTATE_UINT32(finished
, AHCIDevice
),
1630 VMSTATE_UINT32(port_regs
.lst_addr
, AHCIDevice
),
1631 VMSTATE_UINT32(port_regs
.lst_addr_hi
, AHCIDevice
),
1632 VMSTATE_UINT32(port_regs
.fis_addr
, AHCIDevice
),
1633 VMSTATE_UINT32(port_regs
.fis_addr_hi
, AHCIDevice
),
1634 VMSTATE_UINT32(port_regs
.irq_stat
, AHCIDevice
),
1635 VMSTATE_UINT32(port_regs
.irq_mask
, AHCIDevice
),
1636 VMSTATE_UINT32(port_regs
.cmd
, AHCIDevice
),
1637 VMSTATE_UINT32(port_regs
.tfdata
, AHCIDevice
),
1638 VMSTATE_UINT32(port_regs
.sig
, AHCIDevice
),
1639 VMSTATE_UINT32(port_regs
.scr_stat
, AHCIDevice
),
1640 VMSTATE_UINT32(port_regs
.scr_ctl
, AHCIDevice
),
1641 VMSTATE_UINT32(port_regs
.scr_err
, AHCIDevice
),
1642 VMSTATE_UINT32(port_regs
.scr_act
, AHCIDevice
),
1643 VMSTATE_UINT32(port_regs
.cmd_issue
, AHCIDevice
),
1644 VMSTATE_BOOL(done_first_drq
, AHCIDevice
),
1645 VMSTATE_INT32(busy_slot
, AHCIDevice
),
1646 VMSTATE_BOOL(init_d2h_sent
, AHCIDevice
),
1647 VMSTATE_STRUCT_ARRAY(ncq_tfs
, AHCIDevice
, AHCI_MAX_CMDS
,
1648 1, vmstate_ncq_tfs
, NCQTransferState
),
1649 VMSTATE_END_OF_LIST()
1653 static int ahci_state_post_load(void *opaque
, int version_id
)
1656 struct AHCIDevice
*ad
;
1657 NCQTransferState
*ncq_tfs
;
1659 AHCIState
*s
= opaque
;
1661 for (i
= 0; i
< s
->ports
; i
++) {
1663 pr
= &ad
->port_regs
;
1665 if (!(pr
->cmd
& PORT_CMD_START
) && (pr
->cmd
& PORT_CMD_LIST_ON
)) {
1666 error_report("AHCI: DMA engine should be off, but status bit "
1667 "indicates it is still running.");
1670 if (!(pr
->cmd
& PORT_CMD_FIS_RX
) && (pr
->cmd
& PORT_CMD_FIS_ON
)) {
1671 error_report("AHCI: FIS RX engine should be off, but status bit "
1672 "indicates it is still running.");
1676 /* After a migrate, the DMA/FIS engines are "off" and
1677 * need to be conditionally restarted */
1678 pr
->cmd
&= ~(PORT_CMD_LIST_ON
| PORT_CMD_FIS_ON
);
1679 if (ahci_cond_start_engines(ad
) != 0) {
1683 for (j
= 0; j
< AHCI_MAX_CMDS
; j
++) {
1684 ncq_tfs
= &ad
->ncq_tfs
[j
];
1685 ncq_tfs
->drive
= ad
;
1687 if (ncq_tfs
->used
!= ncq_tfs
->halt
) {
1690 if (!ncq_tfs
->halt
) {
1693 if (!is_ncq(ncq_tfs
->cmd
)) {
1696 if (ncq_tfs
->slot
!= ncq_tfs
->tag
) {
1699 /* If ncq_tfs->halt is justly set, the engine should be engaged,
1700 * and the command list buffer should be mapped. */
1701 ncq_tfs
->cmdh
= get_cmd_header(s
, i
, ncq_tfs
->slot
);
1702 if (!ncq_tfs
->cmdh
) {
1705 ahci_populate_sglist(ncq_tfs
->drive
, &ncq_tfs
->sglist
,
1706 ncq_tfs
->cmdh
, ncq_tfs
->sector_count
* 512,
1708 if (ncq_tfs
->sector_count
!= ncq_tfs
->sglist
.size
>> 9) {
1715 * If an error is present, ad->busy_slot will be valid and not -1.
1716 * In this case, an operation is waiting to resume and will re-check
1717 * for additional AHCI commands to execute upon completion.
1719 * In the case where no error was present, busy_slot will be -1,
1720 * and we should check to see if there are additional commands waiting.
1722 if (ad
->busy_slot
== -1) {
1725 /* We are in the middle of a command, and may need to access
1726 * the command header in guest memory again. */
1727 if (ad
->busy_slot
< 0 || ad
->busy_slot
>= AHCI_MAX_CMDS
) {
1730 ad
->cur_cmd
= get_cmd_header(s
, i
, ad
->busy_slot
);
1737 const VMStateDescription vmstate_ahci
= {
1740 .post_load
= ahci_state_post_load
,
1741 .fields
= (VMStateField
[]) {
1742 VMSTATE_STRUCT_VARRAY_POINTER_INT32(dev
, AHCIState
, ports
,
1743 vmstate_ahci_device
, AHCIDevice
),
1744 VMSTATE_UINT32(control_regs
.cap
, AHCIState
),
1745 VMSTATE_UINT32(control_regs
.ghc
, AHCIState
),
1746 VMSTATE_UINT32(control_regs
.irqstatus
, AHCIState
),
1747 VMSTATE_UINT32(control_regs
.impl
, AHCIState
),
1748 VMSTATE_UINT32(control_regs
.version
, AHCIState
),
1749 VMSTATE_UINT32(idp_index
, AHCIState
),
1750 VMSTATE_INT32_EQUAL(ports
, AHCIState
, NULL
),
1751 VMSTATE_END_OF_LIST()
1755 static const VMStateDescription vmstate_sysbus_ahci
= {
1756 .name
= "sysbus-ahci",
1757 .fields
= (VMStateField
[]) {
1758 VMSTATE_AHCI(ahci
, SysbusAHCIState
),
1759 VMSTATE_END_OF_LIST()
1763 static void sysbus_ahci_reset(DeviceState
*dev
)
1765 SysbusAHCIState
*s
= SYSBUS_AHCI(dev
);
1767 ahci_reset(&s
->ahci
);
1770 static void sysbus_ahci_init(Object
*obj
)
1772 SysbusAHCIState
*s
= SYSBUS_AHCI(obj
);
1773 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
1775 ahci_init(&s
->ahci
, DEVICE(obj
));
1777 sysbus_init_mmio(sbd
, &s
->ahci
.mem
);
1778 sysbus_init_irq(sbd
, &s
->ahci
.irq
);
1781 static void sysbus_ahci_realize(DeviceState
*dev
, Error
**errp
)
1783 SysbusAHCIState
*s
= SYSBUS_AHCI(dev
);
1785 ahci_realize(&s
->ahci
, dev
, &address_space_memory
, s
->num_ports
);
1788 static Property sysbus_ahci_properties
[] = {
1789 DEFINE_PROP_UINT32("num-ports", SysbusAHCIState
, num_ports
, 1),
1790 DEFINE_PROP_END_OF_LIST(),
1793 static void sysbus_ahci_class_init(ObjectClass
*klass
, void *data
)
1795 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1797 dc
->realize
= sysbus_ahci_realize
;
1798 dc
->vmsd
= &vmstate_sysbus_ahci
;
1799 dc
->props
= sysbus_ahci_properties
;
1800 dc
->reset
= sysbus_ahci_reset
;
1801 set_bit(DEVICE_CATEGORY_STORAGE
, dc
->categories
);
1804 static const TypeInfo sysbus_ahci_info
= {
1805 .name
= TYPE_SYSBUS_AHCI
,
1806 .parent
= TYPE_SYS_BUS_DEVICE
,
1807 .instance_size
= sizeof(SysbusAHCIState
),
1808 .instance_init
= sysbus_ahci_init
,
1809 .class_init
= sysbus_ahci_class_init
,
1812 static void sysbus_ahci_register_types(void)
1814 type_register_static(&sysbus_ahci_info
);
1817 type_init(sysbus_ahci_register_types
)
1819 int32_t ahci_get_num_ports(PCIDevice
*dev
)
1821 AHCIPCIState
*d
= ICH_AHCI(dev
);
1822 AHCIState
*ahci
= &d
->ahci
;
1827 void ahci_ide_create_devs(PCIDevice
*dev
, DriveInfo
**hd
)
1829 AHCIPCIState
*d
= ICH_AHCI(dev
);
1830 AHCIState
*ahci
= &d
->ahci
;
1833 for (i
= 0; i
< ahci
->ports
; i
++) {
1834 if (hd
[i
] == NULL
) {
1837 ide_create_drive(&ahci
->dev
[i
].port
, 0, hd
[i
]);