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ppc/pnv: Remove user-created PHB{3,4,5} devices
[qemu.git] / hw / ppc / pnv.c
blob00f57c9678e6a7f97cf445cb9a5dd41d1b6e9d6c
1 /*
2 * QEMU PowerPC PowerNV machine model
3 *
4 * Copyright (c) 2016, IBM Corporation.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu-common.h"
22 #include "qemu/datadir.h"
23 #include "qemu/units.h"
24 #include "qemu/cutils.h"
25 #include "qapi/error.h"
26 #include "sysemu/qtest.h"
27 #include "sysemu/sysemu.h"
28 #include "sysemu/numa.h"
29 #include "sysemu/reset.h"
30 #include "sysemu/runstate.h"
31 #include "sysemu/cpus.h"
32 #include "sysemu/device_tree.h"
33 #include "sysemu/hw_accel.h"
34 #include "target/ppc/cpu.h"
35 #include "hw/ppc/fdt.h"
36 #include "hw/ppc/ppc.h"
37 #include "hw/ppc/pnv.h"
38 #include "hw/ppc/pnv_core.h"
39 #include "hw/loader.h"
40 #include "hw/nmi.h"
41 #include "qapi/visitor.h"
42 #include "monitor/monitor.h"
43 #include "hw/intc/intc.h"
44 #include "hw/ipmi/ipmi.h"
45 #include "target/ppc/mmu-hash64.h"
46 #include "hw/pci/msi.h"
47
48 #include "hw/ppc/xics.h"
49 #include "hw/qdev-properties.h"
50 #include "hw/ppc/pnv_xscom.h"
51 #include "hw/ppc/pnv_pnor.h"
52
53 #include "hw/isa/isa.h"
54 #include "hw/char/serial.h"
55 #include "hw/rtc/mc146818rtc.h"
56
57 #include <libfdt.h>
58
59 #define FDT_MAX_SIZE (1 * MiB)
60
61 #define FW_FILE_NAME "skiboot.lid"
62 #define FW_LOAD_ADDR 0x0
63 #define FW_MAX_SIZE (16 * MiB)
64
65 #define KERNEL_LOAD_ADDR 0x20000000
66 #define KERNEL_MAX_SIZE (128 * MiB)
67 #define INITRD_LOAD_ADDR 0x28000000
68 #define INITRD_MAX_SIZE (128 * MiB)
69
70 static const char *pnv_chip_core_typename(const PnvChip *o)
71 {
72 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o)));
73 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX);
74 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type);
75 const char *core_type = object_class_get_name(object_class_by_name(s));
76 g_free(s);
77 return core_type;
78 }
79
80 /*
81 * On Power Systems E880 (POWER8), the max cpus (threads) should be :
82 * 4 * 4 sockets * 12 cores * 8 threads = 1536
83 * Let's make it 2^11
84 */
85 #define MAX_CPUS 2048
86
87 /*
88 * Memory nodes are created by hostboot, one for each range of memory
89 * that has a different "affinity". In practice, it means one range
90 * per chip.
91 */
92 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size)
93 {
94 char *mem_name;
95 uint64_t mem_reg_property[2];
96 int off;
97
98 mem_reg_property[0] = cpu_to_be64(start);
99 mem_reg_property[1] = cpu_to_be64(size);
100
101 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start);
102 off = fdt_add_subnode(fdt, 0, mem_name);
103 g_free(mem_name);
104
105 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
106 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
107 sizeof(mem_reg_property))));
108 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id)));
109 }
110
111 static int get_cpus_node(void *fdt)
112 {
113 int cpus_offset = fdt_path_offset(fdt, "/cpus");
114
115 if (cpus_offset < 0) {
116 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
117 if (cpus_offset) {
118 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
119 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
120 }
121 }
122 _FDT(cpus_offset);
123 return cpus_offset;
124 }
125
126 /*
127 * The PowerNV cores (and threads) need to use real HW ids and not an
128 * incremental index like it has been done on other platforms. This HW
129 * id is stored in the CPU PIR, it is used to create cpu nodes in the
130 * device tree, used in XSCOM to address cores and in interrupt
131 * servers.
132 */
133 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
134 {
135 PowerPCCPU *cpu = pc->threads[0];
136 CPUState *cs = CPU(cpu);
137 DeviceClass *dc = DEVICE_GET_CLASS(cs);
138 int smt_threads = CPU_CORE(pc)->nr_threads;
139 CPUPPCState *env = &cpu->env;
140 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
141 uint32_t servers_prop[smt_threads];
142 int i;
143 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
144 0xffffffff, 0xffffffff};
145 uint32_t tbfreq = PNV_TIMEBASE_FREQ;
146 uint32_t cpufreq = 1000000000;
147 uint32_t page_sizes_prop[64];
148 size_t page_sizes_prop_size;
149 const uint8_t pa_features[] = { 24, 0,
150 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0,
151 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
152 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
153 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
154 int offset;
155 char *nodename;
156 int cpus_offset = get_cpus_node(fdt);
157
158 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir);
159 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
160 _FDT(offset);
161 g_free(nodename);
162
163 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id)));
164
165 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir)));
166 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir)));
167 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
168
169 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
170 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
171 env->dcache_line_size)));
172 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
173 env->dcache_line_size)));
174 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
175 env->icache_line_size)));
176 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
177 env->icache_line_size)));
178
179 if (pcc->l1_dcache_size) {
180 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
181 pcc->l1_dcache_size)));
182 } else {
183 warn_report("Unknown L1 dcache size for cpu");
184 }
185 if (pcc->l1_icache_size) {
186 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
187 pcc->l1_icache_size)));
188 } else {
189 warn_report("Unknown L1 icache size for cpu");
190 }
191
192 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
193 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
194 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size",
195 cpu->hash64_opts->slb_size)));
196 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
197 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
198
199 if (ppc_has_spr(cpu, SPR_PURR)) {
200 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
201 }
202
203 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) {
204 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
205 segs, sizeof(segs))));
206 }
207
208 /*
209 * Advertise VMX/VSX (vector extensions) if available
210 * 0 / no property == no vector extensions
211 * 1 == VMX / Altivec available
212 * 2 == VSX available
213 */
214 if (env->insns_flags & PPC_ALTIVEC) {
215 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
216
217 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
218 }
219
220 /*
221 * Advertise DFP (Decimal Floating Point) if available
222 * 0 / no property == no DFP
223 * 1 == DFP available
224 */
225 if (env->insns_flags2 & PPC2_DFP) {
226 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
227 }
228
229 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop,
230 sizeof(page_sizes_prop));
231 if (page_sizes_prop_size) {
232 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
233 page_sizes_prop, page_sizes_prop_size)));
234 }
235
236 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
237 pa_features, sizeof(pa_features))));
238
239 /* Build interrupt servers properties */
240 for (i = 0; i < smt_threads; i++) {
241 servers_prop[i] = cpu_to_be32(pc->pir + i);
242 }
243 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
244 servers_prop, sizeof(servers_prop))));
245 }
246
247 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir,
248 uint32_t nr_threads)
249 {
250 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12);
251 char *name;
252 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp";
253 uint32_t irange[2], i, rsize;
254 uint64_t *reg;
255 int offset;
256
257 irange[0] = cpu_to_be32(pir);
258 irange[1] = cpu_to_be32(nr_threads);
259
260 rsize = sizeof(uint64_t) * 2 * nr_threads;
261 reg = g_malloc(rsize);
262 for (i = 0; i < nr_threads; i++) {
263 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000));
264 reg[i * 2 + 1] = cpu_to_be64(0x1000);
265 }
266
267 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr);
268 offset = fdt_add_subnode(fdt, 0, name);
269 _FDT(offset);
270 g_free(name);
271
272 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat))));
273 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize)));
274 _FDT((fdt_setprop_string(fdt, offset, "device_type",
275 "PowerPC-External-Interrupt-Presentation")));
276 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0)));
277 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges",
278 irange, sizeof(irange))));
279 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1)));
280 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0)));
281 g_free(reg);
282 }
283
284 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt)
285 {
286 static const char compat[] = "ibm,power8-xscom\0ibm,xscom";
287 int i;
288
289 pnv_dt_xscom(chip, fdt, 0,
290 cpu_to_be64(PNV_XSCOM_BASE(chip)),
291 cpu_to_be64(PNV_XSCOM_SIZE),
292 compat, sizeof(compat));
293
294 for (i = 0; i < chip->nr_cores; i++) {
295 PnvCore *pnv_core = chip->cores[i];
296
297 pnv_dt_core(chip, pnv_core, fdt);
298
299 /* Interrupt Control Presenters (ICP). One per core. */
300 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads);
301 }
302
303 if (chip->ram_size) {
304 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
305 }
306 }
307
308 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
309 {
310 static const char compat[] = "ibm,power9-xscom\0ibm,xscom";
311 int i;
312
313 pnv_dt_xscom(chip, fdt, 0,
314 cpu_to_be64(PNV9_XSCOM_BASE(chip)),
315 cpu_to_be64(PNV9_XSCOM_SIZE),
316 compat, sizeof(compat));
317
318 for (i = 0; i < chip->nr_cores; i++) {
319 PnvCore *pnv_core = chip->cores[i];
320
321 pnv_dt_core(chip, pnv_core, fdt);
322 }
323
324 if (chip->ram_size) {
325 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
326 }
327
328 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE);
329 }
330
331 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
332 {
333 static const char compat[] = "ibm,power10-xscom\0ibm,xscom";
334 int i;
335
336 pnv_dt_xscom(chip, fdt, 0,
337 cpu_to_be64(PNV10_XSCOM_BASE(chip)),
338 cpu_to_be64(PNV10_XSCOM_SIZE),
339 compat, sizeof(compat));
340
341 for (i = 0; i < chip->nr_cores; i++) {
342 PnvCore *pnv_core = chip->cores[i];
343
344 pnv_dt_core(chip, pnv_core, fdt);
345 }
346
347 if (chip->ram_size) {
348 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
349 }
350
351 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE);
352 }
353
354 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off)
355 {
356 uint32_t io_base = d->ioport_id;
357 uint32_t io_regs[] = {
358 cpu_to_be32(1),
359 cpu_to_be32(io_base),
360 cpu_to_be32(2)
361 };
362 char *name;
363 int node;
364
365 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
366 node = fdt_add_subnode(fdt, lpc_off, name);
367 _FDT(node);
368 g_free(name);
369
370 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
371 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00")));
372 }
373
374 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off)
375 {
376 const char compatible[] = "ns16550\0pnpPNP,501";
377 uint32_t io_base = d->ioport_id;
378 uint32_t io_regs[] = {
379 cpu_to_be32(1),
380 cpu_to_be32(io_base),
381 cpu_to_be32(8)
382 };
383 uint32_t irq;
384 char *name;
385 int node;
386
387 irq = object_property_get_uint(OBJECT(d), "irq", &error_fatal);
388
389 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
390 node = fdt_add_subnode(fdt, lpc_off, name);
391 _FDT(node);
392 g_free(name);
393
394 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
395 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
396 sizeof(compatible))));
397
398 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200)));
399 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200)));
400 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq)));
401 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
402 fdt_get_phandle(fdt, lpc_off))));
403
404 /* This is needed by Linux */
405 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial")));
406 }
407
408 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off)
409 {
410 const char compatible[] = "bt\0ipmi-bt";
411 uint32_t io_base;
412 uint32_t io_regs[] = {
413 cpu_to_be32(1),
414 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */
415 cpu_to_be32(3)
416 };
417 uint32_t irq;
418 char *name;
419 int node;
420
421 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal);
422 io_regs[1] = cpu_to_be32(io_base);
423
424 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal);
425
426 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
427 node = fdt_add_subnode(fdt, lpc_off, name);
428 _FDT(node);
429 g_free(name);
430
431 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
432 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
433 sizeof(compatible))));
434
435 /* Mark it as reserved to avoid Linux trying to claim it */
436 _FDT((fdt_setprop_string(fdt, node, "status", "reserved")));
437 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq)));
438 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
439 fdt_get_phandle(fdt, lpc_off))));
440 }
441
442 typedef struct ForeachPopulateArgs {
443 void *fdt;
444 int offset;
445 } ForeachPopulateArgs;
446
447 static int pnv_dt_isa_device(DeviceState *dev, void *opaque)
448 {
449 ForeachPopulateArgs *args = opaque;
450 ISADevice *d = ISA_DEVICE(dev);
451
452 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) {
453 pnv_dt_rtc(d, args->fdt, args->offset);
454 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) {
455 pnv_dt_serial(d, args->fdt, args->offset);
456 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) {
457 pnv_dt_ipmi_bt(d, args->fdt, args->offset);
458 } else {
459 error_report("unknown isa device %s@i%x", qdev_fw_name(dev),
460 d->ioport_id);
461 }
462
463 return 0;
464 }
465
466 /*
467 * The default LPC bus of a multichip system is on chip 0. It's
468 * recognized by the firmware (skiboot) using a "primary" property.
469 */
470 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt)
471 {
472 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename);
473 ForeachPopulateArgs args = {
474 .fdt = fdt,
475 .offset = isa_offset,
476 };
477 uint32_t phandle;
478
479 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0)));
480
481 phandle = qemu_fdt_alloc_phandle(fdt);
482 assert(phandle > 0);
483 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle)));
484
485 /*
486 * ISA devices are not necessarily parented to the ISA bus so we
487 * can not use object_child_foreach()
488 */
489 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL,
490 &args);
491 }
492
493 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt)
494 {
495 int off;
496
497 off = fdt_add_subnode(fdt, 0, "ibm,opal");
498 off = fdt_add_subnode(fdt, off, "power-mgt");
499
500 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000));
501 }
502
503 static void *pnv_dt_create(MachineState *machine)
504 {
505 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine);
506 PnvMachineState *pnv = PNV_MACHINE(machine);
507 void *fdt;
508 char *buf;
509 int off;
510 int i;
511
512 fdt = g_malloc0(FDT_MAX_SIZE);
513 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
514
515 /* /qemu node */
516 _FDT((fdt_add_subnode(fdt, 0, "qemu")));
517
518 /* Root node */
519 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2)));
520 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2)));
521 _FDT((fdt_setprop_string(fdt, 0, "model",
522 "IBM PowerNV (emulated by qemu)")));
523 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size)));
524
525 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
526 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf)));
527 if (qemu_uuid_set) {
528 _FDT((fdt_setprop_string(fdt, 0, "system-id", buf)));
529 }
530 g_free(buf);
531
532 off = fdt_add_subnode(fdt, 0, "chosen");
533 if (machine->kernel_cmdline) {
534 _FDT((fdt_setprop_string(fdt, off, "bootargs",
535 machine->kernel_cmdline)));
536 }
537
538 if (pnv->initrd_size) {
539 uint32_t start_prop = cpu_to_be32(pnv->initrd_base);
540 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size);
541
542 _FDT((fdt_setprop(fdt, off, "linux,initrd-start",
543 &start_prop, sizeof(start_prop))));
544 _FDT((fdt_setprop(fdt, off, "linux,initrd-end",
545 &end_prop, sizeof(end_prop))));
546 }
547
548 /* Populate device tree for each chip */
549 for (i = 0; i < pnv->num_chips; i++) {
550 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt);
551 }
552
553 /* Populate ISA devices on chip 0 */
554 pnv_dt_isa(pnv, fdt);
555
556 if (pnv->bmc) {
557 pnv_dt_bmc_sensors(pnv->bmc, fdt);
558 }
559
560 /* Create an extra node for power management on machines that support it */
561 if (pmc->dt_power_mgt) {
562 pmc->dt_power_mgt(pnv, fdt);
563 }
564
565 return fdt;
566 }
567
568 static void pnv_powerdown_notify(Notifier *n, void *opaque)
569 {
570 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier);
571
572 if (pnv->bmc) {
573 pnv_bmc_powerdown(pnv->bmc);
574 }
575 }
576
577 static void pnv_reset(MachineState *machine)
578 {
579 PnvMachineState *pnv = PNV_MACHINE(machine);
580 IPMIBmc *bmc;
581 void *fdt;
582
583 qemu_devices_reset();
584
585 /*
586 * The machine should provide by default an internal BMC simulator.
587 * If not, try to use the BMC device that was provided on the command
588 * line.
589 */
590 bmc = pnv_bmc_find(&error_fatal);
591 if (!pnv->bmc) {
592 if (!bmc) {
593 if (!qtest_enabled()) {
594 warn_report("machine has no BMC device. Use '-device "
595 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' "
596 "to define one");
597 }
598 } else {
599 pnv_bmc_set_pnor(bmc, pnv->pnor);
600 pnv->bmc = bmc;
601 }
602 }
603
604 fdt = pnv_dt_create(machine);
605
606 /* Pack resulting tree */
607 _FDT((fdt_pack(fdt)));
608
609 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
610 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt));
611
612 g_free(fdt);
613 }
614
615 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp)
616 {
617 Pnv8Chip *chip8 = PNV8_CHIP(chip);
618 return pnv_lpc_isa_create(&chip8->lpc, true, errp);
619 }
620
621 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp)
622 {
623 Pnv8Chip *chip8 = PNV8_CHIP(chip);
624 return pnv_lpc_isa_create(&chip8->lpc, false, errp);
625 }
626
627 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp)
628 {
629 Pnv9Chip *chip9 = PNV9_CHIP(chip);
630 return pnv_lpc_isa_create(&chip9->lpc, false, errp);
631 }
632
633 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp)
634 {
635 Pnv10Chip *chip10 = PNV10_CHIP(chip);
636 return pnv_lpc_isa_create(&chip10->lpc, false, errp);
637 }
638
639 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp)
640 {
641 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp);
642 }
643
644 static int pnv_chip_power8_pic_print_info_child(Object *child, void *opaque)
645 {
646 Monitor *mon = opaque;
647 PnvPHB3 *phb3 = (PnvPHB3 *) object_dynamic_cast(child, TYPE_PNV_PHB3);
648
649 if (phb3) {
650 pnv_phb3_msi_pic_print_info(&phb3->msis, mon);
651 ics_pic_print_info(&phb3->lsis, mon);
652 }
653 return 0;
654 }
655
656 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon)
657 {
658 Pnv8Chip *chip8 = PNV8_CHIP(chip);
659
660 ics_pic_print_info(&chip8->psi.ics, mon);
661 object_child_foreach(OBJECT(chip),
662 pnv_chip_power8_pic_print_info_child, mon);
663 }
664
665 static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque)
666 {
667 Monitor *mon = opaque;
668 PnvPHB4 *phb4 = (PnvPHB4 *) object_dynamic_cast(child, TYPE_PNV_PHB4);
669
670 if (phb4) {
671 pnv_phb4_pic_print_info(phb4, mon);
672 }
673 return 0;
674 }
675
676 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon)
677 {
678 Pnv9Chip *chip9 = PNV9_CHIP(chip);
679
680 pnv_xive_pic_print_info(&chip9->xive, mon);
681 pnv_psi_pic_print_info(&chip9->psi, mon);
682
683 object_child_foreach_recursive(OBJECT(chip),
684 pnv_chip_power9_pic_print_info_child, mon);
685 }
686
687 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip,
688 uint32_t core_id)
689 {
690 return PNV_XSCOM_EX_BASE(core_id);
691 }
692
693 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip,
694 uint32_t core_id)
695 {
696 return PNV9_XSCOM_EC_BASE(core_id);
697 }
698
699 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip,
700 uint32_t core_id)
701 {
702 return PNV10_XSCOM_EC_BASE(core_id);
703 }
704
705 static bool pnv_match_cpu(const char *default_type, const char *cpu_type)
706 {
707 PowerPCCPUClass *ppc_default =
708 POWERPC_CPU_CLASS(object_class_by_name(default_type));
709 PowerPCCPUClass *ppc =
710 POWERPC_CPU_CLASS(object_class_by_name(cpu_type));
711
712 return ppc_default->pvr_match(ppc_default, ppc->pvr);
713 }
714
715 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq)
716 {
717 ISADevice *dev = isa_new("isa-ipmi-bt");
718
719 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal);
720 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal);
721 isa_realize_and_unref(dev, bus, &error_fatal);
722 }
723
724 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon)
725 {
726 Pnv10Chip *chip10 = PNV10_CHIP(chip);
727
728 pnv_xive2_pic_print_info(&chip10->xive, mon);
729 pnv_psi_pic_print_info(&chip10->psi, mon);
730
731 object_child_foreach_recursive(OBJECT(chip),
732 pnv_chip_power9_pic_print_info_child, mon);
733 }
734
735 /* Always give the first 1GB to chip 0 else we won't boot */
736 static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv, int chip_id)
737 {
738 MachineState *machine = MACHINE(pnv);
739 uint64_t ram_per_chip;
740
741 assert(machine->ram_size >= 1 * GiB);
742
743 ram_per_chip = machine->ram_size / pnv->num_chips;
744 if (ram_per_chip >= 1 * GiB) {
745 return QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB);
746 }
747
748 assert(pnv->num_chips > 1);
749
750 ram_per_chip = (machine->ram_size - 1 * GiB) / (pnv->num_chips - 1);
751 return chip_id == 0 ? 1 * GiB : QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB);
752 }
753
754 static void pnv_init(MachineState *machine)
755 {
756 const char *bios_name = machine->firmware ?: FW_FILE_NAME;
757 PnvMachineState *pnv = PNV_MACHINE(machine);
758 MachineClass *mc = MACHINE_GET_CLASS(machine);
759 char *fw_filename;
760 long fw_size;
761 uint64_t chip_ram_start = 0;
762 int i;
763 char *chip_typename;
764 DriveInfo *pnor = drive_get(IF_MTD, 0, 0);
765 DeviceState *dev;
766
767 if (kvm_enabled()) {
768 error_report("The powernv machine does not work with KVM acceleration");
769 exit(EXIT_FAILURE);
770 }
771
772 /* allocate RAM */
773 if (machine->ram_size < mc->default_ram_size) {
774 char *sz = size_to_str(mc->default_ram_size);
775 error_report("Invalid RAM size, should be bigger than %s", sz);
776 g_free(sz);
777 exit(EXIT_FAILURE);
778 }
779 memory_region_add_subregion(get_system_memory(), 0, machine->ram);
780
781 /*
782 * Create our simple PNOR device
783 */
784 dev = qdev_new(TYPE_PNV_PNOR);
785 if (pnor) {
786 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor));
787 }
788 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
789 pnv->pnor = PNV_PNOR(dev);
790
791 /* load skiboot firmware */
792 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
793 if (!fw_filename) {
794 error_report("Could not find OPAL firmware '%s'", bios_name);
795 exit(1);
796 }
797
798 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE);
799 if (fw_size < 0) {
800 error_report("Could not load OPAL firmware '%s'", fw_filename);
801 exit(1);
802 }
803 g_free(fw_filename);
804
805 /* load kernel */
806 if (machine->kernel_filename) {
807 long kernel_size;
808
809 kernel_size = load_image_targphys(machine->kernel_filename,
810 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE);
811 if (kernel_size < 0) {
812 error_report("Could not load kernel '%s'",
813 machine->kernel_filename);
814 exit(1);
815 }
816 }
817
818 /* load initrd */
819 if (machine->initrd_filename) {
820 pnv->initrd_base = INITRD_LOAD_ADDR;
821 pnv->initrd_size = load_image_targphys(machine->initrd_filename,
822 pnv->initrd_base, INITRD_MAX_SIZE);
823 if (pnv->initrd_size < 0) {
824 error_report("Could not load initial ram disk '%s'",
825 machine->initrd_filename);
826 exit(1);
827 }
828 }
829
830 /* MSIs are supported on this platform */
831 msi_nonbroken = true;
832
833 /*
834 * Check compatibility of the specified CPU with the machine
835 * default.
836 */
837 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) {
838 error_report("invalid CPU model '%s' for %s machine",
839 machine->cpu_type, mc->name);
840 exit(1);
841 }
842
843 /* Create the processor chips */
844 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX);
845 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"),
846 i, machine->cpu_type);
847 if (!object_class_by_name(chip_typename)) {
848 error_report("invalid chip model '%.*s' for %s machine",
849 i, machine->cpu_type, mc->name);
850 exit(1);
851 }
852
853 pnv->num_chips =
854 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads);
855 /*
856 * TODO: should we decide on how many chips we can create based
857 * on #cores and Venice vs. Murano vs. Naples chip type etc...,
858 */
859 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 16) {
860 error_report("invalid number of chips: '%d'", pnv->num_chips);
861 error_printf(
862 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n");
863 exit(1);
864 }
865
866 pnv->chips = g_new0(PnvChip *, pnv->num_chips);
867 for (i = 0; i < pnv->num_chips; i++) {
868 char chip_name[32];
869 Object *chip = OBJECT(qdev_new(chip_typename));
870 uint64_t chip_ram_size = pnv_chip_get_ram_size(pnv, i);
871
872 pnv->chips[i] = PNV_CHIP(chip);
873
874 /* Distribute RAM among the chips */
875 object_property_set_int(chip, "ram-start", chip_ram_start,
876 &error_fatal);
877 object_property_set_int(chip, "ram-size", chip_ram_size,
878 &error_fatal);
879 chip_ram_start += chip_ram_size;
880
881 snprintf(chip_name, sizeof(chip_name), "chip[%d]", i);
882 object_property_add_child(OBJECT(pnv), chip_name, chip);
883 object_property_set_int(chip, "chip-id", i, &error_fatal);
884 object_property_set_int(chip, "nr-cores", machine->smp.cores,
885 &error_fatal);
886 object_property_set_int(chip, "nr-threads", machine->smp.threads,
887 &error_fatal);
888 /*
889 * The POWER8 machine use the XICS interrupt interface.
890 * Propagate the XICS fabric to the chip and its controllers.
891 */
892 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) {
893 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort);
894 }
895 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) {
896 object_property_set_link(chip, "xive-fabric", OBJECT(pnv),
897 &error_abort);
898 }
899 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal);
900 }
901 g_free(chip_typename);
902
903 /* Instantiate ISA bus on chip 0 */
904 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal);
905
906 /* Create serial port */
907 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS);
908
909 /* Create an RTC ISA device too */
910 mc146818_rtc_init(pnv->isa_bus, 2000, NULL);
911
912 /*
913 * Create the machine BMC simulator and the IPMI BT device for
914 * communication with the BMC
915 */
916 if (defaults_enabled()) {
917 pnv->bmc = pnv_bmc_create(pnv->pnor);
918 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10);
919 }
920
921 /*
922 * The PNOR is mapped on the LPC FW address space by the BMC.
923 * Since we can not reach the remote BMC machine with LPC memops,
924 * map it always for now.
925 */
926 memory_region_add_subregion(pnv->chips[0]->fw_mr, PNOR_SPI_OFFSET,
927 &pnv->pnor->mmio);
928
929 /*
930 * OpenPOWER systems use a IPMI SEL Event message to notify the
931 * host to powerdown
932 */
933 pnv->powerdown_notifier.notify = pnv_powerdown_notify;
934 qemu_register_powerdown_notifier(&pnv->powerdown_notifier);
935 }
936
937 /*
938 * 0:21 Reserved - Read as zeros
939 * 22:24 Chip ID
940 * 25:28 Core number
941 * 29:31 Thread ID
942 */
943 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id)
944 {
945 return (chip->chip_id << 7) | (core_id << 3);
946 }
947
948 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu,
949 Error **errp)
950 {
951 Pnv8Chip *chip8 = PNV8_CHIP(chip);
952 Error *local_err = NULL;
953 Object *obj;
954 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
955
956 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err);
957 if (local_err) {
958 error_propagate(errp, local_err);
959 return;
960 }
961
962 pnv_cpu->intc = obj;
963 }
964
965
966 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
967 {
968 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
969
970 icp_reset(ICP(pnv_cpu->intc));
971 }
972
973 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
974 {
975 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
976
977 icp_destroy(ICP(pnv_cpu->intc));
978 pnv_cpu->intc = NULL;
979 }
980
981 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
982 Monitor *mon)
983 {
984 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon);
985 }
986
987 /*
988 * 0:48 Reserved - Read as zeroes
989 * 49:52 Node ID
990 * 53:55 Chip ID
991 * 56 Reserved - Read as zero
992 * 57:61 Core number
993 * 62:63 Thread ID
994 *
995 * We only care about the lower bits. uint32_t is fine for the moment.
996 */
997 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id)
998 {
999 return (chip->chip_id << 8) | (core_id << 2);
1000 }
1001
1002 static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id)
1003 {
1004 return (chip->chip_id << 8) | (core_id << 2);
1005 }
1006
1007 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu,
1008 Error **errp)
1009 {
1010 Pnv9Chip *chip9 = PNV9_CHIP(chip);
1011 Error *local_err = NULL;
1012 Object *obj;
1013 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1014
1015 /*
1016 * The core creates its interrupt presenter but the XIVE interrupt
1017 * controller object is initialized afterwards. Hopefully, it's
1018 * only used at runtime.
1019 */
1020 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive),
1021 &local_err);
1022 if (local_err) {
1023 error_propagate(errp, local_err);
1024 return;
1025 }
1026
1027 pnv_cpu->intc = obj;
1028 }
1029
1030 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
1031 {
1032 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1033
1034 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc));
1035 }
1036
1037 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
1038 {
1039 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1040
1041 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc));
1042 pnv_cpu->intc = NULL;
1043 }
1044
1045 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
1046 Monitor *mon)
1047 {
1048 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon);
1049 }
1050
1051 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu,
1052 Error **errp)
1053 {
1054 Pnv10Chip *chip10 = PNV10_CHIP(chip);
1055 Error *local_err = NULL;
1056 Object *obj;
1057 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1058
1059 /*
1060 * The core creates its interrupt presenter but the XIVE2 interrupt
1061 * controller object is initialized afterwards. Hopefully, it's
1062 * only used at runtime.
1063 */
1064 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip10->xive),
1065 &local_err);
1066 if (local_err) {
1067 error_propagate(errp, local_err);
1068 return;
1069 }
1070
1071 pnv_cpu->intc = obj;
1072 }
1073
1074 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
1075 {
1076 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1077
1078 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc));
1079 }
1080
1081 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
1082 {
1083 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1084
1085 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc));
1086 pnv_cpu->intc = NULL;
1087 }
1088
1089 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
1090 Monitor *mon)
1091 {
1092 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon);
1093 }
1094
1095 /*
1096 * Allowed core identifiers on a POWER8 Processor Chip :
1097 *
1098 * <EX0 reserved>
1099 * EX1 - Venice only
1100 * EX2 - Venice only
1101 * EX3 - Venice only
1102 * EX4
1103 * EX5
1104 * EX6
1105 * <EX7,8 reserved> <reserved>
1106 * EX9 - Venice only
1107 * EX10 - Venice only
1108 * EX11 - Venice only
1109 * EX12
1110 * EX13
1111 * EX14
1112 * <EX15 reserved>
1113 */
1114 #define POWER8E_CORE_MASK (0x7070ull)
1115 #define POWER8_CORE_MASK (0x7e7eull)
1116
1117 /*
1118 * POWER9 has 24 cores, ids starting at 0x0
1119 */
1120 #define POWER9_CORE_MASK (0xffffffffffffffull)
1121
1122
1123 #define POWER10_CORE_MASK (0xffffffffffffffull)
1124
1125 static void pnv_chip_power8_instance_init(Object *obj)
1126 {
1127 Pnv8Chip *chip8 = PNV8_CHIP(obj);
1128 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
1129 int i;
1130
1131 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC,
1132 (Object **)&chip8->xics,
1133 object_property_allow_set_link,
1134 OBJ_PROP_LINK_STRONG);
1135
1136 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI);
1137
1138 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC);
1139
1140 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC);
1141
1142 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER);
1143
1144 chip8->num_phbs = pcc->num_phbs;
1145
1146 for (i = 0; i < chip8->num_phbs; i++) {
1147 object_initialize_child(obj, "phb[*]", &chip8->phbs[i], TYPE_PNV_PHB3);
1148 }
1149
1150 }
1151
1152 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
1153 {
1154 PnvChip *chip = PNV_CHIP(chip8);
1155 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1156 int i, j;
1157 char *name;
1158
1159 name = g_strdup_printf("icp-%x", chip->chip_id);
1160 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE);
1161 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio);
1162 g_free(name);
1163
1164 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip));
1165
1166 /* Map the ICP registers for each thread */
1167 for (i = 0; i < chip->nr_cores; i++) {
1168 PnvCore *pnv_core = chip->cores[i];
1169 int core_hwid = CPU_CORE(pnv_core)->core_id;
1170
1171 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) {
1172 uint32_t pir = pcc->core_pir(chip, core_hwid) + j;
1173 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir));
1174
1175 memory_region_add_subregion(&chip8->icp_mmio, pir << 12,
1176 &icp->mmio);
1177 }
1178 }
1179 }
1180
1181 /* Attach a root port device */
1182 void pnv_phb_attach_root_port(PCIHostState *pci, const char *name)
1183 {
1184 PCIDevice *root = pci_new(PCI_DEVFN(0, 0), name);
1185
1186 pci_realize_and_unref(root, pci->bus, &error_fatal);
1187 }
1188
1189 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
1190 {
1191 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1192 PnvChip *chip = PNV_CHIP(dev);
1193 Pnv8Chip *chip8 = PNV8_CHIP(dev);
1194 Pnv8Psi *psi8 = &chip8->psi;
1195 Error *local_err = NULL;
1196 int i;
1197
1198 assert(chip8->xics);
1199
1200 /* XSCOM bridge is first */
1201 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err);
1202 if (local_err) {
1203 error_propagate(errp, local_err);
1204 return;
1205 }
1206 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip));
1207
1208 pcc->parent_realize(dev, &local_err);
1209 if (local_err) {
1210 error_propagate(errp, local_err);
1211 return;
1212 }
1213
1214 /* Processor Service Interface (PSI) Host Bridge */
1215 object_property_set_int(OBJECT(&chip8->psi), "bar", PNV_PSIHB_BASE(chip),
1216 &error_fatal);
1217 object_property_set_link(OBJECT(&chip8->psi), ICS_PROP_XICS,
1218 OBJECT(chip8->xics), &error_abort);
1219 if (!qdev_realize(DEVICE(&chip8->psi), NULL, errp)) {
1220 return;
1221 }
1222 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE,
1223 &PNV_PSI(psi8)->xscom_regs);
1224
1225 /* Create LPC controller */
1226 object_property_set_link(OBJECT(&chip8->lpc), "psi", OBJECT(&chip8->psi),
1227 &error_abort);
1228 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal);
1229 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs);
1230
1231 chip->fw_mr = &chip8->lpc.isa_fw;
1232 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x",
1233 (uint64_t) PNV_XSCOM_BASE(chip),
1234 PNV_XSCOM_LPC_BASE);
1235
1236 /*
1237 * Interrupt Management Area. This is the memory region holding
1238 * all the Interrupt Control Presenter (ICP) registers
1239 */
1240 pnv_chip_icp_realize(chip8, &local_err);
1241 if (local_err) {
1242 error_propagate(errp, local_err);
1243 return;
1244 }
1245
1246 /* Create the simplified OCC model */
1247 object_property_set_link(OBJECT(&chip8->occ), "psi", OBJECT(&chip8->psi),
1248 &error_abort);
1249 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) {
1250 return;
1251 }
1252 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs);
1253
1254 /* OCC SRAM model */
1255 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip),
1256 &chip8->occ.sram_regs);
1257
1258 /* HOMER */
1259 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip),
1260 &error_abort);
1261 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) {
1262 return;
1263 }
1264 /* Homer Xscom region */
1265 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs);
1266
1267 /* Homer mmio region */
1268 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip),
1269 &chip8->homer.regs);
1270
1271 /* PHB3 controllers */
1272 for (i = 0; i < chip8->num_phbs; i++) {
1273 PnvPHB3 *phb = &chip8->phbs[i];
1274
1275 object_property_set_int(OBJECT(phb), "index", i, &error_fatal);
1276 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id,
1277 &error_fatal);
1278 object_property_set_link(OBJECT(phb), "chip", OBJECT(chip),
1279 &error_fatal);
1280 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) {
1281 return;
1282 }
1283 }
1284 }
1285
1286 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr)
1287 {
1288 addr &= (PNV_XSCOM_SIZE - 1);
1289 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf);
1290 }
1291
1292 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
1293 {
1294 DeviceClass *dc = DEVICE_CLASS(klass);
1295 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1296
1297 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */
1298 k->cores_mask = POWER8E_CORE_MASK;
1299 k->num_phbs = 3;
1300 k->core_pir = pnv_chip_core_pir_p8;
1301 k->intc_create = pnv_chip_power8_intc_create;
1302 k->intc_reset = pnv_chip_power8_intc_reset;
1303 k->intc_destroy = pnv_chip_power8_intc_destroy;
1304 k->intc_print_info = pnv_chip_power8_intc_print_info;
1305 k->isa_create = pnv_chip_power8_isa_create;
1306 k->dt_populate = pnv_chip_power8_dt_populate;
1307 k->pic_print_info = pnv_chip_power8_pic_print_info;
1308 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
1309 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
1310 dc->desc = "PowerNV Chip POWER8E";
1311
1312 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1313 &k->parent_realize);
1314 }
1315
1316 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
1317 {
1318 DeviceClass *dc = DEVICE_CLASS(klass);
1319 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1320
1321 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */
1322 k->cores_mask = POWER8_CORE_MASK;
1323 k->num_phbs = 3;
1324 k->core_pir = pnv_chip_core_pir_p8;
1325 k->intc_create = pnv_chip_power8_intc_create;
1326 k->intc_reset = pnv_chip_power8_intc_reset;
1327 k->intc_destroy = pnv_chip_power8_intc_destroy;
1328 k->intc_print_info = pnv_chip_power8_intc_print_info;
1329 k->isa_create = pnv_chip_power8_isa_create;
1330 k->dt_populate = pnv_chip_power8_dt_populate;
1331 k->pic_print_info = pnv_chip_power8_pic_print_info;
1332 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
1333 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
1334 dc->desc = "PowerNV Chip POWER8";
1335
1336 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1337 &k->parent_realize);
1338 }
1339
1340 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
1341 {
1342 DeviceClass *dc = DEVICE_CLASS(klass);
1343 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1344
1345 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */
1346 k->cores_mask = POWER8_CORE_MASK;
1347 k->num_phbs = 4;
1348 k->core_pir = pnv_chip_core_pir_p8;
1349 k->intc_create = pnv_chip_power8_intc_create;
1350 k->intc_reset = pnv_chip_power8_intc_reset;
1351 k->intc_destroy = pnv_chip_power8_intc_destroy;
1352 k->intc_print_info = pnv_chip_power8_intc_print_info;
1353 k->isa_create = pnv_chip_power8nvl_isa_create;
1354 k->dt_populate = pnv_chip_power8_dt_populate;
1355 k->pic_print_info = pnv_chip_power8_pic_print_info;
1356 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
1357 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
1358 dc->desc = "PowerNV Chip POWER8NVL";
1359
1360 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1361 &k->parent_realize);
1362 }
1363
1364 static void pnv_chip_power9_instance_init(Object *obj)
1365 {
1366 PnvChip *chip = PNV_CHIP(obj);
1367 Pnv9Chip *chip9 = PNV9_CHIP(obj);
1368 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
1369 int i;
1370
1371 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE);
1372 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive),
1373 "xive-fabric");
1374
1375 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI);
1376
1377 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC);
1378
1379 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC);
1380
1381 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER);
1382
1383 /* Number of PECs is the chip default */
1384 chip->num_pecs = pcc->num_pecs;
1385
1386 for (i = 0; i < chip->num_pecs; i++) {
1387 object_initialize_child(obj, "pec[*]", &chip9->pecs[i],
1388 TYPE_PNV_PHB4_PEC);
1389 }
1390 }
1391
1392 static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq,
1393 PnvCore *pnv_core)
1394 {
1395 char eq_name[32];
1396 int core_id = CPU_CORE(pnv_core)->core_id;
1397
1398 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id);
1399 object_initialize_child_with_props(OBJECT(chip), eq_name, eq,
1400 sizeof(*eq), TYPE_PNV_QUAD,
1401 &error_fatal, NULL);
1402
1403 object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal);
1404 qdev_realize(DEVICE(eq), NULL, &error_fatal);
1405 }
1406
1407 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp)
1408 {
1409 PnvChip *chip = PNV_CHIP(chip9);
1410 int i;
1411
1412 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4);
1413 chip9->quads = g_new0(PnvQuad, chip9->nr_quads);
1414
1415 for (i = 0; i < chip9->nr_quads; i++) {
1416 PnvQuad *eq = &chip9->quads[i];
1417
1418 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]);
1419
1420 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id),
1421 &eq->xscom_regs);
1422 }
1423 }
1424
1425 static void pnv_chip_power9_pec_realize(PnvChip *chip, Error **errp)
1426 {
1427 Pnv9Chip *chip9 = PNV9_CHIP(chip);
1428 int i;
1429
1430 for (i = 0; i < chip->num_pecs; i++) {
1431 PnvPhb4PecState *pec = &chip9->pecs[i];
1432 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
1433 uint32_t pec_nest_base;
1434 uint32_t pec_pci_base;
1435
1436 object_property_set_int(OBJECT(pec), "index", i, &error_fatal);
1437 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id,
1438 &error_fatal);
1439 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip),
1440 &error_fatal);
1441 if (!qdev_realize(DEVICE(pec), NULL, errp)) {
1442 return;
1443 }
1444
1445 pec_nest_base = pecc->xscom_nest_base(pec);
1446 pec_pci_base = pecc->xscom_pci_base(pec);
1447
1448 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr);
1449 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr);
1450 }
1451 }
1452
1453 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
1454 {
1455 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1456 Pnv9Chip *chip9 = PNV9_CHIP(dev);
1457 PnvChip *chip = PNV_CHIP(dev);
1458 Pnv9Psi *psi9 = &chip9->psi;
1459 Error *local_err = NULL;
1460
1461 /* XSCOM bridge is first */
1462 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err);
1463 if (local_err) {
1464 error_propagate(errp, local_err);
1465 return;
1466 }
1467 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip));
1468
1469 pcc->parent_realize(dev, &local_err);
1470 if (local_err) {
1471 error_propagate(errp, local_err);
1472 return;
1473 }
1474
1475 pnv_chip_quad_realize(chip9, &local_err);
1476 if (local_err) {
1477 error_propagate(errp, local_err);
1478 return;
1479 }
1480
1481 /* XIVE interrupt controller (POWER9) */
1482 object_property_set_int(OBJECT(&chip9->xive), "ic-bar",
1483 PNV9_XIVE_IC_BASE(chip), &error_fatal);
1484 object_property_set_int(OBJECT(&chip9->xive), "vc-bar",
1485 PNV9_XIVE_VC_BASE(chip), &error_fatal);
1486 object_property_set_int(OBJECT(&chip9->xive), "pc-bar",
1487 PNV9_XIVE_PC_BASE(chip), &error_fatal);
1488 object_property_set_int(OBJECT(&chip9->xive), "tm-bar",
1489 PNV9_XIVE_TM_BASE(chip), &error_fatal);
1490 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip),
1491 &error_abort);
1492 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) {
1493 return;
1494 }
1495 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE,
1496 &chip9->xive.xscom_regs);
1497
1498 /* Processor Service Interface (PSI) Host Bridge */
1499 object_property_set_int(OBJECT(&chip9->psi), "bar", PNV9_PSIHB_BASE(chip),
1500 &error_fatal);
1501 /* This is the only device with 4k ESB pages */
1502 object_property_set_int(OBJECT(&chip9->psi), "shift", XIVE_ESB_4K,
1503 &error_fatal);
1504 if (!qdev_realize(DEVICE(&chip9->psi), NULL, errp)) {
1505 return;
1506 }
1507 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE,
1508 &PNV_PSI(psi9)->xscom_regs);
1509
1510 /* LPC */
1511 object_property_set_link(OBJECT(&chip9->lpc), "psi", OBJECT(&chip9->psi),
1512 &error_abort);
1513 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) {
1514 return;
1515 }
1516 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip),
1517 &chip9->lpc.xscom_regs);
1518
1519 chip->fw_mr = &chip9->lpc.isa_fw;
1520 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
1521 (uint64_t) PNV9_LPCM_BASE(chip));
1522
1523 /* Create the simplified OCC model */
1524 object_property_set_link(OBJECT(&chip9->occ), "psi", OBJECT(&chip9->psi),
1525 &error_abort);
1526 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) {
1527 return;
1528 }
1529 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs);
1530
1531 /* OCC SRAM model */
1532 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip),
1533 &chip9->occ.sram_regs);
1534
1535 /* HOMER */
1536 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip),
1537 &error_abort);
1538 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) {
1539 return;
1540 }
1541 /* Homer Xscom region */
1542 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs);
1543
1544 /* Homer mmio region */
1545 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip),
1546 &chip9->homer.regs);
1547
1548 /* PEC PHBs */
1549 pnv_chip_power9_pec_realize(chip, &local_err);
1550 if (local_err) {
1551 error_propagate(errp, local_err);
1552 return;
1553 }
1554 }
1555
1556 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr)
1557 {
1558 addr &= (PNV9_XSCOM_SIZE - 1);
1559 return addr >> 3;
1560 }
1561
1562 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
1563 {
1564 DeviceClass *dc = DEVICE_CLASS(klass);
1565 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1566
1567 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */
1568 k->cores_mask = POWER9_CORE_MASK;
1569 k->core_pir = pnv_chip_core_pir_p9;
1570 k->intc_create = pnv_chip_power9_intc_create;
1571 k->intc_reset = pnv_chip_power9_intc_reset;
1572 k->intc_destroy = pnv_chip_power9_intc_destroy;
1573 k->intc_print_info = pnv_chip_power9_intc_print_info;
1574 k->isa_create = pnv_chip_power9_isa_create;
1575 k->dt_populate = pnv_chip_power9_dt_populate;
1576 k->pic_print_info = pnv_chip_power9_pic_print_info;
1577 k->xscom_core_base = pnv_chip_power9_xscom_core_base;
1578 k->xscom_pcba = pnv_chip_power9_xscom_pcba;
1579 dc->desc = "PowerNV Chip POWER9";
1580 k->num_pecs = PNV9_CHIP_MAX_PEC;
1581
1582 device_class_set_parent_realize(dc, pnv_chip_power9_realize,
1583 &k->parent_realize);
1584 }
1585
1586 static void pnv_chip_power10_instance_init(Object *obj)
1587 {
1588 PnvChip *chip = PNV_CHIP(obj);
1589 Pnv10Chip *chip10 = PNV10_CHIP(obj);
1590 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
1591 int i;
1592
1593 object_initialize_child(obj, "xive", &chip10->xive, TYPE_PNV_XIVE2);
1594 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip10->xive),
1595 "xive-fabric");
1596 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI);
1597 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC);
1598 object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC);
1599 object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER);
1600
1601 chip->num_pecs = pcc->num_pecs;
1602
1603 for (i = 0; i < chip->num_pecs; i++) {
1604 object_initialize_child(obj, "pec[*]", &chip10->pecs[i],
1605 TYPE_PNV_PHB5_PEC);
1606 }
1607 }
1608
1609 static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp)
1610 {
1611 PnvChip *chip = PNV_CHIP(chip10);
1612 int i;
1613
1614 chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4);
1615 chip10->quads = g_new0(PnvQuad, chip10->nr_quads);
1616
1617 for (i = 0; i < chip10->nr_quads; i++) {
1618 PnvQuad *eq = &chip10->quads[i];
1619
1620 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]);
1621
1622 pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id),
1623 &eq->xscom_regs);
1624 }
1625 }
1626
1627 static void pnv_chip_power10_phb_realize(PnvChip *chip, Error **errp)
1628 {
1629 Pnv10Chip *chip10 = PNV10_CHIP(chip);
1630 int i;
1631
1632 for (i = 0; i < chip->num_pecs; i++) {
1633 PnvPhb4PecState *pec = &chip10->pecs[i];
1634 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
1635 uint32_t pec_nest_base;
1636 uint32_t pec_pci_base;
1637
1638 object_property_set_int(OBJECT(pec), "index", i, &error_fatal);
1639 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id,
1640 &error_fatal);
1641 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip),
1642 &error_fatal);
1643 if (!qdev_realize(DEVICE(pec), NULL, errp)) {
1644 return;
1645 }
1646
1647 pec_nest_base = pecc->xscom_nest_base(pec);
1648 pec_pci_base = pecc->xscom_pci_base(pec);
1649
1650 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr);
1651 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr);
1652 }
1653 }
1654
1655 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
1656 {
1657 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1658 PnvChip *chip = PNV_CHIP(dev);
1659 Pnv10Chip *chip10 = PNV10_CHIP(dev);
1660 Error *local_err = NULL;
1661
1662 /* XSCOM bridge is first */
1663 pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err);
1664 if (local_err) {
1665 error_propagate(errp, local_err);
1666 return;
1667 }
1668 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip));
1669
1670 pcc->parent_realize(dev, &local_err);
1671 if (local_err) {
1672 error_propagate(errp, local_err);
1673 return;
1674 }
1675
1676 pnv_chip_power10_quad_realize(chip10, &local_err);
1677 if (local_err) {
1678 error_propagate(errp, local_err);
1679 return;
1680 }
1681
1682 /* XIVE2 interrupt controller (POWER10) */
1683 object_property_set_int(OBJECT(&chip10->xive), "ic-bar",
1684 PNV10_XIVE2_IC_BASE(chip), &error_fatal);
1685 object_property_set_int(OBJECT(&chip10->xive), "esb-bar",
1686 PNV10_XIVE2_ESB_BASE(chip), &error_fatal);
1687 object_property_set_int(OBJECT(&chip10->xive), "end-bar",
1688 PNV10_XIVE2_END_BASE(chip), &error_fatal);
1689 object_property_set_int(OBJECT(&chip10->xive), "nvpg-bar",
1690 PNV10_XIVE2_NVPG_BASE(chip), &error_fatal);
1691 object_property_set_int(OBJECT(&chip10->xive), "nvc-bar",
1692 PNV10_XIVE2_NVC_BASE(chip), &error_fatal);
1693 object_property_set_int(OBJECT(&chip10->xive), "tm-bar",
1694 PNV10_XIVE2_TM_BASE(chip), &error_fatal);
1695 object_property_set_link(OBJECT(&chip10->xive), "chip", OBJECT(chip),
1696 &error_abort);
1697 if (!sysbus_realize(SYS_BUS_DEVICE(&chip10->xive), errp)) {
1698 return;
1699 }
1700 pnv_xscom_add_subregion(chip, PNV10_XSCOM_XIVE2_BASE,
1701 &chip10->xive.xscom_regs);
1702
1703 /* Processor Service Interface (PSI) Host Bridge */
1704 object_property_set_int(OBJECT(&chip10->psi), "bar",
1705 PNV10_PSIHB_BASE(chip), &error_fatal);
1706 /* PSI can now be configured to use 64k ESB pages on POWER10 */
1707 object_property_set_int(OBJECT(&chip10->psi), "shift", XIVE_ESB_64K,
1708 &error_fatal);
1709 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) {
1710 return;
1711 }
1712 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE,
1713 &PNV_PSI(&chip10->psi)->xscom_regs);
1714
1715 /* LPC */
1716 object_property_set_link(OBJECT(&chip10->lpc), "psi",
1717 OBJECT(&chip10->psi), &error_abort);
1718 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) {
1719 return;
1720 }
1721 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip),
1722 &chip10->lpc.xscom_regs);
1723
1724 chip->fw_mr = &chip10->lpc.isa_fw;
1725 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
1726 (uint64_t) PNV10_LPCM_BASE(chip));
1727
1728 /* Create the simplified OCC model */
1729 object_property_set_link(OBJECT(&chip10->occ), "psi", OBJECT(&chip10->psi),
1730 &error_abort);
1731 if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) {
1732 return;
1733 }
1734 pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE,
1735 &chip10->occ.xscom_regs);
1736
1737 /* OCC SRAM model */
1738 memory_region_add_subregion(get_system_memory(),
1739 PNV10_OCC_SENSOR_BASE(chip),
1740 &chip10->occ.sram_regs);
1741
1742 /* HOMER */
1743 object_property_set_link(OBJECT(&chip10->homer), "chip", OBJECT(chip),
1744 &error_abort);
1745 if (!qdev_realize(DEVICE(&chip10->homer), NULL, errp)) {
1746 return;
1747 }
1748 /* Homer Xscom region */
1749 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PBA_BASE,
1750 &chip10->homer.pba_regs);
1751
1752 /* Homer mmio region */
1753 memory_region_add_subregion(get_system_memory(), PNV10_HOMER_BASE(chip),
1754 &chip10->homer.regs);
1755
1756 /* PHBs */
1757 pnv_chip_power10_phb_realize(chip, &local_err);
1758 if (local_err) {
1759 error_propagate(errp, local_err);
1760 return;
1761 }
1762 }
1763
1764 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr)
1765 {
1766 addr &= (PNV10_XSCOM_SIZE - 1);
1767 return addr >> 3;
1768 }
1769
1770 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data)
1771 {
1772 DeviceClass *dc = DEVICE_CLASS(klass);
1773 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1774
1775 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */
1776 k->cores_mask = POWER10_CORE_MASK;
1777 k->core_pir = pnv_chip_core_pir_p10;
1778 k->intc_create = pnv_chip_power10_intc_create;
1779 k->intc_reset = pnv_chip_power10_intc_reset;
1780 k->intc_destroy = pnv_chip_power10_intc_destroy;
1781 k->intc_print_info = pnv_chip_power10_intc_print_info;
1782 k->isa_create = pnv_chip_power10_isa_create;
1783 k->dt_populate = pnv_chip_power10_dt_populate;
1784 k->pic_print_info = pnv_chip_power10_pic_print_info;
1785 k->xscom_core_base = pnv_chip_power10_xscom_core_base;
1786 k->xscom_pcba = pnv_chip_power10_xscom_pcba;
1787 dc->desc = "PowerNV Chip POWER10";
1788 k->num_pecs = PNV10_CHIP_MAX_PEC;
1789
1790 device_class_set_parent_realize(dc, pnv_chip_power10_realize,
1791 &k->parent_realize);
1792 }
1793
1794 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp)
1795 {
1796 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1797 int cores_max;
1798
1799 /*
1800 * No custom mask for this chip, let's use the default one from *
1801 * the chip class
1802 */
1803 if (!chip->cores_mask) {
1804 chip->cores_mask = pcc->cores_mask;
1805 }
1806
1807 /* filter alien core ids ! some are reserved */
1808 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) {
1809 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !",
1810 chip->cores_mask);
1811 return;
1812 }
1813 chip->cores_mask &= pcc->cores_mask;
1814
1815 /* now that we have a sane layout, let check the number of cores */
1816 cores_max = ctpop64(chip->cores_mask);
1817 if (chip->nr_cores > cores_max) {
1818 error_setg(errp, "warning: too many cores for chip ! Limit is %d",
1819 cores_max);
1820 return;
1821 }
1822 }
1823
1824 static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
1825 {
1826 Error *error = NULL;
1827 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1828 const char *typename = pnv_chip_core_typename(chip);
1829 int i, core_hwid;
1830 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
1831
1832 if (!object_class_by_name(typename)) {
1833 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename);
1834 return;
1835 }
1836
1837 /* Cores */
1838 pnv_chip_core_sanitize(chip, &error);
1839 if (error) {
1840 error_propagate(errp, error);
1841 return;
1842 }
1843
1844 chip->cores = g_new0(PnvCore *, chip->nr_cores);
1845
1846 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8)
1847 && (i < chip->nr_cores); core_hwid++) {
1848 char core_name[32];
1849 PnvCore *pnv_core;
1850 uint64_t xscom_core_base;
1851
1852 if (!(chip->cores_mask & (1ull << core_hwid))) {
1853 continue;
1854 }
1855
1856 pnv_core = PNV_CORE(object_new(typename));
1857
1858 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid);
1859 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core));
1860 chip->cores[i] = pnv_core;
1861 object_property_set_int(OBJECT(pnv_core), "nr-threads",
1862 chip->nr_threads, &error_fatal);
1863 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID,
1864 core_hwid, &error_fatal);
1865 object_property_set_int(OBJECT(pnv_core), "pir",
1866 pcc->core_pir(chip, core_hwid), &error_fatal);
1867 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr,
1868 &error_fatal);
1869 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip),
1870 &error_abort);
1871 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal);
1872
1873 /* Each core has an XSCOM MMIO region */
1874 xscom_core_base = pcc->xscom_core_base(chip, core_hwid);
1875
1876 pnv_xscom_add_subregion(chip, xscom_core_base,
1877 &pnv_core->xscom_regs);
1878 i++;
1879 }
1880 }
1881
1882 static void pnv_chip_realize(DeviceState *dev, Error **errp)
1883 {
1884 PnvChip *chip = PNV_CHIP(dev);
1885 Error *error = NULL;
1886
1887 /* Cores */
1888 pnv_chip_core_realize(chip, &error);
1889 if (error) {
1890 error_propagate(errp, error);
1891 return;
1892 }
1893 }
1894
1895 static Property pnv_chip_properties[] = {
1896 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0),
1897 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0),
1898 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0),
1899 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1),
1900 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0),
1901 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1),
1902 DEFINE_PROP_END_OF_LIST(),
1903 };
1904
1905 static void pnv_chip_class_init(ObjectClass *klass, void *data)
1906 {
1907 DeviceClass *dc = DEVICE_CLASS(klass);
1908
1909 set_bit(DEVICE_CATEGORY_CPU, dc->categories);
1910 dc->realize = pnv_chip_realize;
1911 device_class_set_props(dc, pnv_chip_properties);
1912 dc->desc = "PowerNV Chip";
1913 }
1914
1915 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir)
1916 {
1917 int i, j;
1918
1919 for (i = 0; i < chip->nr_cores; i++) {
1920 PnvCore *pc = chip->cores[i];
1921 CPUCore *cc = CPU_CORE(pc);
1922
1923 for (j = 0; j < cc->nr_threads; j++) {
1924 if (ppc_cpu_pir(pc->threads[j]) == pir) {
1925 return pc->threads[j];
1926 }
1927 }
1928 }
1929 return NULL;
1930 }
1931
1932 typedef struct ForeachPhb3Args {
1933 int irq;
1934 ICSState *ics;
1935 } ForeachPhb3Args;
1936
1937 static int pnv_ics_get_child(Object *child, void *opaque)
1938 {
1939 ForeachPhb3Args *args = opaque;
1940 PnvPHB3 *phb3 = (PnvPHB3 *) object_dynamic_cast(child, TYPE_PNV_PHB3);
1941
1942 if (phb3) {
1943 if (ics_valid_irq(&phb3->lsis, args->irq)) {
1944 args->ics = &phb3->lsis;
1945 }
1946 if (ics_valid_irq(ICS(&phb3->msis), args->irq)) {
1947 args->ics = ICS(&phb3->msis);
1948 }
1949 }
1950 return args->ics ? 1 : 0;
1951 }
1952
1953 static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
1954 {
1955 PnvMachineState *pnv = PNV_MACHINE(xi);
1956 ForeachPhb3Args args = { irq, NULL };
1957 int i;
1958
1959 for (i = 0; i < pnv->num_chips; i++) {
1960 PnvChip *chip = pnv->chips[i];
1961 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
1962
1963 if (ics_valid_irq(&chip8->psi.ics, irq)) {
1964 return &chip8->psi.ics;
1965 }
1966
1967 object_child_foreach(OBJECT(chip), pnv_ics_get_child, &args);
1968 if (args.ics) {
1969 return args.ics;
1970 }
1971 }
1972 return NULL;
1973 }
1974
1975 PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id)
1976 {
1977 int i;
1978
1979 for (i = 0; i < pnv->num_chips; i++) {
1980 PnvChip *chip = pnv->chips[i];
1981 if (chip->chip_id == chip_id) {
1982 return chip;
1983 }
1984 }
1985 return NULL;
1986 }
1987
1988 static int pnv_ics_resend_child(Object *child, void *opaque)
1989 {
1990 PnvPHB3 *phb3 = (PnvPHB3 *) object_dynamic_cast(child, TYPE_PNV_PHB3);
1991
1992 if (phb3) {
1993 ics_resend(&phb3->lsis);
1994 ics_resend(ICS(&phb3->msis));
1995 }
1996 return 0;
1997 }
1998
1999 static void pnv_ics_resend(XICSFabric *xi)
2000 {
2001 PnvMachineState *pnv = PNV_MACHINE(xi);
2002 int i;
2003
2004 for (i = 0; i < pnv->num_chips; i++) {
2005 PnvChip *chip = pnv->chips[i];
2006 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
2007
2008 ics_resend(&chip8->psi.ics);
2009 object_child_foreach(OBJECT(chip), pnv_ics_resend_child, NULL);
2010 }
2011 }
2012
2013 static ICPState *pnv_icp_get(XICSFabric *xi, int pir)
2014 {
2015 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir);
2016
2017 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL;
2018 }
2019
2020 static void pnv_pic_print_info(InterruptStatsProvider *obj,
2021 Monitor *mon)
2022 {
2023 PnvMachineState *pnv = PNV_MACHINE(obj);
2024 int i;
2025 CPUState *cs;
2026
2027 CPU_FOREACH(cs) {
2028 PowerPCCPU *cpu = POWERPC_CPU(cs);
2029
2030 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */
2031 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu,
2032 mon);
2033 }
2034
2035 for (i = 0; i < pnv->num_chips; i++) {
2036 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon);
2037 }
2038 }
2039
2040 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format,
2041 uint8_t nvt_blk, uint32_t nvt_idx,
2042 bool cam_ignore, uint8_t priority,
2043 uint32_t logic_serv,
2044 XiveTCTXMatch *match)
2045 {
2046 PnvMachineState *pnv = PNV_MACHINE(xfb);
2047 int total_count = 0;
2048 int i;
2049
2050 for (i = 0; i < pnv->num_chips; i++) {
2051 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]);
2052 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive);
2053 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
2054 int count;
2055
2056 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore,
2057 priority, logic_serv, match);
2058
2059 if (count < 0) {
2060 return count;
2061 }
2062
2063 total_count += count;
2064 }
2065
2066 return total_count;
2067 }
2068
2069 static int pnv10_xive_match_nvt(XiveFabric *xfb, uint8_t format,
2070 uint8_t nvt_blk, uint32_t nvt_idx,
2071 bool cam_ignore, uint8_t priority,
2072 uint32_t logic_serv,
2073 XiveTCTXMatch *match)
2074 {
2075 PnvMachineState *pnv = PNV_MACHINE(xfb);
2076 int total_count = 0;
2077 int i;
2078
2079 for (i = 0; i < pnv->num_chips; i++) {
2080 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]);
2081 XivePresenter *xptr = XIVE_PRESENTER(&chip10->xive);
2082 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
2083 int count;
2084
2085 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore,
2086 priority, logic_serv, match);
2087
2088 if (count < 0) {
2089 return count;
2090 }
2091
2092 total_count += count;
2093 }
2094
2095 return total_count;
2096 }
2097
2098 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data)
2099 {
2100 MachineClass *mc = MACHINE_CLASS(oc);
2101 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
2102 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
2103 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv";
2104
2105 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8";
2106 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
2107
2108 xic->icp_get = pnv_icp_get;
2109 xic->ics_get = pnv_ics_get;
2110 xic->ics_resend = pnv_ics_resend;
2111
2112 pmc->compat = compat;
2113 pmc->compat_size = sizeof(compat);
2114 }
2115
2116 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data)
2117 {
2118 MachineClass *mc = MACHINE_CLASS(oc);
2119 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
2120 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
2121 static const char compat[] = "qemu,powernv9\0ibm,powernv";
2122
2123 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9";
2124 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0");
2125 xfc->match_nvt = pnv_match_nvt;
2126
2127 mc->alias = "powernv";
2128
2129 pmc->compat = compat;
2130 pmc->compat_size = sizeof(compat);
2131 pmc->dt_power_mgt = pnv_dt_power_mgt;
2132 }
2133
2134 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data)
2135 {
2136 MachineClass *mc = MACHINE_CLASS(oc);
2137 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
2138 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
2139 static const char compat[] = "qemu,powernv10\0ibm,powernv";
2140
2141 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10";
2142 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0");
2143
2144 pmc->compat = compat;
2145 pmc->compat_size = sizeof(compat);
2146 pmc->dt_power_mgt = pnv_dt_power_mgt;
2147
2148 xfc->match_nvt = pnv10_xive_match_nvt;
2149 }
2150
2151 static bool pnv_machine_get_hb(Object *obj, Error **errp)
2152 {
2153 PnvMachineState *pnv = PNV_MACHINE(obj);
2154
2155 return !!pnv->fw_load_addr;
2156 }
2157
2158 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp)
2159 {
2160 PnvMachineState *pnv = PNV_MACHINE(obj);
2161
2162 if (value) {
2163 pnv->fw_load_addr = 0x8000000;
2164 }
2165 }
2166
2167 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg)
2168 {
2169 PowerPCCPU *cpu = POWERPC_CPU(cs);
2170 CPUPPCState *env = &cpu->env;
2171
2172 cpu_synchronize_state(cs);
2173 ppc_cpu_do_system_reset(cs);
2174 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) {
2175 /*
2176 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the
2177 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100
2178 * (PPC_BIT(43)).
2179 */
2180 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) {
2181 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason");
2182 env->spr[SPR_SRR1] |= SRR1_WAKERESET;
2183 }
2184 } else {
2185 /*
2186 * For non-powersave system resets, SRR1[42:45] are defined to be
2187 * implementation-dependent. The POWER9 User Manual specifies that
2188 * an external (SCOM driven, which may come from a BMC nmi command or
2189 * another CPU requesting a NMI IPI) system reset exception should be
2190 * 0b0010 (PPC_BIT(44)).
2191 */
2192 env->spr[SPR_SRR1] |= SRR1_WAKESCOM;
2193 }
2194 }
2195
2196 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp)
2197 {
2198 CPUState *cs;
2199
2200 CPU_FOREACH(cs) {
2201 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL);
2202 }
2203 }
2204
2205 static void pnv_machine_class_init(ObjectClass *oc, void *data)
2206 {
2207 MachineClass *mc = MACHINE_CLASS(oc);
2208 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
2209 NMIClass *nc = NMI_CLASS(oc);
2210
2211 mc->desc = "IBM PowerNV (Non-Virtualized)";
2212 mc->init = pnv_init;
2213 mc->reset = pnv_reset;
2214 mc->max_cpus = MAX_CPUS;
2215 /* Pnv provides a AHCI device for storage */
2216 mc->block_default_type = IF_IDE;
2217 mc->no_parallel = 1;
2218 mc->default_boot_order = NULL;
2219 /*
2220 * RAM defaults to less than 2048 for 32-bit hosts, and large
2221 * enough to fit the maximum initrd size at it's load address
2222 */
2223 mc->default_ram_size = 1 * GiB;
2224 mc->default_ram_id = "pnv.ram";
2225 ispc->print_info = pnv_pic_print_info;
2226 nc->nmi_monitor_handler = pnv_nmi;
2227
2228 object_class_property_add_bool(oc, "hb-mode",
2229 pnv_machine_get_hb, pnv_machine_set_hb);
2230 object_class_property_set_description(oc, "hb-mode",
2231 "Use a hostboot like boot loader");
2232 }
2233
2234 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \
2235 { \
2236 .name = type, \
2237 .class_init = class_initfn, \
2238 .parent = TYPE_PNV8_CHIP, \
2239 }
2240
2241 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \
2242 { \
2243 .name = type, \
2244 .class_init = class_initfn, \
2245 .parent = TYPE_PNV9_CHIP, \
2246 }
2247
2248 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \
2249 { \
2250 .name = type, \
2251 .class_init = class_initfn, \
2252 .parent = TYPE_PNV10_CHIP, \
2253 }
2254
2255 static const TypeInfo types[] = {
2256 {
2257 .name = MACHINE_TYPE_NAME("powernv10"),
2258 .parent = TYPE_PNV_MACHINE,
2259 .class_init = pnv_machine_power10_class_init,
2260 .interfaces = (InterfaceInfo[]) {
2261 { TYPE_XIVE_FABRIC },
2262 { },
2263 },
2264 },
2265 {
2266 .name = MACHINE_TYPE_NAME("powernv9"),
2267 .parent = TYPE_PNV_MACHINE,
2268 .class_init = pnv_machine_power9_class_init,
2269 .interfaces = (InterfaceInfo[]) {
2270 { TYPE_XIVE_FABRIC },
2271 { },
2272 },
2273 },
2274 {
2275 .name = MACHINE_TYPE_NAME("powernv8"),
2276 .parent = TYPE_PNV_MACHINE,
2277 .class_init = pnv_machine_power8_class_init,
2278 .interfaces = (InterfaceInfo[]) {
2279 { TYPE_XICS_FABRIC },
2280 { },
2281 },
2282 },
2283 {
2284 .name = TYPE_PNV_MACHINE,
2285 .parent = TYPE_MACHINE,
2286 .abstract = true,
2287 .instance_size = sizeof(PnvMachineState),
2288 .class_init = pnv_machine_class_init,
2289 .class_size = sizeof(PnvMachineClass),
2290 .interfaces = (InterfaceInfo[]) {
2291 { TYPE_INTERRUPT_STATS_PROVIDER },
2292 { TYPE_NMI },
2293 { },
2294 },
2295 },
2296 {
2297 .name = TYPE_PNV_CHIP,
2298 .parent = TYPE_SYS_BUS_DEVICE,
2299 .class_init = pnv_chip_class_init,
2300 .instance_size = sizeof(PnvChip),
2301 .class_size = sizeof(PnvChipClass),
2302 .abstract = true,
2303 },
2304
2305 /*
2306 * P10 chip and variants
2307 */
2308 {
2309 .name = TYPE_PNV10_CHIP,
2310 .parent = TYPE_PNV_CHIP,
2311 .instance_init = pnv_chip_power10_instance_init,
2312 .instance_size = sizeof(Pnv10Chip),
2313 },
2314 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init),
2315
2316 /*
2317 * P9 chip and variants
2318 */
2319 {
2320 .name = TYPE_PNV9_CHIP,
2321 .parent = TYPE_PNV_CHIP,
2322 .instance_init = pnv_chip_power9_instance_init,
2323 .instance_size = sizeof(Pnv9Chip),
2324 },
2325 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init),
2326
2327 /*
2328 * P8 chip and variants
2329 */
2330 {
2331 .name = TYPE_PNV8_CHIP,
2332 .parent = TYPE_PNV_CHIP,
2333 .instance_init = pnv_chip_power8_instance_init,
2334 .instance_size = sizeof(Pnv8Chip),
2335 },
2336 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init),
2337 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init),
2338 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL,
2339 pnv_chip_power8nvl_class_init),
2340 };
2341
2342 DEFINE_TYPES(types)
QEmu