2 * "Inventra" High-speed Dual-Role Controller (MUSB-HDRC), Mentor Graphics,
3 * USB2.0 OTG compliant core used in various chips.
5 * Copyright (C) 2008 Nokia Corporation
6 * Written by Andrzej Zaborowski <andrew@openedhand.com>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 or
11 * (at your option) version 3 of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 * Only host-mode and non-DMA accesses are currently supported.
23 #include "qemu-common.h"
24 #include "qemu-timer.h"
29 /* Common USB registers */
30 #define MUSB_HDRC_FADDR 0x00 /* 8-bit */
31 #define MUSB_HDRC_POWER 0x01 /* 8-bit */
33 #define MUSB_HDRC_INTRTX 0x02 /* 16-bit */
34 #define MUSB_HDRC_INTRRX 0x04
35 #define MUSB_HDRC_INTRTXE 0x06
36 #define MUSB_HDRC_INTRRXE 0x08
37 #define MUSB_HDRC_INTRUSB 0x0a /* 8 bit */
38 #define MUSB_HDRC_INTRUSBE 0x0b /* 8 bit */
39 #define MUSB_HDRC_FRAME 0x0c /* 16-bit */
40 #define MUSB_HDRC_INDEX 0x0e /* 8 bit */
41 #define MUSB_HDRC_TESTMODE 0x0f /* 8 bit */
43 /* Per-EP registers in indexed mode */
44 #define MUSB_HDRC_EP_IDX 0x10 /* 8-bit */
47 #define MUSB_HDRC_FIFO 0x20
49 /* Additional Control Registers */
50 #define MUSB_HDRC_DEVCTL 0x60 /* 8 bit */
52 /* These are indexed */
53 #define MUSB_HDRC_TXFIFOSZ 0x62 /* 8 bit (see masks) */
54 #define MUSB_HDRC_RXFIFOSZ 0x63 /* 8 bit (see masks) */
55 #define MUSB_HDRC_TXFIFOADDR 0x64 /* 16 bit offset shifted right 3 */
56 #define MUSB_HDRC_RXFIFOADDR 0x66 /* 16 bit offset shifted right 3 */
58 /* Some more registers */
59 #define MUSB_HDRC_VCTRL 0x68 /* 8 bit */
60 #define MUSB_HDRC_HWVERS 0x6c /* 8 bit */
62 /* Added in HDRC 1.9(?) & MHDRC 1.4 */
63 /* ULPI pass-through */
64 #define MUSB_HDRC_ULPI_VBUSCTL 0x70
65 #define MUSB_HDRC_ULPI_REGDATA 0x74
66 #define MUSB_HDRC_ULPI_REGADDR 0x75
67 #define MUSB_HDRC_ULPI_REGCTL 0x76
69 /* Extended config & PHY control */
70 #define MUSB_HDRC_ENDCOUNT 0x78 /* 8 bit */
71 #define MUSB_HDRC_DMARAMCFG 0x79 /* 8 bit */
72 #define MUSB_HDRC_PHYWAIT 0x7a /* 8 bit */
73 #define MUSB_HDRC_PHYVPLEN 0x7b /* 8 bit */
74 #define MUSB_HDRC_HS_EOF1 0x7c /* 8 bit, units of 546.1 us */
75 #define MUSB_HDRC_FS_EOF1 0x7d /* 8 bit, units of 533.3 ns */
76 #define MUSB_HDRC_LS_EOF1 0x7e /* 8 bit, units of 1.067 us */
78 /* Per-EP BUSCTL registers */
79 #define MUSB_HDRC_BUSCTL 0x80
81 /* Per-EP registers in flat mode */
82 #define MUSB_HDRC_EP 0x100
84 /* offsets to registers in flat model */
85 #define MUSB_HDRC_TXMAXP 0x00 /* 16 bit apparently */
86 #define MUSB_HDRC_TXCSR 0x02 /* 16 bit apparently */
87 #define MUSB_HDRC_CSR0 MUSB_HDRC_TXCSR /* re-used for EP0 */
88 #define MUSB_HDRC_RXMAXP 0x04 /* 16 bit apparently */
89 #define MUSB_HDRC_RXCSR 0x06 /* 16 bit apparently */
90 #define MUSB_HDRC_RXCOUNT 0x08 /* 16 bit apparently */
91 #define MUSB_HDRC_COUNT0 MUSB_HDRC_RXCOUNT /* re-used for EP0 */
92 #define MUSB_HDRC_TXTYPE 0x0a /* 8 bit apparently */
93 #define MUSB_HDRC_TYPE0 MUSB_HDRC_TXTYPE /* re-used for EP0 */
94 #define MUSB_HDRC_TXINTERVAL 0x0b /* 8 bit apparently */
95 #define MUSB_HDRC_NAKLIMIT0 MUSB_HDRC_TXINTERVAL /* re-used for EP0 */
96 #define MUSB_HDRC_RXTYPE 0x0c /* 8 bit apparently */
97 #define MUSB_HDRC_RXINTERVAL 0x0d /* 8 bit apparently */
98 #define MUSB_HDRC_FIFOSIZE 0x0f /* 8 bit apparently */
99 #define MUSB_HDRC_CONFIGDATA MGC_O_HDRC_FIFOSIZE /* re-used for EP0 */
101 /* "Bus control" registers */
102 #define MUSB_HDRC_TXFUNCADDR 0x00
103 #define MUSB_HDRC_TXHUBADDR 0x02
104 #define MUSB_HDRC_TXHUBPORT 0x03
106 #define MUSB_HDRC_RXFUNCADDR 0x04
107 #define MUSB_HDRC_RXHUBADDR 0x06
108 #define MUSB_HDRC_RXHUBPORT 0x07
111 * MUSBHDRC Register bit masks
115 #define MGC_M_POWER_ISOUPDATE 0x80
116 #define MGC_M_POWER_SOFTCONN 0x40
117 #define MGC_M_POWER_HSENAB 0x20
118 #define MGC_M_POWER_HSMODE 0x10
119 #define MGC_M_POWER_RESET 0x08
120 #define MGC_M_POWER_RESUME 0x04
121 #define MGC_M_POWER_SUSPENDM 0x02
122 #define MGC_M_POWER_ENSUSPEND 0x01
125 #define MGC_M_INTR_SUSPEND 0x01
126 #define MGC_M_INTR_RESUME 0x02
127 #define MGC_M_INTR_RESET 0x04
128 #define MGC_M_INTR_BABBLE 0x04
129 #define MGC_M_INTR_SOF 0x08
130 #define MGC_M_INTR_CONNECT 0x10
131 #define MGC_M_INTR_DISCONNECT 0x20
132 #define MGC_M_INTR_SESSREQ 0x40
133 #define MGC_M_INTR_VBUSERROR 0x80 /* FOR SESSION END */
134 #define MGC_M_INTR_EP0 0x01 /* FOR EP0 INTERRUPT */
137 #define MGC_M_DEVCTL_BDEVICE 0x80
138 #define MGC_M_DEVCTL_FSDEV 0x40
139 #define MGC_M_DEVCTL_LSDEV 0x20
140 #define MGC_M_DEVCTL_VBUS 0x18
141 #define MGC_S_DEVCTL_VBUS 3
142 #define MGC_M_DEVCTL_HM 0x04
143 #define MGC_M_DEVCTL_HR 0x02
144 #define MGC_M_DEVCTL_SESSION 0x01
147 #define MGC_M_TEST_FORCE_HOST 0x80
148 #define MGC_M_TEST_FIFO_ACCESS 0x40
149 #define MGC_M_TEST_FORCE_FS 0x20
150 #define MGC_M_TEST_FORCE_HS 0x10
151 #define MGC_M_TEST_PACKET 0x08
152 #define MGC_M_TEST_K 0x04
153 #define MGC_M_TEST_J 0x02
154 #define MGC_M_TEST_SE0_NAK 0x01
157 #define MGC_M_CSR0_FLUSHFIFO 0x0100
158 #define MGC_M_CSR0_TXPKTRDY 0x0002
159 #define MGC_M_CSR0_RXPKTRDY 0x0001
161 /* CSR0 in Peripheral mode */
162 #define MGC_M_CSR0_P_SVDSETUPEND 0x0080
163 #define MGC_M_CSR0_P_SVDRXPKTRDY 0x0040
164 #define MGC_M_CSR0_P_SENDSTALL 0x0020
165 #define MGC_M_CSR0_P_SETUPEND 0x0010
166 #define MGC_M_CSR0_P_DATAEND 0x0008
167 #define MGC_M_CSR0_P_SENTSTALL 0x0004
169 /* CSR0 in Host mode */
170 #define MGC_M_CSR0_H_NO_PING 0x0800
171 #define MGC_M_CSR0_H_WR_DATATOGGLE 0x0400 /* set to allow setting: */
172 #define MGC_M_CSR0_H_DATATOGGLE 0x0200 /* data toggle control */
173 #define MGC_M_CSR0_H_NAKTIMEOUT 0x0080
174 #define MGC_M_CSR0_H_STATUSPKT 0x0040
175 #define MGC_M_CSR0_H_REQPKT 0x0020
176 #define MGC_M_CSR0_H_ERROR 0x0010
177 #define MGC_M_CSR0_H_SETUPPKT 0x0008
178 #define MGC_M_CSR0_H_RXSTALL 0x0004
181 #define MGC_M_CONFIGDATA_MPRXE 0x80 /* auto bulk pkt combining */
182 #define MGC_M_CONFIGDATA_MPTXE 0x40 /* auto bulk pkt splitting */
183 #define MGC_M_CONFIGDATA_BIGENDIAN 0x20
184 #define MGC_M_CONFIGDATA_HBRXE 0x10 /* HB-ISO for RX */
185 #define MGC_M_CONFIGDATA_HBTXE 0x08 /* HB-ISO for TX */
186 #define MGC_M_CONFIGDATA_DYNFIFO 0x04 /* dynamic FIFO sizing */
187 #define MGC_M_CONFIGDATA_SOFTCONE 0x02 /* SoftConnect */
188 #define MGC_M_CONFIGDATA_UTMIDW 0x01 /* Width, 0 => 8b, 1 => 16b */
190 /* TXCSR in Peripheral and Host mode */
191 #define MGC_M_TXCSR_AUTOSET 0x8000
192 #define MGC_M_TXCSR_ISO 0x4000
193 #define MGC_M_TXCSR_MODE 0x2000
194 #define MGC_M_TXCSR_DMAENAB 0x1000
195 #define MGC_M_TXCSR_FRCDATATOG 0x0800
196 #define MGC_M_TXCSR_DMAMODE 0x0400
197 #define MGC_M_TXCSR_CLRDATATOG 0x0040
198 #define MGC_M_TXCSR_FLUSHFIFO 0x0008
199 #define MGC_M_TXCSR_FIFONOTEMPTY 0x0002
200 #define MGC_M_TXCSR_TXPKTRDY 0x0001
202 /* TXCSR in Peripheral mode */
203 #define MGC_M_TXCSR_P_INCOMPTX 0x0080
204 #define MGC_M_TXCSR_P_SENTSTALL 0x0020
205 #define MGC_M_TXCSR_P_SENDSTALL 0x0010
206 #define MGC_M_TXCSR_P_UNDERRUN 0x0004
208 /* TXCSR in Host mode */
209 #define MGC_M_TXCSR_H_WR_DATATOGGLE 0x0200
210 #define MGC_M_TXCSR_H_DATATOGGLE 0x0100
211 #define MGC_M_TXCSR_H_NAKTIMEOUT 0x0080
212 #define MGC_M_TXCSR_H_RXSTALL 0x0020
213 #define MGC_M_TXCSR_H_ERROR 0x0004
215 /* RXCSR in Peripheral and Host mode */
216 #define MGC_M_RXCSR_AUTOCLEAR 0x8000
217 #define MGC_M_RXCSR_DMAENAB 0x2000
218 #define MGC_M_RXCSR_DISNYET 0x1000
219 #define MGC_M_RXCSR_DMAMODE 0x0800
220 #define MGC_M_RXCSR_INCOMPRX 0x0100
221 #define MGC_M_RXCSR_CLRDATATOG 0x0080
222 #define MGC_M_RXCSR_FLUSHFIFO 0x0010
223 #define MGC_M_RXCSR_DATAERROR 0x0008
224 #define MGC_M_RXCSR_FIFOFULL 0x0002
225 #define MGC_M_RXCSR_RXPKTRDY 0x0001
227 /* RXCSR in Peripheral mode */
228 #define MGC_M_RXCSR_P_ISO 0x4000
229 #define MGC_M_RXCSR_P_SENTSTALL 0x0040
230 #define MGC_M_RXCSR_P_SENDSTALL 0x0020
231 #define MGC_M_RXCSR_P_OVERRUN 0x0004
233 /* RXCSR in Host mode */
234 #define MGC_M_RXCSR_H_AUTOREQ 0x4000
235 #define MGC_M_RXCSR_H_WR_DATATOGGLE 0x0400
236 #define MGC_M_RXCSR_H_DATATOGGLE 0x0200
237 #define MGC_M_RXCSR_H_RXSTALL 0x0040
238 #define MGC_M_RXCSR_H_REQPKT 0x0020
239 #define MGC_M_RXCSR_H_ERROR 0x0004
242 #define MGC_M_HUBADDR_MULTI_TT 0x80
244 /* ULPI: Added in HDRC 1.9(?) & MHDRC 1.4 */
245 #define MGC_M_ULPI_VBCTL_USEEXTVBUSIND 0x02
246 #define MGC_M_ULPI_VBCTL_USEEXTVBUS 0x01
247 #define MGC_M_ULPI_REGCTL_INT_ENABLE 0x08
248 #define MGC_M_ULPI_REGCTL_READNOTWRITE 0x04
249 #define MGC_M_ULPI_REGCTL_COMPLETE 0x02
250 #define MGC_M_ULPI_REGCTL_REG 0x01
252 /* #define MUSB_DEBUG */
255 #define TRACE(fmt,...) fprintf(stderr, "%s@%d: " fmt "\n", __FUNCTION__, \
256 __LINE__, ##__VA_ARGS__)
262 static void musb_attach(USBPort
*port
);
263 static void musb_detach(USBPort
*port
);
265 static USBPortOps musb_port_ops
= {
266 .attach
= musb_attach
,
267 .detach
= musb_detach
,
281 int timeout
[2]; /* Always in microframes */
291 /* For callbacks' use */
295 USBCallback
*delayed_cb
[2];
296 QEMUTimer
*intv_timer
[2];
321 /* Duplicating the world since 2008!... probably we should have 32
322 * logical, single endpoints instead. */
324 } *musb_init(qemu_irq
*irqs
)
326 MUSBState
*s
= qemu_mallocz(sizeof(*s
));
332 s
->power
= MGC_M_POWER_HSENAB
;
342 s
->ep
[0].config
= MGC_M_CONFIGDATA_SOFTCONE
| MGC_M_CONFIGDATA_DYNFIFO
;
343 for (i
= 0; i
< 16; i
++) {
344 s
->ep
[i
].fifosize
= 64;
345 s
->ep
[i
].maxp
[0] = 0x40;
346 s
->ep
[i
].maxp
[1] = 0x40;
351 usb_bus_new(&s
->bus
, NULL
/* FIXME */);
352 usb_register_port(&s
->bus
, &s
->port
, s
, 0, NULL
, &musb_port_ops
,
353 USB_SPEED_MASK_LOW
| USB_SPEED_MASK_FULL
);
358 static void musb_vbus_set(MUSBState
*s
, int level
)
361 s
->devctl
|= 3 << MGC_S_DEVCTL_VBUS
;
363 s
->devctl
&= ~MGC_M_DEVCTL_VBUS
;
365 qemu_set_irq(s
->irqs
[musb_set_vbus
], level
);
368 static void musb_intr_set(MUSBState
*s
, int line
, int level
)
371 s
->intr
&= ~(1 << line
);
372 qemu_irq_lower(s
->irqs
[line
]);
373 } else if (s
->mask
& (1 << line
)) {
374 s
->intr
|= 1 << line
;
375 qemu_irq_raise(s
->irqs
[line
]);
379 static void musb_tx_intr_set(MUSBState
*s
, int line
, int level
)
382 s
->tx_intr
&= ~(1 << line
);
384 qemu_irq_lower(s
->irqs
[musb_irq_tx
]);
385 } else if (s
->tx_mask
& (1 << line
)) {
386 s
->tx_intr
|= 1 << line
;
387 qemu_irq_raise(s
->irqs
[musb_irq_tx
]);
391 static void musb_rx_intr_set(MUSBState
*s
, int line
, int level
)
395 s
->rx_intr
&= ~(1 << line
);
397 qemu_irq_lower(s
->irqs
[musb_irq_rx
]);
398 } else if (s
->rx_mask
& (1 << line
)) {
399 s
->rx_intr
|= 1 << line
;
400 qemu_irq_raise(s
->irqs
[musb_irq_rx
]);
403 musb_tx_intr_set(s
, line
, level
);
406 uint32_t musb_core_intr_get(MUSBState
*s
)
408 return (s
->rx_intr
<< 15) | s
->tx_intr
;
411 void musb_core_intr_clear(MUSBState
*s
, uint32_t mask
)
414 s
->rx_intr
&= mask
>> 15;
416 qemu_irq_lower(s
->irqs
[musb_irq_rx
]);
420 s
->tx_intr
&= mask
& 0xffff;
422 qemu_irq_lower(s
->irqs
[musb_irq_tx
]);
426 void musb_set_size(MUSBState
*s
, int epnum
, int size
, int is_tx
)
428 s
->ep
[epnum
].ext_size
[!is_tx
] = size
;
429 s
->ep
[epnum
].fifostart
[0] = 0;
430 s
->ep
[epnum
].fifostart
[1] = 0;
431 s
->ep
[epnum
].fifolen
[0] = 0;
432 s
->ep
[epnum
].fifolen
[1] = 0;
435 static void musb_session_update(MUSBState
*s
, int prev_dev
, int prev_sess
)
437 int detect_prev
= prev_dev
&& prev_sess
;
438 int detect
= !!s
->port
.dev
&& s
->session
;
440 if (detect
&& !detect_prev
) {
441 /* Let's skip the ID pin sense and VBUS sense formalities and
442 * and signal a successful SRP directly. This should work at least
443 * for the Linux driver stack. */
444 musb_intr_set(s
, musb_irq_connect
, 1);
446 if (s
->port
.dev
->speed
== USB_SPEED_LOW
) {
447 s
->devctl
&= ~MGC_M_DEVCTL_FSDEV
;
448 s
->devctl
|= MGC_M_DEVCTL_LSDEV
;
450 s
->devctl
|= MGC_M_DEVCTL_FSDEV
;
451 s
->devctl
&= ~MGC_M_DEVCTL_LSDEV
;
455 s
->devctl
&= ~MGC_M_DEVCTL_BDEVICE
;
458 s
->devctl
|= MGC_M_DEVCTL_HM
;
462 } else if (!detect
&& detect_prev
) {
469 /* Attach or detach a device on our only port. */
470 static void musb_attach(USBPort
*port
)
472 MUSBState
*s
= (MUSBState
*) port
->opaque
;
474 musb_intr_set(s
, musb_irq_vbus_request
, 1);
475 musb_session_update(s
, 0, s
->session
);
478 static void musb_detach(USBPort
*port
)
480 MUSBState
*s
= (MUSBState
*) port
->opaque
;
482 musb_intr_set(s
, musb_irq_disconnect
, 1);
483 musb_session_update(s
, 1, s
->session
);
486 static inline void musb_cb_tick0(void *opaque
)
488 MUSBEndPoint
*ep
= (MUSBEndPoint
*) opaque
;
490 ep
->delayed_cb
[0](&ep
->packey
[0], opaque
);
493 static inline void musb_cb_tick1(void *opaque
)
495 MUSBEndPoint
*ep
= (MUSBEndPoint
*) opaque
;
497 ep
->delayed_cb
[1](&ep
->packey
[1], opaque
);
500 #define musb_cb_tick (dir ? musb_cb_tick1 : musb_cb_tick0)
502 static inline void musb_schedule_cb(USBPacket
*packey
, void *opaque
, int dir
)
504 MUSBEndPoint
*ep
= (MUSBEndPoint
*) opaque
;
507 if (ep
->status
[dir
] == USB_RET_NAK
)
508 timeout
= ep
->timeout
[dir
];
509 else if (ep
->interrupt
[dir
])
512 return musb_cb_tick(opaque
);
514 if (!ep
->intv_timer
[dir
])
515 ep
->intv_timer
[dir
] = qemu_new_timer(vm_clock
, musb_cb_tick
, opaque
);
517 qemu_mod_timer(ep
->intv_timer
[dir
], qemu_get_clock(vm_clock
) +
518 muldiv64(timeout
, get_ticks_per_sec(), 8000));
521 static void musb_schedule0_cb(USBPacket
*packey
, void *opaque
)
523 return musb_schedule_cb(packey
, opaque
, 0);
526 static void musb_schedule1_cb(USBPacket
*packey
, void *opaque
)
528 return musb_schedule_cb(packey
, opaque
, 1);
531 static int musb_timeout(int ttype
, int speed
, int val
)
538 case USB_ENDPOINT_XFER_CONTROL
:
541 else if (speed
== USB_SPEED_HIGH
)
542 return 1 << (val
- 1);
544 return 8 << (val
- 1);
546 case USB_ENDPOINT_XFER_INT
:
547 if (speed
== USB_SPEED_HIGH
)
551 return 1 << (val
- 1);
555 case USB_ENDPOINT_XFER_BULK
:
556 case USB_ENDPOINT_XFER_ISOC
:
559 else if (speed
== USB_SPEED_HIGH
)
560 return 1 << (val
- 1);
562 return 8 << (val
- 1);
563 /* TODO: what with low-speed Bulk and Isochronous? */
566 hw_error("bad interval\n");
569 static inline void musb_packet(MUSBState
*s
, MUSBEndPoint
*ep
,
570 int epnum
, int pid
, int len
, USBCallback cb
, int dir
)
573 int idx
= epnum
&& dir
;
576 /* ep->type[0,1] contains:
577 * in bits 7:6 the speed (0 - invalid, 1 - high, 2 - full, 3 - slow)
578 * in bits 5:4 the transfer type (BULK / INT)
579 * in bits 3:0 the EP num
581 ttype
= epnum
? (ep
->type
[idx
] >> 4) & 3 : 0;
583 ep
->timeout
[dir
] = musb_timeout(ttype
,
584 ep
->type
[idx
] >> 6, ep
->interval
[idx
]);
585 ep
->interrupt
[dir
] = ttype
== USB_ENDPOINT_XFER_INT
;
586 ep
->delayed_cb
[dir
] = cb
;
587 cb
= dir
? musb_schedule1_cb
: musb_schedule0_cb
;
589 ep
->packey
[dir
].pid
= pid
;
590 /* A wild guess on the FADDR semantics... */
591 ep
->packey
[dir
].devaddr
= ep
->faddr
[idx
];
592 ep
->packey
[dir
].devep
= ep
->type
[idx
] & 0xf;
593 ep
->packey
[dir
].data
= (void *) ep
->buf
[idx
];
594 ep
->packey
[dir
].len
= len
;
595 ep
->packey
[dir
].complete_cb
= cb
;
596 ep
->packey
[dir
].complete_opaque
= ep
;
599 ret
= s
->port
.dev
->info
->handle_packet(s
->port
.dev
, &ep
->packey
[dir
]);
603 if (ret
== USB_RET_ASYNC
) {
604 ep
->status
[dir
] = len
;
608 ep
->status
[dir
] = ret
;
609 usb_packet_complete(&ep
->packey
[dir
]);
612 static void musb_tx_packet_complete(USBPacket
*packey
, void *opaque
)
614 /* Unfortunately we can't use packey->devep because that's the remote
615 * endpoint number and may be different than our local. */
616 MUSBEndPoint
*ep
= (MUSBEndPoint
*) opaque
;
617 int epnum
= ep
->epnum
;
618 MUSBState
*s
= ep
->musb
;
620 ep
->fifostart
[0] = 0;
623 if (ep
->status
[0] != USB_RET_NAK
) {
626 ep
->csr
[0] &= ~(MGC_M_TXCSR_FIFONOTEMPTY
| MGC_M_TXCSR_TXPKTRDY
);
628 ep
->csr
[0] &= ~MGC_M_CSR0_TXPKTRDY
;
633 /* Clear all of the error bits first */
635 ep
->csr
[0] &= ~(MGC_M_TXCSR_H_ERROR
| MGC_M_TXCSR_H_RXSTALL
|
636 MGC_M_TXCSR_H_NAKTIMEOUT
);
638 ep
->csr
[0] &= ~(MGC_M_CSR0_H_ERROR
| MGC_M_CSR0_H_RXSTALL
|
639 MGC_M_CSR0_H_NAKTIMEOUT
| MGC_M_CSR0_H_NO_PING
);
641 if (ep
->status
[0] == USB_RET_STALL
) {
642 /* Command not supported by target! */
646 ep
->csr
[0] |= MGC_M_TXCSR_H_RXSTALL
;
648 ep
->csr
[0] |= MGC_M_CSR0_H_RXSTALL
;
651 if (ep
->status
[0] == USB_RET_NAK
) {
654 /* NAK timeouts are only generated in Bulk transfers and
655 * Data-errors in Isochronous. */
656 if (ep
->interrupt
[0]) {
661 ep
->csr
[0] |= MGC_M_TXCSR_H_NAKTIMEOUT
;
663 ep
->csr
[0] |= MGC_M_CSR0_H_NAKTIMEOUT
;
666 if (ep
->status
[0] < 0) {
667 if (ep
->status
[0] == USB_RET_BABBLE
)
668 musb_intr_set(s
, musb_irq_rst_babble
, 1);
670 /* Pretend we've tried three times already and failed (in
671 * case of USB_TOKEN_SETUP). */
673 ep
->csr
[0] |= MGC_M_TXCSR_H_ERROR
;
675 ep
->csr
[0] |= MGC_M_CSR0_H_ERROR
;
677 musb_tx_intr_set(s
, epnum
, 1);
680 /* TODO: check len for over/underruns of an OUT packet? */
683 if (!epnum
&& ep
->packey
[0].pid
== USB_TOKEN_SETUP
)
684 s
->setup_len
= ep
->packey
[0].data
[6];
687 /* In DMA mode: if no error, assert DMA request for this EP,
688 * and skip the interrupt. */
689 musb_tx_intr_set(s
, epnum
, 1);
692 static void musb_rx_packet_complete(USBPacket
*packey
, void *opaque
)
694 /* Unfortunately we can't use packey->devep because that's the remote
695 * endpoint number and may be different than our local. */
696 MUSBEndPoint
*ep
= (MUSBEndPoint
*) opaque
;
697 int epnum
= ep
->epnum
;
698 MUSBState
*s
= ep
->musb
;
700 ep
->fifostart
[1] = 0;
704 if (ep
->status
[1] != USB_RET_NAK
) {
706 ep
->csr
[1] &= ~MGC_M_RXCSR_H_REQPKT
;
708 ep
->csr
[0] &= ~MGC_M_CSR0_H_REQPKT
;
713 /* Clear all of the imaginable error bits first */
714 ep
->csr
[1] &= ~(MGC_M_RXCSR_H_ERROR
| MGC_M_RXCSR_H_RXSTALL
|
715 MGC_M_RXCSR_DATAERROR
);
717 ep
->csr
[0] &= ~(MGC_M_CSR0_H_ERROR
| MGC_M_CSR0_H_RXSTALL
|
718 MGC_M_CSR0_H_NAKTIMEOUT
| MGC_M_CSR0_H_NO_PING
);
720 if (ep
->status
[1] == USB_RET_STALL
) {
724 ep
->csr
[1] |= MGC_M_RXCSR_H_RXSTALL
;
726 ep
->csr
[0] |= MGC_M_CSR0_H_RXSTALL
;
729 if (ep
->status
[1] == USB_RET_NAK
) {
732 /* NAK timeouts are only generated in Bulk transfers and
733 * Data-errors in Isochronous. */
734 if (ep
->interrupt
[1])
735 return musb_packet(s
, ep
, epnum
, USB_TOKEN_IN
,
736 packey
->len
, musb_rx_packet_complete
, 1);
738 ep
->csr
[1] |= MGC_M_RXCSR_DATAERROR
;
740 ep
->csr
[0] |= MGC_M_CSR0_H_NAKTIMEOUT
;
743 if (ep
->status
[1] < 0) {
744 if (ep
->status
[1] == USB_RET_BABBLE
) {
745 musb_intr_set(s
, musb_irq_rst_babble
, 1);
749 /* Pretend we've tried three times already and failed (in
750 * case of a control transfer). */
751 ep
->csr
[1] |= MGC_M_RXCSR_H_ERROR
;
753 ep
->csr
[0] |= MGC_M_CSR0_H_ERROR
;
755 musb_rx_intr_set(s
, epnum
, 1);
758 /* TODO: check len for over/underruns of an OUT packet? */
759 /* TODO: perhaps make use of e->ext_size[1] here. */
761 packey
->len
= ep
->status
[1];
763 if (!(ep
->csr
[1] & (MGC_M_RXCSR_H_RXSTALL
| MGC_M_RXCSR_DATAERROR
))) {
764 ep
->csr
[1] |= MGC_M_RXCSR_FIFOFULL
| MGC_M_RXCSR_RXPKTRDY
;
766 ep
->csr
[0] |= MGC_M_CSR0_RXPKTRDY
;
768 ep
->rxcount
= packey
->len
; /* XXX: MIN(packey->len, ep->maxp[1]); */
769 /* In DMA mode: assert DMA request for this EP */
772 /* Only if DMA has not been asserted */
773 musb_rx_intr_set(s
, epnum
, 1);
776 static void musb_tx_rdy(MUSBState
*s
, int epnum
)
778 MUSBEndPoint
*ep
= s
->ep
+ epnum
;
780 int total
, valid
= 0;
781 TRACE("start %d, len %d", ep
->fifostart
[0], ep
->fifolen
[0] );
782 ep
->fifostart
[0] += ep
->fifolen
[0];
785 /* XXX: how's the total size of the packet retrieved exactly in
786 * the generic case? */
787 total
= ep
->maxp
[0] & 0x3ff;
789 if (ep
->ext_size
[0]) {
790 total
= ep
->ext_size
[0];
795 /* If the packet is not fully ready yet, wait for a next segment. */
796 if (epnum
&& (ep
->fifostart
[0]) < total
)
800 total
= ep
->fifostart
[0];
803 if (!epnum
&& (ep
->csr
[0] & MGC_M_CSR0_H_SETUPPKT
)) {
804 pid
= USB_TOKEN_SETUP
;
806 TRACE("illegal SETUPPKT length of %i bytes", total
);
808 /* Controller should retry SETUP packets three times on errors
809 * but it doesn't make sense for us to do that. */
812 return musb_packet(s
, ep
, epnum
, pid
,
813 total
, musb_tx_packet_complete
, 0);
816 static void musb_rx_req(MUSBState
*s
, int epnum
)
818 MUSBEndPoint
*ep
= s
->ep
+ epnum
;
821 /* If we already have a packet, which didn't fit into the
822 * 64 bytes of the FIFO, only move the FIFO start and return. (Obsolete) */
823 if (ep
->packey
[1].pid
== USB_TOKEN_IN
&& ep
->status
[1] >= 0 &&
824 (ep
->fifostart
[1]) + ep
->rxcount
<
826 TRACE("0x%08x, %d", ep
->fifostart
[1], ep
->rxcount
);
827 ep
->fifostart
[1] += ep
->rxcount
;
830 ep
->rxcount
= MIN(ep
->packey
[0].len
- (ep
->fifostart
[1]),
833 ep
->csr
[1] &= ~MGC_M_RXCSR_H_REQPKT
;
835 ep
->csr
[0] &= ~MGC_M_CSR0_H_REQPKT
;
837 /* Clear all of the error bits first */
838 ep
->csr
[1] &= ~(MGC_M_RXCSR_H_ERROR
| MGC_M_RXCSR_H_RXSTALL
|
839 MGC_M_RXCSR_DATAERROR
);
841 ep
->csr
[0] &= ~(MGC_M_CSR0_H_ERROR
| MGC_M_CSR0_H_RXSTALL
|
842 MGC_M_CSR0_H_NAKTIMEOUT
| MGC_M_CSR0_H_NO_PING
);
844 ep
->csr
[1] |= MGC_M_RXCSR_FIFOFULL
| MGC_M_RXCSR_RXPKTRDY
;
846 ep
->csr
[0] |= MGC_M_CSR0_RXPKTRDY
;
847 musb_rx_intr_set(s
, epnum
, 1);
851 /* The driver sets maxp[1] to 64 or less because it knows the hardware
852 * FIFO is this deep. Bigger packets get split in
853 * usb_generic_handle_packet but we can also do the splitting locally
854 * for performance. It turns out we can also have a bigger FIFO and
855 * ignore the limit set in ep->maxp[1]. The Linux MUSB driver deals
856 * OK with single packets of even 32KB and we avoid splitting, however
857 * usb_msd.c sometimes sends a packet bigger than what Linux expects
858 * (e.g. 8192 bytes instead of 4096) and we get an OVERRUN. Splitting
859 * hides this overrun from Linux. Up to 4096 everything is fine
860 * though. Currently this is disabled.
862 * XXX: mind ep->fifosize. */
863 total
= MIN(ep
->maxp
[1] & 0x3ff, sizeof(s
->buf
));
866 /* Why should *we* do that instead of Linux? */
868 if (ep
->packey
[0].devaddr
== 2)
869 total
= MIN(s
->setup_len
, 8);
871 total
= MIN(s
->setup_len
, 64);
872 s
->setup_len
-= total
;
876 return musb_packet(s
, ep
, epnum
, USB_TOKEN_IN
,
877 total
, musb_rx_packet_complete
, 1);
880 static uint8_t musb_read_fifo(MUSBEndPoint
*ep
)
883 if (ep
->fifolen
[1] >= 64) {
884 /* We have a FIFO underrun */
885 TRACE("EP%d FIFO is now empty, stop reading", ep
->epnum
);
888 /* In DMA mode clear RXPKTRDY and set REQPKT automatically
889 * (if AUTOREQ is set) */
891 ep
->csr
[1] &= ~MGC_M_RXCSR_FIFOFULL
;
892 value
=ep
->buf
[1][ep
->fifostart
[1] + ep
->fifolen
[1] ++];
893 TRACE("EP%d 0x%02x, %d", ep
->epnum
, value
, ep
->fifolen
[1] );
897 static void musb_write_fifo(MUSBEndPoint
*ep
, uint8_t value
)
899 TRACE("EP%d = %02x", ep
->epnum
, value
);
900 if (ep
->fifolen
[0] >= 64) {
901 /* We have a FIFO overrun */
902 TRACE("EP%d FIFO exceeded 64 bytes, stop feeding data", ep
->epnum
);
906 ep
->buf
[0][ep
->fifostart
[0] + ep
->fifolen
[0] ++] = value
;
907 ep
->csr
[0] |= MGC_M_TXCSR_FIFONOTEMPTY
;
910 static void musb_ep_frame_cancel(MUSBEndPoint
*ep
, int dir
)
912 if (ep
->intv_timer
[dir
])
913 qemu_del_timer(ep
->intv_timer
[dir
]);
917 static uint8_t musb_busctl_readb(void *opaque
, int ep
, int addr
)
919 MUSBState
*s
= (MUSBState
*) opaque
;
922 /* For USB2.0 HS hubs only */
923 case MUSB_HDRC_TXHUBADDR
:
924 return s
->ep
[ep
].haddr
[0];
925 case MUSB_HDRC_TXHUBPORT
:
926 return s
->ep
[ep
].hport
[0];
927 case MUSB_HDRC_RXHUBADDR
:
928 return s
->ep
[ep
].haddr
[1];
929 case MUSB_HDRC_RXHUBPORT
:
930 return s
->ep
[ep
].hport
[1];
933 TRACE("unknown register 0x%02x", addr
);
938 static void musb_busctl_writeb(void *opaque
, int ep
, int addr
, uint8_t value
)
940 MUSBState
*s
= (MUSBState
*) opaque
;
943 case MUSB_HDRC_TXFUNCADDR
:
944 s
->ep
[ep
].faddr
[0] = value
;
946 case MUSB_HDRC_RXFUNCADDR
:
947 s
->ep
[ep
].faddr
[1] = value
;
949 case MUSB_HDRC_TXHUBADDR
:
950 s
->ep
[ep
].haddr
[0] = value
;
952 case MUSB_HDRC_TXHUBPORT
:
953 s
->ep
[ep
].hport
[0] = value
;
955 case MUSB_HDRC_RXHUBADDR
:
956 s
->ep
[ep
].haddr
[1] = value
;
958 case MUSB_HDRC_RXHUBPORT
:
959 s
->ep
[ep
].hport
[1] = value
;
963 TRACE("unknown register 0x%02x", addr
);
968 static uint16_t musb_busctl_readh(void *opaque
, int ep
, int addr
)
970 MUSBState
*s
= (MUSBState
*) opaque
;
973 case MUSB_HDRC_TXFUNCADDR
:
974 return s
->ep
[ep
].faddr
[0];
975 case MUSB_HDRC_RXFUNCADDR
:
976 return s
->ep
[ep
].faddr
[1];
979 return musb_busctl_readb(s
, ep
, addr
) |
980 (musb_busctl_readb(s
, ep
, addr
| 1) << 8);
984 static void musb_busctl_writeh(void *opaque
, int ep
, int addr
, uint16_t value
)
986 MUSBState
*s
= (MUSBState
*) opaque
;
989 case MUSB_HDRC_TXFUNCADDR
:
990 s
->ep
[ep
].faddr
[0] = value
;
992 case MUSB_HDRC_RXFUNCADDR
:
993 s
->ep
[ep
].faddr
[1] = value
;
997 musb_busctl_writeb(s
, ep
, addr
, value
& 0xff);
998 musb_busctl_writeb(s
, ep
, addr
| 1, value
>> 8);
1002 /* Endpoint control */
1003 static uint8_t musb_ep_readb(void *opaque
, int ep
, int addr
)
1005 MUSBState
*s
= (MUSBState
*) opaque
;
1008 case MUSB_HDRC_TXTYPE
:
1009 return s
->ep
[ep
].type
[0];
1010 case MUSB_HDRC_TXINTERVAL
:
1011 return s
->ep
[ep
].interval
[0];
1012 case MUSB_HDRC_RXTYPE
:
1013 return s
->ep
[ep
].type
[1];
1014 case MUSB_HDRC_RXINTERVAL
:
1015 return s
->ep
[ep
].interval
[1];
1016 case (MUSB_HDRC_FIFOSIZE
& ~1):
1018 case MUSB_HDRC_FIFOSIZE
:
1019 return ep
? s
->ep
[ep
].fifosize
: s
->ep
[ep
].config
;
1020 case MUSB_HDRC_RXCOUNT
:
1021 return s
->ep
[ep
].rxcount
;
1024 TRACE("unknown register 0x%02x", addr
);
1029 static void musb_ep_writeb(void *opaque
, int ep
, int addr
, uint8_t value
)
1031 MUSBState
*s
= (MUSBState
*) opaque
;
1034 case MUSB_HDRC_TXTYPE
:
1035 s
->ep
[ep
].type
[0] = value
;
1037 case MUSB_HDRC_TXINTERVAL
:
1038 s
->ep
[ep
].interval
[0] = value
;
1039 musb_ep_frame_cancel(&s
->ep
[ep
], 0);
1041 case MUSB_HDRC_RXTYPE
:
1042 s
->ep
[ep
].type
[1] = value
;
1044 case MUSB_HDRC_RXINTERVAL
:
1045 s
->ep
[ep
].interval
[1] = value
;
1046 musb_ep_frame_cancel(&s
->ep
[ep
], 1);
1048 case (MUSB_HDRC_FIFOSIZE
& ~1):
1050 case MUSB_HDRC_FIFOSIZE
:
1051 TRACE("somebody messes with fifosize (now %i bytes)", value
);
1052 s
->ep
[ep
].fifosize
= value
;
1055 TRACE("unknown register 0x%02x", addr
);
1060 static uint16_t musb_ep_readh(void *opaque
, int ep
, int addr
)
1062 MUSBState
*s
= (MUSBState
*) opaque
;
1066 case MUSB_HDRC_TXMAXP
:
1067 return s
->ep
[ep
].maxp
[0];
1068 case MUSB_HDRC_TXCSR
:
1069 return s
->ep
[ep
].csr
[0];
1070 case MUSB_HDRC_RXMAXP
:
1071 return s
->ep
[ep
].maxp
[1];
1072 case MUSB_HDRC_RXCSR
:
1073 ret
= s
->ep
[ep
].csr
[1];
1075 /* TODO: This and other bits probably depend on
1076 * ep->csr[1] & MGC_M_RXCSR_AUTOCLEAR. */
1077 if (s
->ep
[ep
].csr
[1] & MGC_M_RXCSR_AUTOCLEAR
)
1078 s
->ep
[ep
].csr
[1] &= ~MGC_M_RXCSR_RXPKTRDY
;
1081 case MUSB_HDRC_RXCOUNT
:
1082 return s
->ep
[ep
].rxcount
;
1085 return musb_ep_readb(s
, ep
, addr
) |
1086 (musb_ep_readb(s
, ep
, addr
| 1) << 8);
1090 static void musb_ep_writeh(void *opaque
, int ep
, int addr
, uint16_t value
)
1092 MUSBState
*s
= (MUSBState
*) opaque
;
1095 case MUSB_HDRC_TXMAXP
:
1096 s
->ep
[ep
].maxp
[0] = value
;
1098 case MUSB_HDRC_TXCSR
:
1100 s
->ep
[ep
].csr
[0] &= value
& 0xa6;
1101 s
->ep
[ep
].csr
[0] |= value
& 0xff59;
1103 s
->ep
[ep
].csr
[0] &= value
& 0x85;
1104 s
->ep
[ep
].csr
[0] |= value
& 0xf7a;
1107 musb_ep_frame_cancel(&s
->ep
[ep
], 0);
1109 if ((ep
&& (value
& MGC_M_TXCSR_FLUSHFIFO
)) ||
1110 (!ep
&& (value
& MGC_M_CSR0_FLUSHFIFO
))) {
1111 s
->ep
[ep
].fifolen
[0] = 0;
1112 s
->ep
[ep
].fifostart
[0] = 0;
1115 ~(MGC_M_TXCSR_FIFONOTEMPTY
| MGC_M_TXCSR_TXPKTRDY
);
1118 ~(MGC_M_CSR0_TXPKTRDY
| MGC_M_CSR0_RXPKTRDY
);
1123 (value
& MGC_M_TXCSR_TXPKTRDY
) &&
1124 !(value
& MGC_M_TXCSR_H_NAKTIMEOUT
)) ||
1126 (value
& MGC_M_TXCSR_TXPKTRDY
)) ||
1130 (value
& MGC_M_CSR0_TXPKTRDY
) &&
1131 !(value
& MGC_M_CSR0_H_NAKTIMEOUT
)))
1133 (value
& MGC_M_CSR0_TXPKTRDY
)))
1137 (value
& MGC_M_CSR0_H_REQPKT
) &&
1139 !(value
& (MGC_M_CSR0_H_NAKTIMEOUT
|
1140 MGC_M_CSR0_RXPKTRDY
)))
1142 !(value
& MGC_M_CSR0_RXPKTRDY
))
1147 case MUSB_HDRC_RXMAXP
:
1148 s
->ep
[ep
].maxp
[1] = value
;
1150 case MUSB_HDRC_RXCSR
:
1151 /* (DMA mode only) */
1153 (value
& MGC_M_RXCSR_H_AUTOREQ
) &&
1154 !(value
& MGC_M_RXCSR_RXPKTRDY
) &&
1155 (s
->ep
[ep
].csr
[1] & MGC_M_RXCSR_RXPKTRDY
))
1156 value
|= MGC_M_RXCSR_H_REQPKT
;
1158 s
->ep
[ep
].csr
[1] &= 0x102 | (value
& 0x4d);
1159 s
->ep
[ep
].csr
[1] |= value
& 0xfeb0;
1161 musb_ep_frame_cancel(&s
->ep
[ep
], 1);
1163 if (value
& MGC_M_RXCSR_FLUSHFIFO
) {
1164 s
->ep
[ep
].fifolen
[1] = 0;
1165 s
->ep
[ep
].fifostart
[1] = 0;
1166 s
->ep
[ep
].csr
[1] &= ~(MGC_M_RXCSR_FIFOFULL
| MGC_M_RXCSR_RXPKTRDY
);
1167 /* If double buffering and we have two packets ready, flush
1168 * only the first one and set up the fifo at the second packet. */
1171 if ((value
& MGC_M_RXCSR_H_REQPKT
) && !(value
& MGC_M_RXCSR_DATAERROR
))
1173 if (value
& MGC_M_RXCSR_H_REQPKT
)
1177 case MUSB_HDRC_RXCOUNT
:
1178 s
->ep
[ep
].rxcount
= value
;
1182 musb_ep_writeb(s
, ep
, addr
, value
& 0xff);
1183 musb_ep_writeb(s
, ep
, addr
| 1, value
>> 8);
1187 /* Generic control */
1188 static uint32_t musb_readb(void *opaque
, target_phys_addr_t addr
)
1190 MUSBState
*s
= (MUSBState
*) opaque
;
1195 case MUSB_HDRC_FADDR
:
1197 case MUSB_HDRC_POWER
:
1199 case MUSB_HDRC_INTRUSB
:
1201 for (i
= 0; i
< sizeof(ret
) * 8; i
++)
1203 musb_intr_set(s
, i
, 0);
1205 case MUSB_HDRC_INTRUSBE
:
1207 case MUSB_HDRC_INDEX
:
1209 case MUSB_HDRC_TESTMODE
:
1212 case MUSB_HDRC_EP_IDX
... (MUSB_HDRC_EP_IDX
+ 0xf):
1213 return musb_ep_readb(s
, s
->idx
, addr
& 0xf);
1215 case MUSB_HDRC_DEVCTL
:
1218 case MUSB_HDRC_TXFIFOSZ
:
1219 case MUSB_HDRC_RXFIFOSZ
:
1220 case MUSB_HDRC_VCTRL
:
1224 case MUSB_HDRC_HWVERS
:
1225 return (1 << 10) | 400;
1227 case (MUSB_HDRC_VCTRL
| 1):
1228 case (MUSB_HDRC_HWVERS
| 1):
1229 case (MUSB_HDRC_DEVCTL
| 1):
1232 case MUSB_HDRC_BUSCTL
... (MUSB_HDRC_BUSCTL
+ 0x7f):
1233 ep
= (addr
>> 3) & 0xf;
1234 return musb_busctl_readb(s
, ep
, addr
& 0x7);
1236 case MUSB_HDRC_EP
... (MUSB_HDRC_EP
+ 0xff):
1237 ep
= (addr
>> 4) & 0xf;
1238 return musb_ep_readb(s
, ep
, addr
& 0xf);
1240 case MUSB_HDRC_FIFO
... (MUSB_HDRC_FIFO
+ 0x3f):
1241 ep
= ((addr
- MUSB_HDRC_FIFO
) >> 2) & 0xf;
1242 return musb_read_fifo(s
->ep
+ ep
);
1245 TRACE("unknown register 0x%02x", (int) addr
);
1250 static void musb_writeb(void *opaque
, target_phys_addr_t addr
, uint32_t value
)
1252 MUSBState
*s
= (MUSBState
*) opaque
;
1256 case MUSB_HDRC_FADDR
:
1257 s
->faddr
= value
& 0x7f;
1259 case MUSB_HDRC_POWER
:
1260 s
->power
= (value
& 0xef) | (s
->power
& 0x10);
1261 /* MGC_M_POWER_RESET is also read-only in Peripheral Mode */
1262 if ((value
& MGC_M_POWER_RESET
) && s
->port
.dev
) {
1263 usb_send_msg(s
->port
.dev
, USB_MSG_RESET
);
1264 /* Negotiate high-speed operation if MGC_M_POWER_HSENAB is set. */
1265 if ((value
& MGC_M_POWER_HSENAB
) &&
1266 s
->port
.dev
->speed
== USB_SPEED_HIGH
)
1267 s
->power
|= MGC_M_POWER_HSMODE
; /* Success */
1268 /* Restart frame counting. */
1270 if (value
& MGC_M_POWER_SUSPENDM
) {
1271 /* When all transfers finish, suspend and if MGC_M_POWER_ENSUSPEND
1272 * is set, also go into low power mode. Frame counting stops. */
1273 /* XXX: Cleared when the interrupt register is read */
1275 if (value
& MGC_M_POWER_RESUME
) {
1276 /* Wait 20ms and signal resuming on the bus. Frame counting
1280 case MUSB_HDRC_INTRUSB
:
1282 case MUSB_HDRC_INTRUSBE
:
1283 s
->mask
= value
& 0xff;
1285 case MUSB_HDRC_INDEX
:
1286 s
->idx
= value
& 0xf;
1288 case MUSB_HDRC_TESTMODE
:
1291 case MUSB_HDRC_EP_IDX
... (MUSB_HDRC_EP_IDX
+ 0xf):
1292 musb_ep_writeb(s
, s
->idx
, addr
& 0xf, value
);
1295 case MUSB_HDRC_DEVCTL
:
1296 s
->session
= !!(value
& MGC_M_DEVCTL_SESSION
);
1297 musb_session_update(s
,
1299 !!(s
->devctl
& MGC_M_DEVCTL_SESSION
));
1301 /* It seems this is the only R/W bit in this register? */
1302 s
->devctl
&= ~MGC_M_DEVCTL_SESSION
;
1303 s
->devctl
|= value
& MGC_M_DEVCTL_SESSION
;
1306 case MUSB_HDRC_TXFIFOSZ
:
1307 case MUSB_HDRC_RXFIFOSZ
:
1308 case MUSB_HDRC_VCTRL
:
1312 case (MUSB_HDRC_VCTRL
| 1):
1313 case (MUSB_HDRC_DEVCTL
| 1):
1316 case MUSB_HDRC_BUSCTL
... (MUSB_HDRC_BUSCTL
+ 0x7f):
1317 ep
= (addr
>> 3) & 0xf;
1318 musb_busctl_writeb(s
, ep
, addr
& 0x7, value
);
1321 case MUSB_HDRC_EP
... (MUSB_HDRC_EP
+ 0xff):
1322 ep
= (addr
>> 4) & 0xf;
1323 musb_ep_writeb(s
, ep
, addr
& 0xf, value
);
1326 case MUSB_HDRC_FIFO
... (MUSB_HDRC_FIFO
+ 0x3f):
1327 ep
= ((addr
- MUSB_HDRC_FIFO
) >> 2) & 0xf;
1328 musb_write_fifo(s
->ep
+ ep
, value
& 0xff);
1332 TRACE("unknown register 0x%02x", (int) addr
);
1337 static uint32_t musb_readh(void *opaque
, target_phys_addr_t addr
)
1339 MUSBState
*s
= (MUSBState
*) opaque
;
1344 case MUSB_HDRC_INTRTX
:
1347 for (i
= 0; i
< sizeof(ret
) * 8; i
++)
1349 musb_tx_intr_set(s
, i
, 0);
1351 case MUSB_HDRC_INTRRX
:
1354 for (i
= 0; i
< sizeof(ret
) * 8; i
++)
1356 musb_rx_intr_set(s
, i
, 0);
1358 case MUSB_HDRC_INTRTXE
:
1360 case MUSB_HDRC_INTRRXE
:
1363 case MUSB_HDRC_FRAME
:
1366 case MUSB_HDRC_TXFIFOADDR
:
1367 return s
->ep
[s
->idx
].fifoaddr
[0];
1368 case MUSB_HDRC_RXFIFOADDR
:
1369 return s
->ep
[s
->idx
].fifoaddr
[1];
1371 case MUSB_HDRC_EP_IDX
... (MUSB_HDRC_EP_IDX
+ 0xf):
1372 return musb_ep_readh(s
, s
->idx
, addr
& 0xf);
1374 case MUSB_HDRC_BUSCTL
... (MUSB_HDRC_BUSCTL
+ 0x7f):
1375 ep
= (addr
>> 3) & 0xf;
1376 return musb_busctl_readh(s
, ep
, addr
& 0x7);
1378 case MUSB_HDRC_EP
... (MUSB_HDRC_EP
+ 0xff):
1379 ep
= (addr
>> 4) & 0xf;
1380 return musb_ep_readh(s
, ep
, addr
& 0xf);
1382 case MUSB_HDRC_FIFO
... (MUSB_HDRC_FIFO
+ 0x3f):
1383 ep
= ((addr
- MUSB_HDRC_FIFO
) >> 2) & 0xf;
1384 return (musb_read_fifo(s
->ep
+ ep
) | musb_read_fifo(s
->ep
+ ep
) << 8);
1387 return musb_readb(s
, addr
) | (musb_readb(s
, addr
| 1) << 8);
1391 static void musb_writeh(void *opaque
, target_phys_addr_t addr
, uint32_t value
)
1393 MUSBState
*s
= (MUSBState
*) opaque
;
1397 case MUSB_HDRC_INTRTXE
:
1399 /* XXX: the masks seem to apply on the raising edge like with
1400 * edge-triggered interrupts, thus no need to update. I may be
1403 case MUSB_HDRC_INTRRXE
:
1407 case MUSB_HDRC_FRAME
:
1410 case MUSB_HDRC_TXFIFOADDR
:
1411 s
->ep
[s
->idx
].fifoaddr
[0] = value
;
1412 s
->ep
[s
->idx
].buf
[0] =
1413 s
->buf
+ ((value
<< 3) & 0x7ff );
1415 case MUSB_HDRC_RXFIFOADDR
:
1416 s
->ep
[s
->idx
].fifoaddr
[1] = value
;
1417 s
->ep
[s
->idx
].buf
[1] =
1418 s
->buf
+ ((value
<< 3) & 0x7ff);
1421 case MUSB_HDRC_EP_IDX
... (MUSB_HDRC_EP_IDX
+ 0xf):
1422 musb_ep_writeh(s
, s
->idx
, addr
& 0xf, value
);
1425 case MUSB_HDRC_BUSCTL
... (MUSB_HDRC_BUSCTL
+ 0x7f):
1426 ep
= (addr
>> 3) & 0xf;
1427 musb_busctl_writeh(s
, ep
, addr
& 0x7, value
);
1430 case MUSB_HDRC_EP
... (MUSB_HDRC_EP
+ 0xff):
1431 ep
= (addr
>> 4) & 0xf;
1432 musb_ep_writeh(s
, ep
, addr
& 0xf, value
);
1435 case MUSB_HDRC_FIFO
... (MUSB_HDRC_FIFO
+ 0x3f):
1436 ep
= ((addr
- MUSB_HDRC_FIFO
) >> 2) & 0xf;
1437 musb_write_fifo(s
->ep
+ ep
, value
& 0xff);
1438 musb_write_fifo(s
->ep
+ ep
, (value
>> 8) & 0xff);
1442 musb_writeb(s
, addr
, value
& 0xff);
1443 musb_writeb(s
, addr
| 1, value
>> 8);
1447 static uint32_t musb_readw(void *opaque
, target_phys_addr_t addr
)
1449 MUSBState
*s
= (MUSBState
*) opaque
;
1453 case MUSB_HDRC_FIFO
... (MUSB_HDRC_FIFO
+ 0x3f):
1454 ep
= ((addr
- MUSB_HDRC_FIFO
) >> 2) & 0xf;
1455 return ( musb_read_fifo(s
->ep
+ ep
) |
1456 musb_read_fifo(s
->ep
+ ep
) << 8 |
1457 musb_read_fifo(s
->ep
+ ep
) << 16 |
1458 musb_read_fifo(s
->ep
+ ep
) << 24 );
1460 TRACE("unknown register 0x%02x", (int) addr
);
1465 static void musb_writew(void *opaque
, target_phys_addr_t addr
, uint32_t value
)
1467 MUSBState
*s
= (MUSBState
*) opaque
;
1471 case MUSB_HDRC_FIFO
... (MUSB_HDRC_FIFO
+ 0x3f):
1472 ep
= ((addr
- MUSB_HDRC_FIFO
) >> 2) & 0xf;
1473 musb_write_fifo(s
->ep
+ ep
, value
& 0xff);
1474 musb_write_fifo(s
->ep
+ ep
, (value
>> 8 ) & 0xff);
1475 musb_write_fifo(s
->ep
+ ep
, (value
>> 16) & 0xff);
1476 musb_write_fifo(s
->ep
+ ep
, (value
>> 24) & 0xff);
1479 TRACE("unknown register 0x%02x", (int) addr
);
1484 CPUReadMemoryFunc
* const musb_read
[] = {
1490 CPUWriteMemoryFunc
* const musb_write
[] = {