2 * PPC4xx I2C controller emulation
4 * Copyright (c) 2007 Jocelyn Mayer
5 * Copyright (c) 2012 François Revol
6 * Copyright (c) 2016-2018 BALATON Zoltan
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #include "qemu/osdep.h"
28 #include "qemu-common.h"
32 #include "hw/i2c/ppc4xx_i2c.h"
33 #include "bitbang_i2c.h"
35 #define PPC4xx_I2C_MEM_SIZE 18
37 #define IIC_CNTL_PT (1 << 0)
38 #define IIC_CNTL_READ (1 << 1)
39 #define IIC_CNTL_CHT (1 << 2)
40 #define IIC_CNTL_RPST (1 << 3)
42 #define IIC_STS_PT (1 << 0)
43 #define IIC_STS_ERR (1 << 2)
44 #define IIC_STS_MDBS (1 << 5)
46 #define IIC_EXTSTS_XFRA (1 << 0)
48 #define IIC_XTCNTLSS_SRST (1 << 0)
50 #define IIC_DIRECTCNTL_SDAC (1 << 3)
51 #define IIC_DIRECTCNTL_SCLC (1 << 2)
52 #define IIC_DIRECTCNTL_MSDA (1 << 1)
53 #define IIC_DIRECTCNTL_MSCL (1 << 0)
55 static void ppc4xx_i2c_reset(DeviceState
*s
)
57 PPC4xxI2CState
*i2c
= PPC4xx_I2C(s
);
59 /* FIXME: Should also reset bus?
60 *if (s->address != ADDR_RESET) {
61 * i2c_end_transfer(s->bus);
78 i2c
->directcntl
= 0xf;
81 static inline bool ppc4xx_i2c_is_master(PPC4xxI2CState
*i2c
)
86 static uint64_t ppc4xx_i2c_readb(void *opaque
, hwaddr addr
, unsigned int size
)
88 PPC4xxI2CState
*i2c
= PPC4xx_I2C(opaque
);
94 if (ppc4xx_i2c_is_master(i2c
)) {
97 if (!(i2c
->sts
& IIC_STS_MDBS
)) {
98 qemu_log_mask(LOG_GUEST_ERROR
, "[%s]%s: Trying to read "
99 "without starting transfer\n",
100 TYPE_PPC4xx_I2C
, __func__
);
102 int pending
= (i2c
->cntl
>> 4) & 3;
104 /* get the next byte */
105 int byte
= i2c_recv(i2c
->bus
);
108 qemu_log_mask(LOG_GUEST_ERROR
, "[%s]%s: read failed "
109 "for device 0x%02x\n", TYPE_PPC4xx_I2C
,
110 __func__
, i2c
->lmadr
);
114 /* Raise interrupt if enabled */
115 /*ppc4xx_i2c_raise_interrupt(i2c)*/;
119 i2c
->sts
&= ~IIC_STS_MDBS
;
120 /*i2c_end_transfer(i2c->bus);*/
121 /*} else if (i2c->cntl & (IIC_CNTL_RPST | IIC_CNTL_CHT)) {*/
122 } else if (pending
) {
123 /* current smbus implementation doesn't like
124 multibyte xfer repeated start */
125 i2c_end_transfer(i2c
->bus
);
126 if (i2c_start_transfer(i2c
->bus
, i2c
->lmadr
>> 1, 1)) {
127 /* if non zero is returned, the adress is not valid */
128 i2c
->sts
&= ~IIC_STS_PT
;
129 i2c
->sts
|= IIC_STS_ERR
;
130 i2c
->extsts
|= IIC_EXTSTS_XFRA
;
132 /*i2c->sts |= IIC_STS_PT;*/
133 i2c
->sts
|= IIC_STS_MDBS
;
134 i2c
->sts
&= ~IIC_STS_ERR
;
139 i2c
->cntl
= (i2c
->cntl
& 0xcf) | (pending
<< 4);
142 qemu_log_mask(LOG_UNIMP
, "[%s]%s: slave mode not implemented\n",
143 TYPE_PPC4xx_I2C
, __func__
);
183 ret
= i2c
->directcntl
;
186 if (addr
< PPC4xx_I2C_MEM_SIZE
) {
187 qemu_log_mask(LOG_UNIMP
, "%s: Unimplemented register 0x%"
188 HWADDR_PRIx
"\n", __func__
, addr
);
190 qemu_log_mask(LOG_GUEST_ERROR
, "%s: Bad address 0x%"
191 HWADDR_PRIx
"\n", __func__
, addr
);
199 static void ppc4xx_i2c_writeb(void *opaque
, hwaddr addr
, uint64_t value
,
202 PPC4xxI2CState
*i2c
= opaque
;
207 if (!i2c_bus_busy(i2c
->bus
)) {
208 /* assume we start a write transfer */
209 if (i2c_start_transfer(i2c
->bus
, i2c
->lmadr
>> 1, 0)) {
210 /* if non zero is returned, the adress is not valid */
211 i2c
->sts
&= ~IIC_STS_PT
;
212 i2c
->sts
|= IIC_STS_ERR
;
213 i2c
->extsts
|= IIC_EXTSTS_XFRA
;
215 i2c
->sts
|= IIC_STS_PT
;
216 i2c
->sts
&= ~IIC_STS_ERR
;
220 if (i2c_bus_busy(i2c
->bus
)) {
221 if (i2c_send(i2c
->bus
, i2c
->mdata
)) {
222 /* if the target return non zero then end the transfer */
223 i2c
->sts
&= ~IIC_STS_PT
;
224 i2c
->sts
|= IIC_STS_ERR
;
225 i2c
->extsts
|= IIC_EXTSTS_XFRA
;
226 i2c_end_transfer(i2c
->bus
);
232 if (i2c_bus_busy(i2c
->bus
)) {
233 i2c_end_transfer(i2c
->bus
);
241 if (i2c
->cntl
& IIC_CNTL_PT
) {
242 if (i2c
->cntl
& IIC_CNTL_READ
) {
243 if (i2c_bus_busy(i2c
->bus
)) {
244 /* end previous transfer */
245 i2c
->sts
&= ~IIC_STS_PT
;
246 i2c_end_transfer(i2c
->bus
);
248 if (i2c_start_transfer(i2c
->bus
, i2c
->lmadr
>> 1, 1)) {
249 /* if non zero is returned, the adress is not valid */
250 i2c
->sts
&= ~IIC_STS_PT
;
251 i2c
->sts
|= IIC_STS_ERR
;
252 i2c
->extsts
|= IIC_EXTSTS_XFRA
;
254 /*i2c->sts |= IIC_STS_PT;*/
255 i2c
->sts
|= IIC_STS_MDBS
;
256 i2c
->sts
&= ~IIC_STS_ERR
;
260 /* we actually already did the write transfer... */
261 i2c
->sts
&= ~IIC_STS_PT
;
266 i2c
->mdcntl
= value
& 0xdf;
269 i2c
->sts
&= ~(value
& 0xa);
272 i2c
->extsts
&= ~(value
& 0x8f);
284 i2c
->intrmsk
= value
;
287 i2c
->xfrcnt
= value
& 0x77;
290 if (value
& IIC_XTCNTLSS_SRST
) {
291 /* Is it actually a full reset? U-Boot sets some regs before */
292 ppc4xx_i2c_reset(DEVICE(i2c
));
295 i2c
->xtcntlss
= value
;
298 i2c
->directcntl
= value
& (IIC_DIRECTCNTL_SDAC
& IIC_DIRECTCNTL_SCLC
);
299 i2c
->directcntl
|= (value
& IIC_DIRECTCNTL_SCLC
? 1 : 0);
300 bitbang_i2c_set(i2c
->bitbang
, BITBANG_I2C_SCL
,
301 i2c
->directcntl
& IIC_DIRECTCNTL_MSCL
);
302 i2c
->directcntl
|= bitbang_i2c_set(i2c
->bitbang
, BITBANG_I2C_SDA
,
303 (value
& IIC_DIRECTCNTL_SDAC
) != 0) << 1;
306 if (addr
< PPC4xx_I2C_MEM_SIZE
) {
307 qemu_log_mask(LOG_UNIMP
, "%s: Unimplemented register 0x%"
308 HWADDR_PRIx
"\n", __func__
, addr
);
310 qemu_log_mask(LOG_GUEST_ERROR
, "%s: Bad address 0x%"
311 HWADDR_PRIx
"\n", __func__
, addr
);
317 static const MemoryRegionOps ppc4xx_i2c_ops
= {
318 .read
= ppc4xx_i2c_readb
,
319 .write
= ppc4xx_i2c_writeb
,
320 .valid
.min_access_size
= 1,
321 .valid
.max_access_size
= 4,
322 .impl
.min_access_size
= 1,
323 .impl
.max_access_size
= 1,
324 .endianness
= DEVICE_NATIVE_ENDIAN
,
327 static void ppc4xx_i2c_init(Object
*o
)
329 PPC4xxI2CState
*s
= PPC4xx_I2C(o
);
331 memory_region_init_io(&s
->iomem
, OBJECT(s
), &ppc4xx_i2c_ops
, s
,
332 TYPE_PPC4xx_I2C
, PPC4xx_I2C_MEM_SIZE
);
333 sysbus_init_mmio(SYS_BUS_DEVICE(s
), &s
->iomem
);
334 sysbus_init_irq(SYS_BUS_DEVICE(s
), &s
->irq
);
335 s
->bus
= i2c_init_bus(DEVICE(s
), "i2c");
336 s
->bitbang
= bitbang_i2c_init(s
->bus
);
339 static void ppc4xx_i2c_class_init(ObjectClass
*klass
, void *data
)
341 DeviceClass
*dc
= DEVICE_CLASS(klass
);
343 dc
->reset
= ppc4xx_i2c_reset
;
346 static const TypeInfo ppc4xx_i2c_type_info
= {
347 .name
= TYPE_PPC4xx_I2C
,
348 .parent
= TYPE_SYS_BUS_DEVICE
,
349 .instance_size
= sizeof(PPC4xxI2CState
),
350 .instance_init
= ppc4xx_i2c_init
,
351 .class_init
= ppc4xx_i2c_class_init
,
354 static void ppc4xx_i2c_register_types(void)
356 type_register_static(&ppc4xx_i2c_type_info
);
359 type_init(ppc4xx_i2c_register_types
)