2 * Status and system control registers for ARM RealView/Versatile boards.
4 * Copyright (c) 2006-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licenced under the GPL.
11 #include "qemu-timer.h"
13 #include "primecell.h"
16 #define LOCK_VALUE 0xa05f
32 static const VMStateDescription vmstate_arm_sysctl
= {
33 .name
= "realview_sysctl",
35 .minimum_version_id
= 1,
36 .fields
= (VMStateField
[]) {
37 VMSTATE_UINT32(leds
, arm_sysctl_state
),
38 VMSTATE_UINT16(lockval
, arm_sysctl_state
),
39 VMSTATE_UINT32(cfgdata1
, arm_sysctl_state
),
40 VMSTATE_UINT32(cfgdata2
, arm_sysctl_state
),
41 VMSTATE_UINT32(flags
, arm_sysctl_state
),
42 VMSTATE_UINT32(nvflags
, arm_sysctl_state
),
43 VMSTATE_UINT32(resetlevel
, arm_sysctl_state
),
48 /* The PB926 actually uses a different format for
49 * its SYS_ID register. Fortunately the bits which are
50 * board type on later boards are distinct.
52 #define BOARD_ID_PB926 0x100
53 #define BOARD_ID_EB 0x140
54 #define BOARD_ID_PBA8 0x178
55 #define BOARD_ID_PBX 0x182
57 static int board_id(arm_sysctl_state
*s
)
59 /* Extract the board ID field from the SYS_ID register value */
60 return (s
->sys_id
>> 16) & 0xfff;
63 static void arm_sysctl_reset(DeviceState
*d
)
65 arm_sysctl_state
*s
= FROM_SYSBUS(arm_sysctl_state
, sysbus_from_qdev(d
));
75 static uint32_t arm_sysctl_read(void *opaque
, target_phys_addr_t offset
)
77 arm_sysctl_state
*s
= (arm_sysctl_state
*)opaque
;
83 /* General purpose hardware switches.
84 We don't have a useful way of exposing these to the user. */
95 case 0x24: /* 100HZ */
96 /* ??? Implement these. */
98 case 0x28: /* CFGDATA1 */
100 case 0x2c: /* CFGDATA2 */
102 case 0x30: /* FLAGS */
104 case 0x38: /* NVFLAGS */
106 case 0x40: /* RESETCTL */
107 return s
->resetlevel
;
108 case 0x44: /* PCICTL */
112 case 0x4c: /* FLASH */
114 case 0x50: /* CLCD */
116 case 0x54: /* CLCDSER */
118 case 0x58: /* BOOTCS */
120 case 0x5c: /* 24MHz */
121 return muldiv64(qemu_get_clock(vm_clock
), 24000000, get_ticks_per_sec());
122 case 0x60: /* MISC */
124 case 0x84: /* PROCID0 */
126 case 0x88: /* PROCID1 */
128 case 0x64: /* DMAPSR0 */
129 case 0x68: /* DMAPSR1 */
130 case 0x6c: /* DMAPSR2 */
131 case 0x70: /* IOSEL */
132 case 0x74: /* PLDCTL */
133 case 0x80: /* BUSID */
134 case 0x8c: /* OSCRESET0 */
135 case 0x90: /* OSCRESET1 */
136 case 0x94: /* OSCRESET2 */
137 case 0x98: /* OSCRESET3 */
138 case 0x9c: /* OSCRESET4 */
139 case 0xc0: /* SYS_TEST_OSC0 */
140 case 0xc4: /* SYS_TEST_OSC1 */
141 case 0xc8: /* SYS_TEST_OSC2 */
142 case 0xcc: /* SYS_TEST_OSC3 */
143 case 0xd0: /* SYS_TEST_OSC4 */
146 printf ("arm_sysctl_read: Bad register offset 0x%x\n", (int)offset
);
151 static void arm_sysctl_write(void *opaque
, target_phys_addr_t offset
,
154 arm_sysctl_state
*s
= (arm_sysctl_state
*)opaque
;
159 case 0x0c: /* OSC0 */
160 case 0x10: /* OSC1 */
161 case 0x14: /* OSC2 */
162 case 0x18: /* OSC3 */
163 case 0x1c: /* OSC4 */
166 case 0x20: /* LOCK */
167 if (val
== LOCK_VALUE
)
170 s
->lockval
= val
& 0x7fff;
172 case 0x28: /* CFGDATA1 */
173 /* ??? Need to implement this. */
176 case 0x2c: /* CFGDATA2 */
177 /* ??? Need to implement this. */
180 case 0x30: /* FLAGSSET */
183 case 0x34: /* FLAGSCLR */
186 case 0x38: /* NVFLAGSSET */
189 case 0x3c: /* NVFLAGSCLR */
192 case 0x40: /* RESETCTL */
193 if (s
->lockval
== LOCK_VALUE
) {
196 qemu_system_reset_request ();
199 case 0x44: /* PCICTL */
202 case 0x4c: /* FLASH */
203 case 0x50: /* CLCD */
204 case 0x54: /* CLCDSER */
205 case 0x64: /* DMAPSR0 */
206 case 0x68: /* DMAPSR1 */
207 case 0x6c: /* DMAPSR2 */
208 case 0x70: /* IOSEL */
209 case 0x74: /* PLDCTL */
210 case 0x80: /* BUSID */
211 case 0x84: /* PROCID0 */
212 case 0x88: /* PROCID1 */
213 case 0x8c: /* OSCRESET0 */
214 case 0x90: /* OSCRESET1 */
215 case 0x94: /* OSCRESET2 */
216 case 0x98: /* OSCRESET3 */
217 case 0x9c: /* OSCRESET4 */
220 printf ("arm_sysctl_write: Bad register offset 0x%x\n", (int)offset
);
225 static CPUReadMemoryFunc
* const arm_sysctl_readfn
[] = {
231 static CPUWriteMemoryFunc
* const arm_sysctl_writefn
[] = {
237 static void arm_sysctl_gpio_set(void *opaque
, int line
, int level
)
239 arm_sysctl_state
*s
= (arm_sysctl_state
*)opaque
;
241 case ARM_SYSCTL_GPIO_MMC_WPROT
:
243 /* For PB926 and EB write-protect is bit 2 of SYS_MCI;
244 * for all later boards it is bit 1.
247 if ((board_id(s
) == BOARD_ID_PB926
) || (board_id(s
) == BOARD_ID_EB
)) {
256 case ARM_SYSCTL_GPIO_MMC_CARDIN
:
265 static int arm_sysctl_init1(SysBusDevice
*dev
)
267 arm_sysctl_state
*s
= FROM_SYSBUS(arm_sysctl_state
, dev
);
270 iomemtype
= cpu_register_io_memory(arm_sysctl_readfn
,
271 arm_sysctl_writefn
, s
,
272 DEVICE_NATIVE_ENDIAN
);
273 sysbus_init_mmio(dev
, 0x1000, iomemtype
);
274 qdev_init_gpio_in(&s
->busdev
.qdev
, arm_sysctl_gpio_set
, 2);
275 /* ??? Save/restore. */
279 /* Legacy helper function. */
280 void arm_sysctl_init(uint32_t base
, uint32_t sys_id
, uint32_t proc_id
)
284 dev
= qdev_create(NULL
, "realview_sysctl");
285 qdev_prop_set_uint32(dev
, "sys_id", sys_id
);
286 qdev_init_nofail(dev
);
287 qdev_prop_set_uint32(dev
, "proc_id", proc_id
);
288 sysbus_mmio_map(sysbus_from_qdev(dev
), 0, base
);
291 static SysBusDeviceInfo arm_sysctl_info
= {
292 .init
= arm_sysctl_init1
,
293 .qdev
.name
= "realview_sysctl",
294 .qdev
.size
= sizeof(arm_sysctl_state
),
295 .qdev
.vmsd
= &vmstate_arm_sysctl
,
296 .qdev
.reset
= arm_sysctl_reset
,
297 .qdev
.props
= (Property
[]) {
298 DEFINE_PROP_UINT32("sys_id", arm_sysctl_state
, sys_id
, 0),
299 DEFINE_PROP_UINT32("proc_id", arm_sysctl_state
, proc_id
, 0),
300 DEFINE_PROP_END_OF_LIST(),
304 static void arm_sysctl_register_devices(void)
306 sysbus_register_withprop(&arm_sysctl_info
);
309 device_init(arm_sysctl_register_devices
)