target/riscv/cpu.c

   1 /*
   2  * QEMU RISC-V CPU
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  * Copyright (c) 2017-2018 SiFive, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2 or later, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qemu/qemu-print.h"
  22 #include "qemu/ctype.h"
  23 #include "qemu/log.h"
  24 #include "cpu.h"
  25 #include "internals.h"
  26 #include "exec/exec-all.h"
  27 #include "qapi/error.h"
  28 #include "qemu/error-report.h"
  29 #include "hw/qdev-properties.h"
  30 #include "migration/vmstate.h"
  31 #include "fpu/softfloat-helpers.h"
  32
  33 /* RISC-V CPU definitions */
  34
  35 static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
  36
  37 const char * const riscv_int_regnames[] = {
  38   "x0/zero", "x1/ra",  "x2/sp",  "x3/gp",  "x4/tp",  "x5/t0",   "x6/t1",
  39   "x7/t2",   "x8/s0",  "x9/s1",  "x10/a0", "x11/a1", "x12/a2",  "x13/a3",
  40   "x14/a4",  "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3",  "x20/s4",
  41   "x21/s5",  "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11",
  42   "x28/t3",  "x29/t4", "x30/t5", "x31/t6"
  43 };
  44
  45 const char * const riscv_fpr_regnames[] = {
  46   "f0/ft0",   "f1/ft1",  "f2/ft2",   "f3/ft3",   "f4/ft4",  "f5/ft5",
  47   "f6/ft6",   "f7/ft7",  "f8/fs0",   "f9/fs1",   "f10/fa0", "f11/fa1",
  48   "f12/fa2",  "f13/fa3", "f14/fa4",  "f15/fa5",  "f16/fa6", "f17/fa7",
  49   "f18/fs2",  "f19/fs3", "f20/fs4",  "f21/fs5",  "f22/fs6", "f23/fs7",
  50   "f24/fs8",  "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9",
  51   "f30/ft10", "f31/ft11"
  52 };
  53
  54 static const char * const riscv_excp_names[] = {
  55     "misaligned_fetch",
  56     "fault_fetch",
  57     "illegal_instruction",
  58     "breakpoint",
  59     "misaligned_load",
  60     "fault_load",
  61     "misaligned_store",
  62     "fault_store",
  63     "user_ecall",
  64     "supervisor_ecall",
  65     "hypervisor_ecall",
  66     "machine_ecall",
  67     "exec_page_fault",
  68     "load_page_fault",
  69     "reserved",
  70     "store_page_fault",
  71     "reserved",
  72     "reserved",
  73     "reserved",
  74     "reserved",
  75     "guest_exec_page_fault",
  76     "guest_load_page_fault",
  77     "reserved",
  78     "guest_store_page_fault",
  79 };
  80
  81 static const char * const riscv_intr_names[] = {
  82     "u_software",
  83     "s_software",
  84     "vs_software",
  85     "m_software",
  86     "u_timer",
  87     "s_timer",
  88     "vs_timer",
  89     "m_timer",
  90     "u_external",
  91     "s_external",
  92     "vs_external",
  93     "m_external",
  94     "reserved",
  95     "reserved",
  96     "reserved",
  97     "reserved"
  98 };
  99
 100 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
 101 {
 102     if (async) {
 103         return (cause < ARRAY_SIZE(riscv_intr_names)) ?
 104                riscv_intr_names[cause] : "(unknown)";
 105     } else {
 106         return (cause < ARRAY_SIZE(riscv_excp_names)) ?
 107                riscv_excp_names[cause] : "(unknown)";
 108     }
 109 }
 110
 111 static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
 112 {
 113     env->misa_mxl_max = env->misa_mxl = mxl;
 114     env->misa_ext_mask = env->misa_ext = ext;
 115 }
 116
 117 static void set_priv_version(CPURISCVState *env, int priv_ver)
 118 {
 119     env->priv_ver = priv_ver;
 120 }
 121
 122 static void set_vext_version(CPURISCVState *env, int vext_ver)
 123 {
 124     env->vext_ver = vext_ver;
 125 }
 126
 127 static void set_feature(CPURISCVState *env, int feature)
 128 {
 129     env->features |= (1ULL << feature);
 130 }
 131
 132 static void set_resetvec(CPURISCVState *env, target_ulong resetvec)
 133 {
 134 #ifndef CONFIG_USER_ONLY
 135     env->resetvec = resetvec;
 136 #endif
 137 }
 138
 139 static void riscv_any_cpu_init(Object *obj)
 140 {
 141     CPURISCVState *env = &RISCV_CPU(obj)->env;
 142 #if defined(TARGET_RISCV32)
 143     set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
 144 #elif defined(TARGET_RISCV64)
 145     set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
 146 #endif
 147     set_priv_version(env, PRIV_VERSION_1_11_0);
 148 }
 149
 150 #if defined(TARGET_RISCV64)
 151 static void rv64_base_cpu_init(Object *obj)
 152 {
 153     CPURISCVState *env = &RISCV_CPU(obj)->env;
 154     /* We set this in the realise function */
 155     set_misa(env, MXL_RV64, 0);
 156 }
 157
 158 static void rv64_sifive_u_cpu_init(Object *obj)
 159 {
 160     CPURISCVState *env = &RISCV_CPU(obj)->env;
 161     set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
 162     set_priv_version(env, PRIV_VERSION_1_10_0);
 163 }
 164
 165 static void rv64_sifive_e_cpu_init(Object *obj)
 166 {
 167     CPURISCVState *env = &RISCV_CPU(obj)->env;
 168     set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
 169     set_priv_version(env, PRIV_VERSION_1_10_0);
 170     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 171 }
 172 #else
 173 static void rv32_base_cpu_init(Object *obj)
 174 {
 175     CPURISCVState *env = &RISCV_CPU(obj)->env;
 176     /* We set this in the realise function */
 177     set_misa(env, MXL_RV32, 0);
 178 }
 179
 180 static void rv32_sifive_u_cpu_init(Object *obj)
 181 {
 182     CPURISCVState *env = &RISCV_CPU(obj)->env;
 183     set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
 184     set_priv_version(env, PRIV_VERSION_1_10_0);
 185 }
 186
 187 static void rv32_sifive_e_cpu_init(Object *obj)
 188 {
 189     CPURISCVState *env = &RISCV_CPU(obj)->env;
 190     set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
 191     set_priv_version(env, PRIV_VERSION_1_10_0);
 192     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 193 }
 194
 195 static void rv32_ibex_cpu_init(Object *obj)
 196 {
 197     CPURISCVState *env = &RISCV_CPU(obj)->env;
 198     set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
 199     set_priv_version(env, PRIV_VERSION_1_10_0);
 200     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 201     qdev_prop_set_bit(DEVICE(obj), "x-epmp", true);
 202 }
 203
 204 static void rv32_imafcu_nommu_cpu_init(Object *obj)
 205 {
 206     CPURISCVState *env = &RISCV_CPU(obj)->env;
 207     set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
 208     set_priv_version(env, PRIV_VERSION_1_10_0);
 209     set_resetvec(env, DEFAULT_RSTVEC);
 210     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 211 }
 212 #endif
 213
 214 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
 215 {
 216     ObjectClass *oc;
 217     char *typename;
 218     char **cpuname;
 219
 220     cpuname = g_strsplit(cpu_model, ",", 1);
 221     typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]);
 222     oc = object_class_by_name(typename);
 223     g_strfreev(cpuname);
 224     g_free(typename);
 225     if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) ||
 226         object_class_is_abstract(oc)) {
 227         return NULL;
 228     }
 229     return oc;
 230 }
 231
 232 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 233 {
 234     RISCVCPU *cpu = RISCV_CPU(cs);
 235     CPURISCVState *env = &cpu->env;
 236     int i;
 237
 238 #if !defined(CONFIG_USER_ONLY)
 239     if (riscv_has_ext(env, RVH)) {
 240         qemu_fprintf(f, " %s %d\n", "V      =  ", riscv_cpu_virt_enabled(env));
 241     }
 242 #endif
 243     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc      ", env->pc);
 244 #ifndef CONFIG_USER_ONLY
 245     {
 246         static const int dump_csrs[] = {
 247             CSR_MHARTID,
 248             CSR_MSTATUS,
 249             CSR_MSTATUSH,
 250             CSR_HSTATUS,
 251             CSR_VSSTATUS,
 252             CSR_MIP,
 253             CSR_MIE,
 254             CSR_MIDELEG,
 255             CSR_HIDELEG,
 256             CSR_MEDELEG,
 257             CSR_HEDELEG,
 258             CSR_MTVEC,
 259             CSR_STVEC,
 260             CSR_VSTVEC,
 261             CSR_MEPC,
 262             CSR_SEPC,
 263             CSR_VSEPC,
 264             CSR_MCAUSE,
 265             CSR_SCAUSE,
 266             CSR_VSCAUSE,
 267             CSR_MTVAL,
 268             CSR_STVAL,
 269             CSR_HTVAL,
 270             CSR_MTVAL2,
 271             CSR_MSCRATCH,
 272             CSR_SSCRATCH,
 273             CSR_SATP,
 274             CSR_MMTE,
 275             CSR_UPMBASE,
 276             CSR_UPMMASK,
 277             CSR_SPMBASE,
 278             CSR_SPMMASK,
 279             CSR_MPMBASE,
 280             CSR_MPMMASK,
 281         };
 282
 283         for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) {
 284             int csrno = dump_csrs[i];
 285             target_ulong val = 0;
 286             RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0);
 287
 288             /*
 289              * Rely on the smode, hmode, etc, predicates within csr.c
 290              * to do the filtering of the registers that are present.
 291              */
 292             if (res == RISCV_EXCP_NONE) {
 293                 qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n",
 294                              csr_ops[csrno].name, val);
 295             }
 296         }
 297     }
 298 #endif
 299
 300     for (i = 0; i < 32; i++) {
 301         qemu_fprintf(f, " %-8s " TARGET_FMT_lx,
 302                      riscv_int_regnames[i], env->gpr[i]);
 303         if ((i & 3) == 3) {
 304             qemu_fprintf(f, "\n");
 305         }
 306     }
 307     if (flags & CPU_DUMP_FPU) {
 308         for (i = 0; i < 32; i++) {
 309             qemu_fprintf(f, " %-8s %016" PRIx64,
 310                          riscv_fpr_regnames[i], env->fpr[i]);
 311             if ((i & 3) == 3) {
 312                 qemu_fprintf(f, "\n");
 313             }
 314         }
 315     }
 316 }
 317
 318 static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
 319 {
 320     RISCVCPU *cpu = RISCV_CPU(cs);
 321     CPURISCVState *env = &cpu->env;
 322     env->pc = value;
 323 }
 324
 325 static void riscv_cpu_synchronize_from_tb(CPUState *cs,
 326                                           const TranslationBlock *tb)
 327 {
 328     RISCVCPU *cpu = RISCV_CPU(cs);
 329     CPURISCVState *env = &cpu->env;
 330     env->pc = tb->pc;
 331 }
 332
 333 static bool riscv_cpu_has_work(CPUState *cs)
 334 {
 335 #ifndef CONFIG_USER_ONLY
 336     RISCVCPU *cpu = RISCV_CPU(cs);
 337     CPURISCVState *env = &cpu->env;
 338     /*
 339      * Definition of the WFI instruction requires it to ignore the privilege
 340      * mode and delegation registers, but respect individual enables
 341      */
 342     return (env->mip & env->mie) != 0;
 343 #else
 344     return true;
 345 #endif
 346 }
 347
 348 void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb,
 349                           target_ulong *data)
 350 {
 351     env->pc = data[0];
 352 }
 353
 354 static void riscv_cpu_reset(DeviceState *dev)
 355 {
 356     CPUState *cs = CPU(dev);
 357     RISCVCPU *cpu = RISCV_CPU(cs);
 358     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
 359     CPURISCVState *env = &cpu->env;
 360
 361     mcc->parent_reset(dev);
 362 #ifndef CONFIG_USER_ONLY
 363     env->misa_mxl = env->misa_mxl_max;
 364     env->priv = PRV_M;
 365     env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
 366     if (env->misa_mxl > MXL_RV32) {
 367         /*
 368          * The reset status of SXL/UXL is undefined, but mstatus is WARL
 369          * and we must ensure that the value after init is valid for read.
 370          */
 371         env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl);
 372         env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl);
 373     }
 374     env->mcause = 0;
 375     env->pc = env->resetvec;
 376     env->two_stage_lookup = false;
 377     /* mmte is supposed to have pm.current hardwired to 1 */
 378     env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT);
 379 #endif
 380     cs->exception_index = RISCV_EXCP_NONE;
 381     env->load_res = -1;
 382     set_default_nan_mode(1, &env->fp_status);
 383 }
 384
 385 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
 386 {
 387     RISCVCPU *cpu = RISCV_CPU(s);
 388
 389     switch (riscv_cpu_mxl(&cpu->env)) {
 390     case MXL_RV32:
 391         info->print_insn = print_insn_riscv32;
 392         break;
 393     case MXL_RV64:
 394         info->print_insn = print_insn_riscv64;
 395         break;
 396     default:
 397         g_assert_not_reached();
 398     }
 399 }
 400
 401 static void riscv_cpu_realize(DeviceState *dev, Error **errp)
 402 {
 403     CPUState *cs = CPU(dev);
 404     RISCVCPU *cpu = RISCV_CPU(dev);
 405     CPURISCVState *env = &cpu->env;
 406     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
 407     int priv_version = 0;
 408     Error *local_err = NULL;
 409
 410     cpu_exec_realizefn(cs, &local_err);
 411     if (local_err != NULL) {
 412         error_propagate(errp, local_err);
 413         return;
 414     }
 415
 416     if (cpu->cfg.priv_spec) {
 417         if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
 418             priv_version = PRIV_VERSION_1_11_0;
 419         } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
 420             priv_version = PRIV_VERSION_1_10_0;
 421         } else {
 422             error_setg(errp,
 423                        "Unsupported privilege spec version '%s'",
 424                        cpu->cfg.priv_spec);
 425             return;
 426         }
 427     }
 428
 429     if (priv_version) {
 430         set_priv_version(env, priv_version);
 431     } else if (!env->priv_ver) {
 432         set_priv_version(env, PRIV_VERSION_1_11_0);
 433     }
 434
 435     if (cpu->cfg.mmu) {
 436         set_feature(env, RISCV_FEATURE_MMU);
 437     }
 438
 439     if (cpu->cfg.pmp) {
 440         set_feature(env, RISCV_FEATURE_PMP);
 441
 442         /*
 443          * Enhanced PMP should only be available
 444          * on harts with PMP support
 445          */
 446         if (cpu->cfg.epmp) {
 447             set_feature(env, RISCV_FEATURE_EPMP);
 448         }
 449     }
 450
 451     set_resetvec(env, cpu->cfg.resetvec);
 452
 453     /* Validate that MISA_MXL is set properly. */
 454     switch (env->misa_mxl_max) {
 455 #ifdef TARGET_RISCV64
 456     case MXL_RV64:
 457         break;
 458 #endif
 459     case MXL_RV32:
 460         break;
 461     default:
 462         g_assert_not_reached();
 463     }
 464     assert(env->misa_mxl_max == env->misa_mxl);
 465
 466     /* If only MISA_EXT is unset for misa, then set it from properties */
 467     if (env->misa_ext == 0) {
 468         uint32_t ext = 0;
 469
 470         /* Do some ISA extension error checking */
 471         if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
 472             error_setg(errp,
 473                        "I and E extensions are incompatible");
 474                        return;
 475        }
 476
 477         if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
 478             error_setg(errp,
 479                        "Either I or E extension must be set");
 480                        return;
 481        }
 482
 483        if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
 484                                cpu->cfg.ext_a & cpu->cfg.ext_f &
 485                                cpu->cfg.ext_d)) {
 486             warn_report("Setting G will also set IMAFD");
 487             cpu->cfg.ext_i = true;
 488             cpu->cfg.ext_m = true;
 489             cpu->cfg.ext_a = true;
 490             cpu->cfg.ext_f = true;
 491             cpu->cfg.ext_d = true;
 492         }
 493
 494         /* Set the ISA extensions, checks should have happened above */
 495         if (cpu->cfg.ext_i) {
 496             ext |= RVI;
 497         }
 498         if (cpu->cfg.ext_e) {
 499             ext |= RVE;
 500         }
 501         if (cpu->cfg.ext_m) {
 502             ext |= RVM;
 503         }
 504         if (cpu->cfg.ext_a) {
 505             ext |= RVA;
 506         }
 507         if (cpu->cfg.ext_f) {
 508             ext |= RVF;
 509         }
 510         if (cpu->cfg.ext_d) {
 511             ext |= RVD;
 512         }
 513         if (cpu->cfg.ext_c) {
 514             ext |= RVC;
 515         }
 516         if (cpu->cfg.ext_s) {
 517             ext |= RVS;
 518         }
 519         if (cpu->cfg.ext_u) {
 520             ext |= RVU;
 521         }
 522         if (cpu->cfg.ext_h) {
 523             ext |= RVH;
 524         }
 525         if (cpu->cfg.ext_v) {
 526             int vext_version = VEXT_VERSION_0_07_1;
 527             ext |= RVV;
 528             if (!is_power_of_2(cpu->cfg.vlen)) {
 529                 error_setg(errp,
 530                         "Vector extension VLEN must be power of 2");
 531                 return;
 532             }
 533             if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) {
 534                 error_setg(errp,
 535                         "Vector extension implementation only supports VLEN "
 536                         "in the range [128, %d]", RV_VLEN_MAX);
 537                 return;
 538             }
 539             if (!is_power_of_2(cpu->cfg.elen)) {
 540                 error_setg(errp,
 541                         "Vector extension ELEN must be power of 2");
 542                 return;
 543             }
 544             if (cpu->cfg.elen > 64 || cpu->cfg.vlen < 8) {
 545                 error_setg(errp,
 546                         "Vector extension implementation only supports ELEN "
 547                         "in the range [8, 64]");
 548                 return;
 549             }
 550             if (cpu->cfg.vext_spec) {
 551                 if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) {
 552                     vext_version = VEXT_VERSION_0_07_1;
 553                 } else {
 554                     error_setg(errp,
 555                            "Unsupported vector spec version '%s'",
 556                            cpu->cfg.vext_spec);
 557                     return;
 558                 }
 559             } else {
 560                 qemu_log("vector version is not specified, "
 561                         "use the default value v0.7.1\n");
 562             }
 563             set_vext_version(env, vext_version);
 564         }
 565         if (cpu->cfg.ext_j) {
 566             ext |= RVJ;
 567         }
 568
 569         set_misa(env, env->misa_mxl, ext);
 570     }
 571
 572     riscv_cpu_register_gdb_regs_for_features(cs);
 573
 574     qemu_init_vcpu(cs);
 575     cpu_reset(cs);
 576
 577     mcc->parent_realize(dev, errp);
 578 }
 579
 580 #ifndef CONFIG_USER_ONLY
 581 static void riscv_cpu_set_irq(void *opaque, int irq, int level)
 582 {
 583     RISCVCPU *cpu = RISCV_CPU(opaque);
 584
 585     switch (irq) {
 586     case IRQ_U_SOFT:
 587     case IRQ_S_SOFT:
 588     case IRQ_VS_SOFT:
 589     case IRQ_M_SOFT:
 590     case IRQ_U_TIMER:
 591     case IRQ_S_TIMER:
 592     case IRQ_VS_TIMER:
 593     case IRQ_M_TIMER:
 594     case IRQ_U_EXT:
 595     case IRQ_S_EXT:
 596     case IRQ_VS_EXT:
 597     case IRQ_M_EXT:
 598         riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level));
 599         break;
 600     default:
 601         g_assert_not_reached();
 602     }
 603 }
 604 #endif /* CONFIG_USER_ONLY */
 605
 606 static void riscv_cpu_init(Object *obj)
 607 {
 608     RISCVCPU *cpu = RISCV_CPU(obj);
 609
 610     cpu_set_cpustate_pointers(cpu);
 611
 612 #ifndef CONFIG_USER_ONLY
 613     qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 12);
 614 #endif /* CONFIG_USER_ONLY */
 615 }
 616
 617 static Property riscv_cpu_properties[] = {
 618     /* Defaults for standard extensions */
 619     DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
 620     DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
 621     DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true),
 622     DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
 623     DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true),
 624     DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true),
 625     DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true),
 626     DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true),
 627     DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
 628     DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
 629     DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
 630     DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
 631     DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
 632     DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
 633     DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
 634
 635     DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
 636
 637     /* These are experimental so mark with 'x-' */
 638     DEFINE_PROP_BOOL("x-zba", RISCVCPU, cfg.ext_zba, false),
 639     DEFINE_PROP_BOOL("x-zbb", RISCVCPU, cfg.ext_zbb, false),
 640     DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false),
 641     DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false),
 642     DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
 643     DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
 644     DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
 645     DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
 646     DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
 647     DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
 648     /* ePMP 0.9.3 */
 649     DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
 650
 651     DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
 652     DEFINE_PROP_END_OF_LIST(),
 653 };
 654
 655 static gchar *riscv_gdb_arch_name(CPUState *cs)
 656 {
 657     RISCVCPU *cpu = RISCV_CPU(cs);
 658     CPURISCVState *env = &cpu->env;
 659
 660     switch (riscv_cpu_mxl(env)) {
 661     case MXL_RV32:
 662         return g_strdup("riscv:rv32");
 663     case MXL_RV64:
 664         return g_strdup("riscv:rv64");
 665     default:
 666         g_assert_not_reached();
 667     }
 668 }
 669
 670 static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
 671 {
 672     RISCVCPU *cpu = RISCV_CPU(cs);
 673
 674     if (strcmp(xmlname, "riscv-csr.xml") == 0) {
 675         return cpu->dyn_csr_xml;
 676     }
 677
 678     return NULL;
 679 }
 680
 681 #ifndef CONFIG_USER_ONLY
 682 #include "hw/core/sysemu-cpu-ops.h"
 683
 684 static const struct SysemuCPUOps riscv_sysemu_ops = {
 685     .get_phys_page_debug = riscv_cpu_get_phys_page_debug,
 686     .write_elf64_note = riscv_cpu_write_elf64_note,
 687     .write_elf32_note = riscv_cpu_write_elf32_note,
 688     .legacy_vmsd = &vmstate_riscv_cpu,
 689 };
 690 #endif
 691
 692 #include "hw/core/tcg-cpu-ops.h"
 693
 694 static const struct TCGCPUOps riscv_tcg_ops = {
 695     .initialize = riscv_translate_init,
 696     .synchronize_from_tb = riscv_cpu_synchronize_from_tb,
 697
 698 #ifndef CONFIG_USER_ONLY
 699     .tlb_fill = riscv_cpu_tlb_fill,
 700     .cpu_exec_interrupt = riscv_cpu_exec_interrupt,
 701     .do_interrupt = riscv_cpu_do_interrupt,
 702     .do_transaction_failed = riscv_cpu_do_transaction_failed,
 703     .do_unaligned_access = riscv_cpu_do_unaligned_access,
 704 #endif /* !CONFIG_USER_ONLY */
 705 };
 706
 707 static void riscv_cpu_class_init(ObjectClass *c, void *data)
 708 {
 709     RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
 710     CPUClass *cc = CPU_CLASS(c);
 711     DeviceClass *dc = DEVICE_CLASS(c);
 712
 713     device_class_set_parent_realize(dc, riscv_cpu_realize,
 714                                     &mcc->parent_realize);
 715
 716     device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset);
 717
 718     cc->class_by_name = riscv_cpu_class_by_name;
 719     cc->has_work = riscv_cpu_has_work;
 720     cc->dump_state = riscv_cpu_dump_state;
 721     cc->set_pc = riscv_cpu_set_pc;
 722     cc->gdb_read_register = riscv_cpu_gdb_read_register;
 723     cc->gdb_write_register = riscv_cpu_gdb_write_register;
 724     cc->gdb_num_core_regs = 33;
 725 #if defined(TARGET_RISCV32)
 726     cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
 727 #elif defined(TARGET_RISCV64)
 728     cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
 729 #endif
 730     cc->gdb_stop_before_watchpoint = true;
 731     cc->disas_set_info = riscv_cpu_disas_set_info;
 732 #ifndef CONFIG_USER_ONLY
 733     cc->sysemu_ops = &riscv_sysemu_ops;
 734 #endif
 735     cc->gdb_arch_name = riscv_gdb_arch_name;
 736     cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
 737     cc->tcg_ops = &riscv_tcg_ops;
 738
 739     device_class_set_props(dc, riscv_cpu_properties);
 740 }
 741
 742 char *riscv_isa_string(RISCVCPU *cpu)
 743 {
 744     int i;
 745     const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1;
 746     char *isa_str = g_new(char, maxlen);
 747     char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS);
 748     for (i = 0; i < sizeof(riscv_exts); i++) {
 749         if (cpu->env.misa_ext & RV(riscv_exts[i])) {
 750             *p++ = qemu_tolower(riscv_exts[i]);
 751         }
 752     }
 753     *p = '\0';
 754     return isa_str;
 755 }
 756
 757 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b)
 758 {
 759     ObjectClass *class_a = (ObjectClass *)a;
 760     ObjectClass *class_b = (ObjectClass *)b;
 761     const char *name_a, *name_b;
 762
 763     name_a = object_class_get_name(class_a);
 764     name_b = object_class_get_name(class_b);
 765     return strcmp(name_a, name_b);
 766 }
 767
 768 static void riscv_cpu_list_entry(gpointer data, gpointer user_data)
 769 {
 770     const char *typename = object_class_get_name(OBJECT_CLASS(data));
 771     int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX);
 772
 773     qemu_printf("%.*s\n", len, typename);
 774 }
 775
 776 void riscv_cpu_list(void)
 777 {
 778     GSList *list;
 779
 780     list = object_class_get_list(TYPE_RISCV_CPU, false);
 781     list = g_slist_sort(list, riscv_cpu_list_compare);
 782     g_slist_foreach(list, riscv_cpu_list_entry, NULL);
 783     g_slist_free(list);
 784 }
 785
 786 #define DEFINE_CPU(type_name, initfn)      \
 787     {                                      \
 788         .name = type_name,                 \
 789         .parent = TYPE_RISCV_CPU,          \
 790         .instance_init = initfn            \
 791     }
 792
 793 static const TypeInfo riscv_cpu_type_infos[] = {
 794     {
 795         .name = TYPE_RISCV_CPU,
 796         .parent = TYPE_CPU,
 797         .instance_size = sizeof(RISCVCPU),
 798         .instance_align = __alignof__(RISCVCPU),
 799         .instance_init = riscv_cpu_init,
 800         .abstract = true,
 801         .class_size = sizeof(RISCVCPUClass),
 802         .class_init = riscv_cpu_class_init,
 803     },
 804     DEFINE_CPU(TYPE_RISCV_CPU_ANY,              riscv_any_cpu_init),
 805 #if defined(TARGET_RISCV32)
 806     DEFINE_CPU(TYPE_RISCV_CPU_BASE32,           rv32_base_cpu_init),
 807     DEFINE_CPU(TYPE_RISCV_CPU_IBEX,             rv32_ibex_cpu_init),
 808     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31,       rv32_sifive_e_cpu_init),
 809     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34,       rv32_imafcu_nommu_cpu_init),
 810     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34,       rv32_sifive_u_cpu_init),
 811 #elif defined(TARGET_RISCV64)
 812     DEFINE_CPU(TYPE_RISCV_CPU_BASE64,           rv64_base_cpu_init),
 813     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51,       rv64_sifive_e_cpu_init),
 814     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54,       rv64_sifive_u_cpu_init),
 815     DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C,         rv64_sifive_u_cpu_init),
 816 #endif
 817 };
 818
 819 DEFINE_TYPES(riscv_cpu_type_infos)