target/riscv/kvm.c

   1 /*
   2  * RISC-V implementation of KVM hooks
   3  *
   4  * Copyright (c) 2020 Huawei Technologies Co., Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2 or later, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include "qemu/osdep.h"
  20 #include <sys/ioctl.h>
  21
  22 #include <linux/kvm.h>
  23
  24 #include "qemu-common.h"
  25 #include "qemu/timer.h"
  26 #include "qemu/error-report.h"
  27 #include "qemu/main-loop.h"
  28 #include "sysemu/sysemu.h"
  29 #include "sysemu/kvm.h"
  30 #include "sysemu/kvm_int.h"
  31 #include "cpu.h"
  32 #include "trace.h"
  33 #include "hw/pci/pci.h"
  34 #include "exec/memattrs.h"
  35 #include "exec/address-spaces.h"
  36 #include "hw/boards.h"
  37 #include "hw/irq.h"
  38 #include "qemu/log.h"
  39 #include "hw/loader.h"
  40 #include "kvm_riscv.h"
  41 #include "sbi_ecall_interface.h"
  42 #include "chardev/char-fe.h"
  43 #include "migration/migration.h"
  44 #include "sysemu/runstate.h"
  45
  46 static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
  47                                  uint64_t idx)
  48 {
  49     uint64_t id = KVM_REG_RISCV | type | idx;
  50
  51     switch (riscv_cpu_mxl(env)) {
  52     case MXL_RV32:
  53         id |= KVM_REG_SIZE_U32;
  54         break;
  55     case MXL_RV64:
  56         id |= KVM_REG_SIZE_U64;
  57         break;
  58     default:
  59         g_assert_not_reached();
  60     }
  61     return id;
  62 }
  63
  64 #define RISCV_CORE_REG(env, name)  kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, \
  65                  KVM_REG_RISCV_CORE_REG(name))
  66
  67 #define RISCV_CSR_REG(env, name)  kvm_riscv_reg_id(env, KVM_REG_RISCV_CSR, \
  68                  KVM_REG_RISCV_CSR_REG(name))
  69
  70 #define RISCV_TIMER_REG(env, name)  kvm_riscv_reg_id(env, KVM_REG_RISCV_TIMER, \
  71                  KVM_REG_RISCV_TIMER_REG(name))
  72
  73 #define RISCV_FP_F_REG(env, idx)  kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_F, idx)
  74
  75 #define RISCV_FP_D_REG(env, idx)  kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_D, idx)
  76
  77 #define KVM_RISCV_GET_CSR(cs, env, csr, reg) \
  78     do { \
  79         int ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), &reg); \
  80         if (ret) { \
  81             return ret; \
  82         } \
  83     } while (0)
  84
  85 #define KVM_RISCV_SET_CSR(cs, env, csr, reg) \
  86     do { \
  87         int ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), &reg); \
  88         if (ret) { \
  89             return ret; \
  90         } \
  91     } while (0)
  92
  93 #define KVM_RISCV_GET_TIMER(cs, env, name, reg) \
  94     do { \
  95         int ret = kvm_get_one_reg(cs, RISCV_TIMER_REG(env, name), &reg); \
  96         if (ret) { \
  97             abort(); \
  98         } \
  99     } while (0)
 100
 101 #define KVM_RISCV_SET_TIMER(cs, env, name, reg) \
 102     do { \
 103         int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(env, time), &reg); \
 104         if (ret) { \
 105             abort(); \
 106         } \
 107     } while (0)
 108
 109 static int kvm_riscv_get_regs_core(CPUState *cs)
 110 {
 111     int ret = 0;
 112     int i;
 113     target_ulong reg;
 114     CPURISCVState *env = &RISCV_CPU(cs)->env;
 115
 116     ret = kvm_get_one_reg(cs, RISCV_CORE_REG(env, regs.pc), &reg);
 117     if (ret) {
 118         return ret;
 119     }
 120     env->pc = reg;
 121
 122     for (i = 1; i < 32; i++) {
 123         uint64_t id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i);
 124         ret = kvm_get_one_reg(cs, id, &reg);
 125         if (ret) {
 126             return ret;
 127         }
 128         env->gpr[i] = reg;
 129     }
 130
 131     return ret;
 132 }
 133
 134 static int kvm_riscv_put_regs_core(CPUState *cs)
 135 {
 136     int ret = 0;
 137     int i;
 138     target_ulong reg;
 139     CPURISCVState *env = &RISCV_CPU(cs)->env;
 140
 141     reg = env->pc;
 142     ret = kvm_set_one_reg(cs, RISCV_CORE_REG(env, regs.pc), &reg);
 143     if (ret) {
 144         return ret;
 145     }
 146
 147     for (i = 1; i < 32; i++) {
 148         uint64_t id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i);
 149         reg = env->gpr[i];
 150         ret = kvm_set_one_reg(cs, id, &reg);
 151         if (ret) {
 152             return ret;
 153         }
 154     }
 155
 156     return ret;
 157 }
 158
 159 static int kvm_riscv_get_regs_csr(CPUState *cs)
 160 {
 161     int ret = 0;
 162     CPURISCVState *env = &RISCV_CPU(cs)->env;
 163
 164     KVM_RISCV_GET_CSR(cs, env, sstatus, env->mstatus);
 165     KVM_RISCV_GET_CSR(cs, env, sie, env->mie);
 166     KVM_RISCV_GET_CSR(cs, env, stvec, env->stvec);
 167     KVM_RISCV_GET_CSR(cs, env, sscratch, env->sscratch);
 168     KVM_RISCV_GET_CSR(cs, env, sepc, env->sepc);
 169     KVM_RISCV_GET_CSR(cs, env, scause, env->scause);
 170     KVM_RISCV_GET_CSR(cs, env, stval, env->stval);
 171     KVM_RISCV_GET_CSR(cs, env, sip, env->mip);
 172     KVM_RISCV_GET_CSR(cs, env, satp, env->satp);
 173     return ret;
 174 }
 175
 176 static int kvm_riscv_put_regs_csr(CPUState *cs)
 177 {
 178     int ret = 0;
 179     CPURISCVState *env = &RISCV_CPU(cs)->env;
 180
 181     KVM_RISCV_SET_CSR(cs, env, sstatus, env->mstatus);
 182     KVM_RISCV_SET_CSR(cs, env, sie, env->mie);
 183     KVM_RISCV_SET_CSR(cs, env, stvec, env->stvec);
 184     KVM_RISCV_SET_CSR(cs, env, sscratch, env->sscratch);
 185     KVM_RISCV_SET_CSR(cs, env, sepc, env->sepc);
 186     KVM_RISCV_SET_CSR(cs, env, scause, env->scause);
 187     KVM_RISCV_SET_CSR(cs, env, stval, env->stval);
 188     KVM_RISCV_SET_CSR(cs, env, sip, env->mip);
 189     KVM_RISCV_SET_CSR(cs, env, satp, env->satp);
 190
 191     return ret;
 192 }
 193
 194 static int kvm_riscv_get_regs_fp(CPUState *cs)
 195 {
 196     int ret = 0;
 197     int i;
 198     CPURISCVState *env = &RISCV_CPU(cs)->env;
 199
 200     if (riscv_has_ext(env, RVD)) {
 201         uint64_t reg;
 202         for (i = 0; i < 32; i++) {
 203             ret = kvm_get_one_reg(cs, RISCV_FP_D_REG(env, i), &reg);
 204             if (ret) {
 205                 return ret;
 206             }
 207             env->fpr[i] = reg;
 208         }
 209         return ret;
 210     }
 211
 212     if (riscv_has_ext(env, RVF)) {
 213         uint32_t reg;
 214         for (i = 0; i < 32; i++) {
 215             ret = kvm_get_one_reg(cs, RISCV_FP_F_REG(env, i), &reg);
 216             if (ret) {
 217                 return ret;
 218             }
 219             env->fpr[i] = reg;
 220         }
 221         return ret;
 222     }
 223
 224     return ret;
 225 }
 226
 227 static int kvm_riscv_put_regs_fp(CPUState *cs)
 228 {
 229     int ret = 0;
 230     int i;
 231     CPURISCVState *env = &RISCV_CPU(cs)->env;
 232
 233     if (riscv_has_ext(env, RVD)) {
 234         uint64_t reg;
 235         for (i = 0; i < 32; i++) {
 236             reg = env->fpr[i];
 237             ret = kvm_set_one_reg(cs, RISCV_FP_D_REG(env, i), &reg);
 238             if (ret) {
 239                 return ret;
 240             }
 241         }
 242         return ret;
 243     }
 244
 245     if (riscv_has_ext(env, RVF)) {
 246         uint32_t reg;
 247         for (i = 0; i < 32; i++) {
 248             reg = env->fpr[i];
 249             ret = kvm_set_one_reg(cs, RISCV_FP_F_REG(env, i), &reg);
 250             if (ret) {
 251                 return ret;
 252             }
 253         }
 254         return ret;
 255     }
 256
 257     return ret;
 258 }
 259
 260 static void kvm_riscv_get_regs_timer(CPUState *cs)
 261 {
 262     CPURISCVState *env = &RISCV_CPU(cs)->env;
 263
 264     if (env->kvm_timer_dirty) {
 265         return;
 266     }
 267
 268     KVM_RISCV_GET_TIMER(cs, env, time, env->kvm_timer_time);
 269     KVM_RISCV_GET_TIMER(cs, env, compare, env->kvm_timer_compare);
 270     KVM_RISCV_GET_TIMER(cs, env, state, env->kvm_timer_state);
 271     KVM_RISCV_GET_TIMER(cs, env, frequency, env->kvm_timer_frequency);
 272
 273     env->kvm_timer_dirty = true;
 274 }
 275
 276 static void kvm_riscv_put_regs_timer(CPUState *cs)
 277 {
 278     uint64_t reg;
 279     CPURISCVState *env = &RISCV_CPU(cs)->env;
 280
 281     if (!env->kvm_timer_dirty) {
 282         return;
 283     }
 284
 285     KVM_RISCV_SET_TIMER(cs, env, time, env->kvm_timer_time);
 286     KVM_RISCV_SET_TIMER(cs, env, compare, env->kvm_timer_compare);
 287
 288     /*
 289      * To set register of RISCV_TIMER_REG(state) will occur a error from KVM
 290      * on env->kvm_timer_state == 0, It's better to adapt in KVM, but it
 291      * doesn't matter that adaping in QEMU now.
 292      * TODO If KVM changes, adapt here.
 293      */
 294     if (env->kvm_timer_state) {
 295         KVM_RISCV_SET_TIMER(cs, env, state, env->kvm_timer_state);
 296     }
 297
 298     /*
 299      * For now, migration will not work between Hosts with different timer
 300      * frequency. Therefore, we should check whether they are the same here
 301      * during the migration.
 302      */
 303     if (migration_is_running(migrate_get_current()->state)) {
 304         KVM_RISCV_GET_TIMER(cs, env, frequency, reg);
 305         if (reg != env->kvm_timer_frequency) {
 306             error_report("Dst Hosts timer frequency != Src Hosts");
 307         }
 308     }
 309
 310     env->kvm_timer_dirty = false;
 311 }
 312
 313 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
 314     KVM_CAP_LAST_INFO
 315 };
 316
 317 int kvm_arch_get_registers(CPUState *cs)
 318 {
 319     int ret = 0;
 320
 321     ret = kvm_riscv_get_regs_core(cs);
 322     if (ret) {
 323         return ret;
 324     }
 325
 326     ret = kvm_riscv_get_regs_csr(cs);
 327     if (ret) {
 328         return ret;
 329     }
 330
 331     ret = kvm_riscv_get_regs_fp(cs);
 332     if (ret) {
 333         return ret;
 334     }
 335
 336     return ret;
 337 }
 338
 339 int kvm_arch_put_registers(CPUState *cs, int level)
 340 {
 341     int ret = 0;
 342
 343     ret = kvm_riscv_put_regs_core(cs);
 344     if (ret) {
 345         return ret;
 346     }
 347
 348     ret = kvm_riscv_put_regs_csr(cs);
 349     if (ret) {
 350         return ret;
 351     }
 352
 353     ret = kvm_riscv_put_regs_fp(cs);
 354     if (ret) {
 355         return ret;
 356     }
 357
 358     return ret;
 359 }
 360
 361 int kvm_arch_release_virq_post(int virq)
 362 {
 363     return 0;
 364 }
 365
 366 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
 367                              uint64_t address, uint32_t data, PCIDevice *dev)
 368 {
 369     return 0;
 370 }
 371
 372 int kvm_arch_destroy_vcpu(CPUState *cs)
 373 {
 374     return 0;
 375 }
 376
 377 unsigned long kvm_arch_vcpu_id(CPUState *cpu)
 378 {
 379     return cpu->cpu_index;
 380 }
 381
 382 static void kvm_riscv_vm_state_change(void *opaque, bool running,
 383                                       RunState state)
 384 {
 385     CPUState *cs = opaque;
 386
 387     if (running) {
 388         kvm_riscv_put_regs_timer(cs);
 389     } else {
 390         kvm_riscv_get_regs_timer(cs);
 391     }
 392 }
 393
 394 void kvm_arch_init_irq_routing(KVMState *s)
 395 {
 396 }
 397
 398 int kvm_arch_init_vcpu(CPUState *cs)
 399 {
 400     int ret = 0;
 401     target_ulong isa;
 402     RISCVCPU *cpu = RISCV_CPU(cs);
 403     CPURISCVState *env = &cpu->env;
 404     uint64_t id;
 405
 406     qemu_add_vm_change_state_handler(kvm_riscv_vm_state_change, cs);
 407
 408     id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG,
 409                           KVM_REG_RISCV_CONFIG_REG(isa));
 410     ret = kvm_get_one_reg(cs, id, &isa);
 411     if (ret) {
 412         return ret;
 413     }
 414     env->misa_ext = isa;
 415
 416     return ret;
 417 }
 418
 419 int kvm_arch_msi_data_to_gsi(uint32_t data)
 420 {
 421     abort();
 422 }
 423
 424 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
 425                                 int vector, PCIDevice *dev)
 426 {
 427     return 0;
 428 }
 429
 430 int kvm_arch_init(MachineState *ms, KVMState *s)
 431 {
 432     return 0;
 433 }
 434
 435 int kvm_arch_irqchip_create(KVMState *s)
 436 {
 437     return 0;
 438 }
 439
 440 int kvm_arch_process_async_events(CPUState *cs)
 441 {
 442     return 0;
 443 }
 444
 445 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
 446 {
 447 }
 448
 449 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
 450 {
 451     return MEMTXATTRS_UNSPECIFIED;
 452 }
 453
 454 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
 455 {
 456     return true;
 457 }
 458
 459 static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
 460 {
 461     int ret = 0;
 462     unsigned char ch;
 463     switch (run->riscv_sbi.extension_id) {
 464     case SBI_EXT_0_1_CONSOLE_PUTCHAR:
 465         ch = run->riscv_sbi.args[0];
 466         qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch));
 467         break;
 468     case SBI_EXT_0_1_CONSOLE_GETCHAR:
 469         ret = qemu_chr_fe_read_all(serial_hd(0)->be, &ch, sizeof(ch));
 470         if (ret == sizeof(ch)) {
 471             run->riscv_sbi.args[0] = ch;
 472         } else {
 473             run->riscv_sbi.args[0] = -1;
 474         }
 475         break;
 476     default:
 477         qemu_log_mask(LOG_UNIMP,
 478                       "%s: un-handled SBI EXIT, specific reasons is %lu\n",
 479                       __func__, run->riscv_sbi.extension_id);
 480         ret = -1;
 481         break;
 482     }
 483     return ret;
 484 }
 485
 486 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
 487 {
 488     int ret = 0;
 489     switch (run->exit_reason) {
 490     case KVM_EXIT_RISCV_SBI:
 491         ret = kvm_riscv_handle_sbi(cs, run);
 492         break;
 493     default:
 494         qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
 495                       __func__, run->exit_reason);
 496         ret = -1;
 497         break;
 498     }
 499     return ret;
 500 }
 501
 502 void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
 503 {
 504     CPURISCVState *env = &cpu->env;
 505
 506     if (!kvm_enabled()) {
 507         return;
 508     }
 509     env->pc = cpu->env.kernel_addr;
 510     env->gpr[10] = kvm_arch_vcpu_id(CPU(cpu)); /* a0 */
 511     env->gpr[11] = cpu->env.fdt_addr;          /* a1 */
 512     env->satp = 0;
 513 }
 514
 515 void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level)
 516 {
 517     int ret;
 518     unsigned virq = level ? KVM_INTERRUPT_SET : KVM_INTERRUPT_UNSET;
 519
 520     if (irq != IRQ_S_EXT) {
 521         perror("kvm riscv set irq != IRQ_S_EXT\n");
 522         abort();
 523     }
 524
 525     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq);
 526     if (ret < 0) {
 527         perror("Set irq failed");
 528         abort();
 529     }
 530 }
 531
 532 bool kvm_arch_cpu_check_are_resettable(void)
 533 {
 534     return true;
 535 }