target-i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include <sys/types.h>
  16 #include <sys/ioctl.h>
  17 #include <sys/mman.h>
  18
  19 #include <linux/kvm.h>
  20
  21 #include "qemu-common.h"
  22 #include "sysemu.h"
  23 #include "kvm.h"
  24 #include "cpu.h"
  25 #include "gdbstub.h"
  26 #include "host-utils.h"
  27
  28 #ifdef CONFIG_KVM_PARA
  29 #include <linux/kvm_para.h>
  30 #endif
  31 //
  32 //#define DEBUG_KVM
  33
  34 #ifdef DEBUG_KVM
  35 #define dprintf(fmt, ...) \
  36     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  37 #else
  38 #define dprintf(fmt, ...) \
  39     do { } while (0)
  40 #endif
  41
  42 #define MSR_KVM_WALL_CLOCK  0x11
  43 #define MSR_KVM_SYSTEM_TIME 0x12
  44
  45 #ifdef KVM_CAP_EXT_CPUID
  46
  47 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
  48 {
  49     struct kvm_cpuid2 *cpuid;
  50     int r, size;
  51
  52     size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
  53     cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size);
  54     cpuid->nent = max;
  55     r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
  56     if (r == 0 && cpuid->nent >= max) {
  57         r = -E2BIG;
  58     }
  59     if (r < 0) {
  60         if (r == -E2BIG) {
  61             qemu_free(cpuid);
  62             return NULL;
  63         } else {
  64             fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
  65                     strerror(-r));
  66             exit(1);
  67         }
  68     }
  69     return cpuid;
  70 }
  71
  72 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, int reg)
  73 {
  74     struct kvm_cpuid2 *cpuid;
  75     int i, max;
  76     uint32_t ret = 0;
  77     uint32_t cpuid_1_edx;
  78
  79     if (!kvm_check_extension(env->kvm_state, KVM_CAP_EXT_CPUID)) {
  80         return -1U;
  81     }
  82
  83     max = 1;
  84     while ((cpuid = try_get_cpuid(env->kvm_state, max)) == NULL) {
  85         max *= 2;
  86     }
  87
  88     for (i = 0; i < cpuid->nent; ++i) {
  89         if (cpuid->entries[i].function == function) {
  90             switch (reg) {
  91             case R_EAX:
  92                 ret = cpuid->entries[i].eax;
  93                 break;
  94             case R_EBX:
  95                 ret = cpuid->entries[i].ebx;
  96                 break;
  97             case R_ECX:
  98                 ret = cpuid->entries[i].ecx;
  99                 break;
 100             case R_EDX:
 101                 ret = cpuid->entries[i].edx;
 102                 switch (function) {
 103                 case 1:
 104                     /* KVM before 2.6.30 misreports the following features */
 105                     ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
 106                     break;
 107                 case 0x80000001:
 108                     /* On Intel, kvm returns cpuid according to the Intel spec,
 109                      * so add missing bits according to the AMD spec:
 110                      */
 111                     cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, R_EDX);
 112                     ret |= cpuid_1_edx & 0xdfeff7ff;
 113                     break;
 114                 }
 115                 break;
 116             }
 117         }
 118     }
 119
 120     qemu_free(cpuid);
 121
 122     return ret;
 123 }
 124
 125 #else
 126
 127 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, int reg)
 128 {
 129     return -1U;
 130 }
 131
 132 #endif
 133
 134 static void kvm_trim_features(uint32_t *features, uint32_t supported)
 135 {
 136     int i;
 137     uint32_t mask;
 138
 139     for (i = 0; i < 32; ++i) {
 140         mask = 1U << i;
 141         if ((*features & mask) && !(supported & mask)) {
 142             *features &= ~mask;
 143         }
 144     }
 145 }
 146
 147 #ifdef CONFIG_KVM_PARA
 148 struct kvm_para_features {
 149         int cap;
 150         int feature;
 151 } para_features[] = {
 152 #ifdef KVM_CAP_CLOCKSOURCE
 153         { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
 154 #endif
 155 #ifdef KVM_CAP_NOP_IO_DELAY
 156         { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
 157 #endif
 158 #ifdef KVM_CAP_PV_MMU
 159         { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
 160 #endif
 161         { -1, -1 }
 162 };
 163
 164 static int get_para_features(CPUState *env)
 165 {
 166         int i, features = 0;
 167
 168         for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) {
 169                 if (kvm_check_extension(env->kvm_state, para_features[i].cap))
 170                         features |= (1 << para_features[i].feature);
 171         }
 172
 173         return features;
 174 }
 175 #endif
 176
 177 int kvm_arch_init_vcpu(CPUState *env)
 178 {
 179     struct {
 180         struct kvm_cpuid2 cpuid;
 181         struct kvm_cpuid_entry2 entries[100];
 182     } __attribute__((packed)) cpuid_data;
 183     uint32_t limit, i, j, cpuid_i;
 184     uint32_t unused;
 185     struct kvm_cpuid_entry2 *c;
 186 #ifdef KVM_CPUID_SIGNATURE
 187     uint32_t signature[3];
 188 #endif
 189
 190     env->mp_state = KVM_MP_STATE_RUNNABLE;
 191
 192     kvm_trim_features(&env->cpuid_features,
 193         kvm_arch_get_supported_cpuid(env, 1, R_EDX));
 194
 195     i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR;
 196     kvm_trim_features(&env->cpuid_ext_features,
 197         kvm_arch_get_supported_cpuid(env, 1, R_ECX));
 198     env->cpuid_ext_features |= i;
 199
 200     kvm_trim_features(&env->cpuid_ext2_features,
 201         kvm_arch_get_supported_cpuid(env, 0x80000001, R_EDX));
 202     kvm_trim_features(&env->cpuid_ext3_features,
 203         kvm_arch_get_supported_cpuid(env, 0x80000001, R_ECX));
 204
 205     cpuid_i = 0;
 206
 207 #ifdef CONFIG_KVM_PARA
 208     /* Paravirtualization CPUIDs */
 209     memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 210     c = &cpuid_data.entries[cpuid_i++];
 211     memset(c, 0, sizeof(*c));
 212     c->function = KVM_CPUID_SIGNATURE;
 213     c->eax = 0;
 214     c->ebx = signature[0];
 215     c->ecx = signature[1];
 216     c->edx = signature[2];
 217
 218     c = &cpuid_data.entries[cpuid_i++];
 219     memset(c, 0, sizeof(*c));
 220     c->function = KVM_CPUID_FEATURES;
 221     c->eax = env->cpuid_kvm_features & get_para_features(env);
 222 #endif
 223
 224     cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
 225
 226     for (i = 0; i <= limit; i++) {
 227         c = &cpuid_data.entries[cpuid_i++];
 228
 229         switch (i) {
 230         case 2: {
 231             /* Keep reading function 2 till all the input is received */
 232             int times;
 233
 234             c->function = i;
 235             c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
 236                        KVM_CPUID_FLAG_STATE_READ_NEXT;
 237             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 238             times = c->eax & 0xff;
 239
 240             for (j = 1; j < times; ++j) {
 241                 c = &cpuid_data.entries[cpuid_i++];
 242                 c->function = i;
 243                 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
 244                 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 245             }
 246             break;
 247         }
 248         case 4:
 249         case 0xb:
 250         case 0xd:
 251             for (j = 0; ; j++) {
 252                 c->function = i;
 253                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
 254                 c->index = j;
 255                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
 256
 257                 if (i == 4 && c->eax == 0)
 258                     break;
 259                 if (i == 0xb && !(c->ecx & 0xff00))
 260                     break;
 261                 if (i == 0xd && c->eax == 0)
 262                     break;
 263
 264                 c = &cpuid_data.entries[cpuid_i++];
 265             }
 266             break;
 267         default:
 268             c->function = i;
 269             c->flags = 0;
 270             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 271             break;
 272         }
 273     }
 274     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
 275
 276     for (i = 0x80000000; i <= limit; i++) {
 277         c = &cpuid_data.entries[cpuid_i++];
 278
 279         c->function = i;
 280         c->flags = 0;
 281         cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 282     }
 283
 284     cpuid_data.cpuid.nent = cpuid_i;
 285
 286     return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
 287 }
 288
 289 void kvm_arch_reset_vcpu(CPUState *env)
 290 {
 291     env->exception_injected = -1;
 292     env->interrupt_injected = -1;
 293     env->nmi_injected = 0;
 294     env->nmi_pending = 0;
 295 }
 296
 297 static int kvm_has_msr_star(CPUState *env)
 298 {
 299     static int has_msr_star;
 300     int ret;
 301
 302     /* first time */
 303     if (has_msr_star == 0) {
 304         struct kvm_msr_list msr_list, *kvm_msr_list;
 305
 306         has_msr_star = -1;
 307
 308         /* Obtain MSR list from KVM.  These are the MSRs that we must
 309          * save/restore */
 310         msr_list.nmsrs = 0;
 311         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, &msr_list);
 312         if (ret < 0 && ret != -E2BIG) {
 313             return 0;
 314         }
 315         /* Old kernel modules had a bug and could write beyond the provided
 316            memory. Allocate at least a safe amount of 1K. */
 317         kvm_msr_list = qemu_mallocz(MAX(1024, sizeof(msr_list) +
 318                                               msr_list.nmsrs *
 319                                               sizeof(msr_list.indices[0])));
 320
 321         kvm_msr_list->nmsrs = msr_list.nmsrs;
 322         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
 323         if (ret >= 0) {
 324             int i;
 325
 326             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
 327                 if (kvm_msr_list->indices[i] == MSR_STAR) {
 328                     has_msr_star = 1;
 329                     break;
 330                 }
 331             }
 332         }
 333
 334         free(kvm_msr_list);
 335     }
 336
 337     if (has_msr_star == 1)
 338         return 1;
 339     return 0;
 340 }
 341
 342 int kvm_arch_init(KVMState *s, int smp_cpus)
 343 {
 344     int ret;
 345
 346     /* create vm86 tss.  KVM uses vm86 mode to emulate 16-bit code
 347      * directly.  In order to use vm86 mode, a TSS is needed.  Since this
 348      * must be part of guest physical memory, we need to allocate it.  Older
 349      * versions of KVM just assumed that it would be at the end of physical
 350      * memory but that doesn't work with more than 4GB of memory.  We simply
 351      * refuse to work with those older versions of KVM. */
 352     ret = kvm_ioctl(s, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
 353     if (ret <= 0) {
 354         fprintf(stderr, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
 355         return ret;
 356     }
 357
 358     /* this address is 3 pages before the bios, and the bios should present
 359      * as unavaible memory.  FIXME, need to ensure the e820 map deals with
 360      * this?
 361      */
 362     return kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, 0xfffbd000);
 363 }
 364
 365 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 366 {
 367     lhs->selector = rhs->selector;
 368     lhs->base = rhs->base;
 369     lhs->limit = rhs->limit;
 370     lhs->type = 3;
 371     lhs->present = 1;
 372     lhs->dpl = 3;
 373     lhs->db = 0;
 374     lhs->s = 1;
 375     lhs->l = 0;
 376     lhs->g = 0;
 377     lhs->avl = 0;
 378     lhs->unusable = 0;
 379 }
 380
 381 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 382 {
 383     unsigned flags = rhs->flags;
 384     lhs->selector = rhs->selector;
 385     lhs->base = rhs->base;
 386     lhs->limit = rhs->limit;
 387     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 388     lhs->present = (flags & DESC_P_MASK) != 0;
 389     lhs->dpl = rhs->selector & 3;
 390     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 391     lhs->s = (flags & DESC_S_MASK) != 0;
 392     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 393     lhs->g = (flags & DESC_G_MASK) != 0;
 394     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 395     lhs->unusable = 0;
 396 }
 397
 398 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 399 {
 400     lhs->selector = rhs->selector;
 401     lhs->base = rhs->base;
 402     lhs->limit = rhs->limit;
 403     lhs->flags =
 404         (rhs->type << DESC_TYPE_SHIFT)
 405         | (rhs->present * DESC_P_MASK)
 406         | (rhs->dpl << DESC_DPL_SHIFT)
 407         | (rhs->db << DESC_B_SHIFT)
 408         | (rhs->s * DESC_S_MASK)
 409         | (rhs->l << DESC_L_SHIFT)
 410         | (rhs->g * DESC_G_MASK)
 411         | (rhs->avl * DESC_AVL_MASK);
 412 }
 413
 414 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
 415 {
 416     if (set)
 417         *kvm_reg = *qemu_reg;
 418     else
 419         *qemu_reg = *kvm_reg;
 420 }
 421
 422 static int kvm_getput_regs(CPUState *env, int set)
 423 {
 424     struct kvm_regs regs;
 425     int ret = 0;
 426
 427     if (!set) {
 428         ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
 429         if (ret < 0)
 430             return ret;
 431     }
 432
 433     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
 434     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
 435     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
 436     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
 437     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
 438     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
 439     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
 440     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
 441 #ifdef TARGET_X86_64
 442     kvm_getput_reg(&regs.r8, &env->regs[8], set);
 443     kvm_getput_reg(&regs.r9, &env->regs[9], set);
 444     kvm_getput_reg(&regs.r10, &env->regs[10], set);
 445     kvm_getput_reg(&regs.r11, &env->regs[11], set);
 446     kvm_getput_reg(&regs.r12, &env->regs[12], set);
 447     kvm_getput_reg(&regs.r13, &env->regs[13], set);
 448     kvm_getput_reg(&regs.r14, &env->regs[14], set);
 449     kvm_getput_reg(&regs.r15, &env->regs[15], set);
 450 #endif
 451
 452     kvm_getput_reg(&regs.rflags, &env->eflags, set);
 453     kvm_getput_reg(&regs.rip, &env->eip, set);
 454
 455     if (set)
 456         ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
 457
 458     return ret;
 459 }
 460
 461 static int kvm_put_fpu(CPUState *env)
 462 {
 463     struct kvm_fpu fpu;
 464     int i;
 465
 466     memset(&fpu, 0, sizeof fpu);
 467     fpu.fsw = env->fpus & ~(7 << 11);
 468     fpu.fsw |= (env->fpstt & 7) << 11;
 469     fpu.fcw = env->fpuc;
 470     for (i = 0; i < 8; ++i)
 471         fpu.ftwx |= (!env->fptags[i]) << i;
 472     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 473     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 474     fpu.mxcsr = env->mxcsr;
 475
 476     return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
 477 }
 478
 479 static int kvm_put_sregs(CPUState *env)
 480 {
 481     struct kvm_sregs sregs;
 482
 483     memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
 484     if (env->interrupt_injected >= 0) {
 485         sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
 486                 (uint64_t)1 << (env->interrupt_injected % 64);
 487     }
 488
 489     if ((env->eflags & VM_MASK)) {
 490             set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 491             set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 492             set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 493             set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 494             set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 495             set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 496     } else {
 497             set_seg(&sregs.cs, &env->segs[R_CS]);
 498             set_seg(&sregs.ds, &env->segs[R_DS]);
 499             set_seg(&sregs.es, &env->segs[R_ES]);
 500             set_seg(&sregs.fs, &env->segs[R_FS]);
 501             set_seg(&sregs.gs, &env->segs[R_GS]);
 502             set_seg(&sregs.ss, &env->segs[R_SS]);
 503
 504             if (env->cr[0] & CR0_PE_MASK) {
 505                 /* force ss cpl to cs cpl */
 506                 sregs.ss.selector = (sregs.ss.selector & ~3) |
 507                         (sregs.cs.selector & 3);
 508                 sregs.ss.dpl = sregs.ss.selector & 3;
 509             }
 510     }
 511
 512     set_seg(&sregs.tr, &env->tr);
 513     set_seg(&sregs.ldt, &env->ldt);
 514
 515     sregs.idt.limit = env->idt.limit;
 516     sregs.idt.base = env->idt.base;
 517     sregs.gdt.limit = env->gdt.limit;
 518     sregs.gdt.base = env->gdt.base;
 519
 520     sregs.cr0 = env->cr[0];
 521     sregs.cr2 = env->cr[2];
 522     sregs.cr3 = env->cr[3];
 523     sregs.cr4 = env->cr[4];
 524
 525     sregs.cr8 = cpu_get_apic_tpr(env);
 526     sregs.apic_base = cpu_get_apic_base(env);
 527
 528     sregs.efer = env->efer;
 529
 530     return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
 531 }
 532
 533 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
 534                               uint32_t index, uint64_t value)
 535 {
 536     entry->index = index;
 537     entry->data = value;
 538 }
 539
 540 static int kvm_put_msrs(CPUState *env)
 541 {
 542     struct {
 543         struct kvm_msrs info;
 544         struct kvm_msr_entry entries[100];
 545     } msr_data;
 546     struct kvm_msr_entry *msrs = msr_data.entries;
 547     int n = 0;
 548
 549     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
 550     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
 551     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
 552     if (kvm_has_msr_star(env))
 553         kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
 554     kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
 555 #ifdef TARGET_X86_64
 556     /* FIXME if lm capable */
 557     kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
 558     kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
 559     kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
 560     kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
 561 #endif
 562     kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,  env->system_time_msr);
 563     kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK,  env->wall_clock_msr);
 564
 565     msr_data.info.nmsrs = n;
 566
 567     return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
 568
 569 }
 570
 571
 572 static int kvm_get_fpu(CPUState *env)
 573 {
 574     struct kvm_fpu fpu;
 575     int i, ret;
 576
 577     ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
 578     if (ret < 0)
 579         return ret;
 580
 581     env->fpstt = (fpu.fsw >> 11) & 7;
 582     env->fpus = fpu.fsw;
 583     env->fpuc = fpu.fcw;
 584     for (i = 0; i < 8; ++i)
 585         env->fptags[i] = !((fpu.ftwx >> i) & 1);
 586     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
 587     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
 588     env->mxcsr = fpu.mxcsr;
 589
 590     return 0;
 591 }
 592
 593 static int kvm_get_sregs(CPUState *env)
 594 {
 595     struct kvm_sregs sregs;
 596     uint32_t hflags;
 597     int bit, i, ret;
 598
 599     ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
 600     if (ret < 0)
 601         return ret;
 602
 603     /* There can only be one pending IRQ set in the bitmap at a time, so try
 604        to find it and save its number instead (-1 for none). */
 605     env->interrupt_injected = -1;
 606     for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
 607         if (sregs.interrupt_bitmap[i]) {
 608             bit = ctz64(sregs.interrupt_bitmap[i]);
 609             env->interrupt_injected = i * 64 + bit;
 610             break;
 611         }
 612     }
 613
 614     get_seg(&env->segs[R_CS], &sregs.cs);
 615     get_seg(&env->segs[R_DS], &sregs.ds);
 616     get_seg(&env->segs[R_ES], &sregs.es);
 617     get_seg(&env->segs[R_FS], &sregs.fs);
 618     get_seg(&env->segs[R_GS], &sregs.gs);
 619     get_seg(&env->segs[R_SS], &sregs.ss);
 620
 621     get_seg(&env->tr, &sregs.tr);
 622     get_seg(&env->ldt, &sregs.ldt);
 623
 624     env->idt.limit = sregs.idt.limit;
 625     env->idt.base = sregs.idt.base;
 626     env->gdt.limit = sregs.gdt.limit;
 627     env->gdt.base = sregs.gdt.base;
 628
 629     env->cr[0] = sregs.cr0;
 630     env->cr[2] = sregs.cr2;
 631     env->cr[3] = sregs.cr3;
 632     env->cr[4] = sregs.cr4;
 633
 634     cpu_set_apic_base(env, sregs.apic_base);
 635
 636     env->efer = sregs.efer;
 637     //cpu_set_apic_tpr(env, sregs.cr8);
 638
 639 #define HFLAG_COPY_MASK ~( \
 640                         HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
 641                         HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
 642                         HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
 643                         HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
 644
 645
 646
 647     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
 648     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
 649     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
 650             (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
 651     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
 652     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
 653             (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
 654
 655     if (env->efer & MSR_EFER_LMA) {
 656         hflags |= HF_LMA_MASK;
 657     }
 658
 659     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
 660         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
 661     } else {
 662         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
 663                 (DESC_B_SHIFT - HF_CS32_SHIFT);
 664         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
 665                 (DESC_B_SHIFT - HF_SS32_SHIFT);
 666         if (!(env->cr[0] & CR0_PE_MASK) ||
 667                    (env->eflags & VM_MASK) ||
 668                    !(hflags & HF_CS32_MASK)) {
 669                 hflags |= HF_ADDSEG_MASK;
 670             } else {
 671                 hflags |= ((env->segs[R_DS].base |
 672                                 env->segs[R_ES].base |
 673                                 env->segs[R_SS].base) != 0) <<
 674                     HF_ADDSEG_SHIFT;
 675             }
 676     }
 677     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
 678
 679     return 0;
 680 }
 681
 682 static int kvm_get_msrs(CPUState *env)
 683 {
 684     struct {
 685         struct kvm_msrs info;
 686         struct kvm_msr_entry entries[100];
 687     } msr_data;
 688     struct kvm_msr_entry *msrs = msr_data.entries;
 689     int ret, i, n;
 690
 691     n = 0;
 692     msrs[n++].index = MSR_IA32_SYSENTER_CS;
 693     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
 694     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
 695     if (kvm_has_msr_star(env))
 696         msrs[n++].index = MSR_STAR;
 697     msrs[n++].index = MSR_IA32_TSC;
 698 #ifdef TARGET_X86_64
 699     /* FIXME lm_capable_kernel */
 700     msrs[n++].index = MSR_CSTAR;
 701     msrs[n++].index = MSR_KERNELGSBASE;
 702     msrs[n++].index = MSR_FMASK;
 703     msrs[n++].index = MSR_LSTAR;
 704 #endif
 705     msrs[n++].index = MSR_KVM_SYSTEM_TIME;
 706     msrs[n++].index = MSR_KVM_WALL_CLOCK;
 707
 708     msr_data.info.nmsrs = n;
 709     ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
 710     if (ret < 0)
 711         return ret;
 712
 713     for (i = 0; i < ret; i++) {
 714         switch (msrs[i].index) {
 715         case MSR_IA32_SYSENTER_CS:
 716             env->sysenter_cs = msrs[i].data;
 717             break;
 718         case MSR_IA32_SYSENTER_ESP:
 719             env->sysenter_esp = msrs[i].data;
 720             break;
 721         case MSR_IA32_SYSENTER_EIP:
 722             env->sysenter_eip = msrs[i].data;
 723             break;
 724         case MSR_STAR:
 725             env->star = msrs[i].data;
 726             break;
 727 #ifdef TARGET_X86_64
 728         case MSR_CSTAR:
 729             env->cstar = msrs[i].data;
 730             break;
 731         case MSR_KERNELGSBASE:
 732             env->kernelgsbase = msrs[i].data;
 733             break;
 734         case MSR_FMASK:
 735             env->fmask = msrs[i].data;
 736             break;
 737         case MSR_LSTAR:
 738             env->lstar = msrs[i].data;
 739             break;
 740 #endif
 741         case MSR_IA32_TSC:
 742             env->tsc = msrs[i].data;
 743             break;
 744         case MSR_KVM_SYSTEM_TIME:
 745             env->system_time_msr = msrs[i].data;
 746             break;
 747         case MSR_KVM_WALL_CLOCK:
 748             env->wall_clock_msr = msrs[i].data;
 749             break;
 750         }
 751     }
 752
 753     return 0;
 754 }
 755
 756 static int kvm_put_mp_state(CPUState *env)
 757 {
 758     struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
 759
 760     return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state);
 761 }
 762
 763 static int kvm_get_mp_state(CPUState *env)
 764 {
 765     struct kvm_mp_state mp_state;
 766     int ret;
 767
 768     ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state);
 769     if (ret < 0) {
 770         return ret;
 771     }
 772     env->mp_state = mp_state.mp_state;
 773     return 0;
 774 }
 775
 776 static int kvm_put_vcpu_events(CPUState *env)
 777 {
 778 #ifdef KVM_CAP_VCPU_EVENTS
 779     struct kvm_vcpu_events events;
 780
 781     if (!kvm_has_vcpu_events()) {
 782         return 0;
 783     }
 784
 785     events.exception.injected = (env->exception_injected >= 0);
 786     events.exception.nr = env->exception_injected;
 787     events.exception.has_error_code = env->has_error_code;
 788     events.exception.error_code = env->error_code;
 789
 790     events.interrupt.injected = (env->interrupt_injected >= 0);
 791     events.interrupt.nr = env->interrupt_injected;
 792     events.interrupt.soft = env->soft_interrupt;
 793
 794     events.nmi.injected = env->nmi_injected;
 795     events.nmi.pending = env->nmi_pending;
 796     events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
 797
 798     events.sipi_vector = env->sipi_vector;
 799
 800     events.flags =
 801         KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
 802
 803     return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events);
 804 #else
 805     return 0;
 806 #endif
 807 }
 808
 809 static int kvm_get_vcpu_events(CPUState *env)
 810 {
 811 #ifdef KVM_CAP_VCPU_EVENTS
 812     struct kvm_vcpu_events events;
 813     int ret;
 814
 815     if (!kvm_has_vcpu_events()) {
 816         return 0;
 817     }
 818
 819     ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events);
 820     if (ret < 0) {
 821        return ret;
 822     }
 823     env->exception_injected =
 824        events.exception.injected ? events.exception.nr : -1;
 825     env->has_error_code = events.exception.has_error_code;
 826     env->error_code = events.exception.error_code;
 827
 828     env->interrupt_injected =
 829         events.interrupt.injected ? events.interrupt.nr : -1;
 830     env->soft_interrupt = events.interrupt.soft;
 831
 832     env->nmi_injected = events.nmi.injected;
 833     env->nmi_pending = events.nmi.pending;
 834     if (events.nmi.masked) {
 835         env->hflags2 |= HF2_NMI_MASK;
 836     } else {
 837         env->hflags2 &= ~HF2_NMI_MASK;
 838     }
 839
 840     env->sipi_vector = events.sipi_vector;
 841 #endif
 842
 843     return 0;
 844 }
 845
 846 int kvm_arch_put_registers(CPUState *env)
 847 {
 848     int ret;
 849
 850     ret = kvm_getput_regs(env, 1);
 851     if (ret < 0)
 852         return ret;
 853
 854     ret = kvm_put_fpu(env);
 855     if (ret < 0)
 856         return ret;
 857
 858     ret = kvm_put_sregs(env);
 859     if (ret < 0)
 860         return ret;
 861
 862     ret = kvm_put_msrs(env);
 863     if (ret < 0)
 864         return ret;
 865
 866     ret = kvm_put_mp_state(env);
 867     if (ret < 0)
 868         return ret;
 869
 870     ret = kvm_put_vcpu_events(env);
 871     if (ret < 0)
 872         return ret;
 873
 874     return 0;
 875 }
 876
 877 int kvm_arch_get_registers(CPUState *env)
 878 {
 879     int ret;
 880
 881     ret = kvm_getput_regs(env, 0);
 882     if (ret < 0)
 883         return ret;
 884
 885     ret = kvm_get_fpu(env);
 886     if (ret < 0)
 887         return ret;
 888
 889     ret = kvm_get_sregs(env);
 890     if (ret < 0)
 891         return ret;
 892
 893     ret = kvm_get_msrs(env);
 894     if (ret < 0)
 895         return ret;
 896
 897     ret = kvm_get_mp_state(env);
 898     if (ret < 0)
 899         return ret;
 900
 901     ret = kvm_get_vcpu_events(env);
 902     if (ret < 0)
 903         return ret;
 904
 905     return 0;
 906 }
 907
 908 int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
 909 {
 910     /* Try to inject an interrupt if the guest can accept it */
 911     if (run->ready_for_interrupt_injection &&
 912         (env->interrupt_request & CPU_INTERRUPT_HARD) &&
 913         (env->eflags & IF_MASK)) {
 914         int irq;
 915
 916         env->interrupt_request &= ~CPU_INTERRUPT_HARD;
 917         irq = cpu_get_pic_interrupt(env);
 918         if (irq >= 0) {
 919             struct kvm_interrupt intr;
 920             intr.irq = irq;
 921             /* FIXME: errors */
 922             dprintf("injected interrupt %d\n", irq);
 923             kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
 924         }
 925     }
 926
 927     /* If we have an interrupt but the guest is not ready to receive an
 928      * interrupt, request an interrupt window exit.  This will
 929      * cause a return to userspace as soon as the guest is ready to
 930      * receive interrupts. */
 931     if ((env->interrupt_request & CPU_INTERRUPT_HARD))
 932         run->request_interrupt_window = 1;
 933     else
 934         run->request_interrupt_window = 0;
 935
 936     dprintf("setting tpr\n");
 937     run->cr8 = cpu_get_apic_tpr(env);
 938
 939     return 0;
 940 }
 941
 942 int kvm_arch_post_run(CPUState *env, struct kvm_run *run)
 943 {
 944     if (run->if_flag)
 945         env->eflags |= IF_MASK;
 946     else
 947         env->eflags &= ~IF_MASK;
 948
 949     cpu_set_apic_tpr(env, run->cr8);
 950     cpu_set_apic_base(env, run->apic_base);
 951
 952     return 0;
 953 }
 954
 955 static int kvm_handle_halt(CPUState *env)
 956 {
 957     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
 958           (env->eflags & IF_MASK)) &&
 959         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
 960         env->halted = 1;
 961         env->exception_index = EXCP_HLT;
 962         return 0;
 963     }
 964
 965     return 1;
 966 }
 967
 968 int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
 969 {
 970     int ret = 0;
 971
 972     switch (run->exit_reason) {
 973     case KVM_EXIT_HLT:
 974         dprintf("handle_hlt\n");
 975         ret = kvm_handle_halt(env);
 976         break;
 977     }
 978
 979     return ret;
 980 }
 981
 982 #ifdef KVM_CAP_SET_GUEST_DEBUG
 983 int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
 984 {
 985     static const uint8_t int3 = 0xcc;
 986
 987     if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
 988         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1))
 989         return -EINVAL;
 990     return 0;
 991 }
 992
 993 int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
 994 {
 995     uint8_t int3;
 996
 997     if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
 998         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1))
 999         return -EINVAL;
1000     return 0;
1001 }
1002
1003 static struct {
1004     target_ulong addr;
1005     int len;
1006     int type;
1007 } hw_breakpoint[4];
1008
1009 static int nb_hw_breakpoint;
1010
1011 static int find_hw_breakpoint(target_ulong addr, int len, int type)
1012 {
1013     int n;
1014
1015     for (n = 0; n < nb_hw_breakpoint; n++)
1016         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1017             (hw_breakpoint[n].len == len || len == -1))
1018             return n;
1019     return -1;
1020 }
1021
1022 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1023                                   target_ulong len, int type)
1024 {
1025     switch (type) {
1026     case GDB_BREAKPOINT_HW:
1027         len = 1;
1028         break;
1029     case GDB_WATCHPOINT_WRITE:
1030     case GDB_WATCHPOINT_ACCESS:
1031         switch (len) {
1032         case 1:
1033             break;
1034         case 2:
1035         case 4:
1036         case 8:
1037             if (addr & (len - 1))
1038                 return -EINVAL;
1039             break;
1040         default:
1041             return -EINVAL;
1042         }
1043         break;
1044     default:
1045         return -ENOSYS;
1046     }
1047
1048     if (nb_hw_breakpoint == 4)
1049         return -ENOBUFS;
1050
1051     if (find_hw_breakpoint(addr, len, type) >= 0)
1052         return -EEXIST;
1053
1054     hw_breakpoint[nb_hw_breakpoint].addr = addr;
1055     hw_breakpoint[nb_hw_breakpoint].len = len;
1056     hw_breakpoint[nb_hw_breakpoint].type = type;
1057     nb_hw_breakpoint++;
1058
1059     return 0;
1060 }
1061
1062 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1063                                   target_ulong len, int type)
1064 {
1065     int n;
1066
1067     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1068     if (n < 0)
1069         return -ENOENT;
1070
1071     nb_hw_breakpoint--;
1072     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1073
1074     return 0;
1075 }
1076
1077 void kvm_arch_remove_all_hw_breakpoints(void)
1078 {
1079     nb_hw_breakpoint = 0;
1080 }
1081
1082 static CPUWatchpoint hw_watchpoint;
1083
1084 int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
1085 {
1086     int handle = 0;
1087     int n;
1088
1089     if (arch_info->exception == 1) {
1090         if (arch_info->dr6 & (1 << 14)) {
1091             if (cpu_single_env->singlestep_enabled)
1092                 handle = 1;
1093         } else {
1094             for (n = 0; n < 4; n++)
1095                 if (arch_info->dr6 & (1 << n))
1096                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1097                     case 0x0:
1098                         handle = 1;
1099                         break;
1100                     case 0x1:
1101                         handle = 1;
1102                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1103                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1104                         hw_watchpoint.flags = BP_MEM_WRITE;
1105                         break;
1106                     case 0x3:
1107                         handle = 1;
1108                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1109                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1110                         hw_watchpoint.flags = BP_MEM_ACCESS;
1111                         break;
1112                     }
1113         }
1114     } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc))
1115         handle = 1;
1116
1117     if (!handle)
1118         kvm_update_guest_debug(cpu_single_env,
1119                         (arch_info->exception == 1) ?
1120                         KVM_GUESTDBG_INJECT_DB : KVM_GUESTDBG_INJECT_BP);
1121
1122     return handle;
1123 }
1124
1125 void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
1126 {
1127     const uint8_t type_code[] = {
1128         [GDB_BREAKPOINT_HW] = 0x0,
1129         [GDB_WATCHPOINT_WRITE] = 0x1,
1130         [GDB_WATCHPOINT_ACCESS] = 0x3
1131     };
1132     const uint8_t len_code[] = {
1133         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1134     };
1135     int n;
1136
1137     if (kvm_sw_breakpoints_active(env))
1138         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1139
1140     if (nb_hw_breakpoint > 0) {
1141         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1142         dbg->arch.debugreg[7] = 0x0600;
1143         for (n = 0; n < nb_hw_breakpoint; n++) {
1144             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
1145             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
1146                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
1147                 (len_code[hw_breakpoint[n].len] << (18 + n*4));
1148         }
1149     }
1150 }
1151 #endif /* KVM_CAP_SET_GUEST_DEBUG */