4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
8 * Anthony Liguori <aliguori@us.ibm.com>
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
15 #include <sys/types.h>
16 #include <sys/ioctl.h>
18 #include <sys/utsname.h>
20 #include <linux/kvm.h>
21 #include <linux/kvm_para.h>
23 #include "qemu-common.h"
28 #include "host-utils.h"
36 #define DPRINTF(fmt, ...) \
37 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
39 #define DPRINTF(fmt, ...) \
43 #define MSR_KVM_WALL_CLOCK 0x11
44 #define MSR_KVM_SYSTEM_TIME 0x12
47 #define BUS_MCEERR_AR 4
50 #define BUS_MCEERR_AO 5
53 const KVMCapabilityInfo kvm_arch_required_capabilities
[] = {
54 KVM_CAP_INFO(SET_TSS_ADDR
),
55 KVM_CAP_INFO(EXT_CPUID
),
56 KVM_CAP_INFO(MP_STATE
),
60 static bool has_msr_star
;
61 static bool has_msr_hsave_pa
;
62 static bool has_msr_async_pf_en
;
63 static int lm_capable_kernel
;
65 static struct kvm_cpuid2
*try_get_cpuid(KVMState
*s
, int max
)
67 struct kvm_cpuid2
*cpuid
;
70 size
= sizeof(*cpuid
) + max
* sizeof(*cpuid
->entries
);
71 cpuid
= (struct kvm_cpuid2
*)qemu_mallocz(size
);
73 r
= kvm_ioctl(s
, KVM_GET_SUPPORTED_CPUID
, cpuid
);
74 if (r
== 0 && cpuid
->nent
>= max
) {
82 fprintf(stderr
, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
90 struct kvm_para_features
{
94 { KVM_CAP_CLOCKSOURCE
, KVM_FEATURE_CLOCKSOURCE
},
95 { KVM_CAP_NOP_IO_DELAY
, KVM_FEATURE_NOP_IO_DELAY
},
96 { KVM_CAP_PV_MMU
, KVM_FEATURE_MMU_OP
},
97 #ifdef KVM_CAP_ASYNC_PF
98 { KVM_CAP_ASYNC_PF
, KVM_FEATURE_ASYNC_PF
},
103 static int get_para_features(CPUState
*env
)
107 for (i
= 0; i
< ARRAY_SIZE(para_features
) - 1; i
++) {
108 if (kvm_check_extension(env
->kvm_state
, para_features
[i
].cap
)) {
109 features
|= (1 << para_features
[i
].feature
);
117 uint32_t kvm_arch_get_supported_cpuid(CPUState
*env
, uint32_t function
,
118 uint32_t index
, int reg
)
120 struct kvm_cpuid2
*cpuid
;
123 uint32_t cpuid_1_edx
;
124 int has_kvm_features
= 0;
127 while ((cpuid
= try_get_cpuid(env
->kvm_state
, max
)) == NULL
) {
131 for (i
= 0; i
< cpuid
->nent
; ++i
) {
132 if (cpuid
->entries
[i
].function
== function
&&
133 cpuid
->entries
[i
].index
== index
) {
134 if (cpuid
->entries
[i
].function
== KVM_CPUID_FEATURES
) {
135 has_kvm_features
= 1;
139 ret
= cpuid
->entries
[i
].eax
;
142 ret
= cpuid
->entries
[i
].ebx
;
145 ret
= cpuid
->entries
[i
].ecx
;
148 ret
= cpuid
->entries
[i
].edx
;
151 /* KVM before 2.6.30 misreports the following features */
152 ret
|= CPUID_MTRR
| CPUID_PAT
| CPUID_MCE
| CPUID_MCA
;
155 /* On Intel, kvm returns cpuid according to the Intel spec,
156 * so add missing bits according to the AMD spec:
158 cpuid_1_edx
= kvm_arch_get_supported_cpuid(env
, 1, 0, R_EDX
);
159 ret
|= cpuid_1_edx
& 0x183f7ff;
169 /* fallback for older kernels */
170 if (!has_kvm_features
&& (function
== KVM_CPUID_FEATURES
)) {
171 ret
= get_para_features(env
);
177 typedef struct HWPoisonPage
{
179 QLIST_ENTRY(HWPoisonPage
) list
;
182 static QLIST_HEAD(, HWPoisonPage
) hwpoison_page_list
=
183 QLIST_HEAD_INITIALIZER(hwpoison_page_list
);
185 static void kvm_unpoison_all(void *param
)
187 HWPoisonPage
*page
, *next_page
;
189 QLIST_FOREACH_SAFE(page
, &hwpoison_page_list
, list
, next_page
) {
190 QLIST_REMOVE(page
, list
);
191 qemu_ram_remap(page
->ram_addr
, TARGET_PAGE_SIZE
);
197 static void kvm_hwpoison_page_add(ram_addr_t ram_addr
)
201 QLIST_FOREACH(page
, &hwpoison_page_list
, list
) {
202 if (page
->ram_addr
== ram_addr
) {
206 page
= qemu_malloc(sizeof(HWPoisonPage
));
207 page
->ram_addr
= ram_addr
;
208 QLIST_INSERT_HEAD(&hwpoison_page_list
, page
, list
);
211 static int kvm_get_mce_cap_supported(KVMState
*s
, uint64_t *mce_cap
,
216 r
= kvm_check_extension(s
, KVM_CAP_MCE
);
219 return kvm_ioctl(s
, KVM_X86_GET_MCE_CAP_SUPPORTED
, mce_cap
);
224 static void kvm_mce_inject(CPUState
*env
, target_phys_addr_t paddr
, int code
)
226 uint64_t status
= MCI_STATUS_VAL
| MCI_STATUS_UC
| MCI_STATUS_EN
|
227 MCI_STATUS_MISCV
| MCI_STATUS_ADDRV
| MCI_STATUS_S
;
228 uint64_t mcg_status
= MCG_STATUS_MCIP
;
230 if (code
== BUS_MCEERR_AR
) {
231 status
|= MCI_STATUS_AR
| 0x134;
232 mcg_status
|= MCG_STATUS_EIPV
;
235 mcg_status
|= MCG_STATUS_RIPV
;
237 cpu_x86_inject_mce(NULL
, env
, 9, status
, mcg_status
, paddr
,
238 (MCM_ADDR_PHYS
<< 6) | 0xc,
239 cpu_x86_support_mca_broadcast(env
) ?
240 MCE_INJECT_BROADCAST
: 0);
242 #endif /* KVM_CAP_MCE */
244 static void hardware_memory_error(void)
246 fprintf(stderr
, "Hardware memory error!\n");
250 int kvm_arch_on_sigbus_vcpu(CPUState
*env
, int code
, void *addr
)
254 target_phys_addr_t paddr
;
256 if ((env
->mcg_cap
& MCG_SER_P
) && addr
257 && (code
== BUS_MCEERR_AR
|| code
== BUS_MCEERR_AO
)) {
258 if (qemu_ram_addr_from_host(addr
, &ram_addr
) ||
259 !kvm_physical_memory_addr_from_ram(env
->kvm_state
, ram_addr
,
261 fprintf(stderr
, "Hardware memory error for memory used by "
262 "QEMU itself instead of guest system!\n");
263 /* Hope we are lucky for AO MCE */
264 if (code
== BUS_MCEERR_AO
) {
267 hardware_memory_error();
270 kvm_hwpoison_page_add(ram_addr
);
271 kvm_mce_inject(env
, paddr
, code
);
273 #endif /* KVM_CAP_MCE */
275 if (code
== BUS_MCEERR_AO
) {
277 } else if (code
== BUS_MCEERR_AR
) {
278 hardware_memory_error();
286 int kvm_arch_on_sigbus(int code
, void *addr
)
289 if ((first_cpu
->mcg_cap
& MCG_SER_P
) && addr
&& code
== BUS_MCEERR_AO
) {
291 target_phys_addr_t paddr
;
293 /* Hope we are lucky for AO MCE */
294 if (qemu_ram_addr_from_host(addr
, &ram_addr
) ||
295 !kvm_physical_memory_addr_from_ram(first_cpu
->kvm_state
, ram_addr
,
297 fprintf(stderr
, "Hardware memory error for memory used by "
298 "QEMU itself instead of guest system!: %p\n", addr
);
301 kvm_hwpoison_page_add(ram_addr
);
302 kvm_mce_inject(first_cpu
, paddr
, code
);
304 #endif /* KVM_CAP_MCE */
306 if (code
== BUS_MCEERR_AO
) {
308 } else if (code
== BUS_MCEERR_AR
) {
309 hardware_memory_error();
317 static int kvm_inject_mce_oldstyle(CPUState
*env
)
320 if (!kvm_has_vcpu_events() && env
->exception_injected
== EXCP12_MCHK
) {
321 unsigned int bank
, bank_num
= env
->mcg_cap
& 0xff;
322 struct kvm_x86_mce mce
;
324 env
->exception_injected
= -1;
327 * There must be at least one bank in use if an MCE is pending.
328 * Find it and use its values for the event injection.
330 for (bank
= 0; bank
< bank_num
; bank
++) {
331 if (env
->mce_banks
[bank
* 4 + 1] & MCI_STATUS_VAL
) {
335 assert(bank
< bank_num
);
338 mce
.status
= env
->mce_banks
[bank
* 4 + 1];
339 mce
.mcg_status
= env
->mcg_status
;
340 mce
.addr
= env
->mce_banks
[bank
* 4 + 2];
341 mce
.misc
= env
->mce_banks
[bank
* 4 + 3];
343 return kvm_vcpu_ioctl(env
, KVM_X86_SET_MCE
, &mce
);
345 #endif /* KVM_CAP_MCE */
349 static void cpu_update_state(void *opaque
, int running
, int reason
)
351 CPUState
*env
= opaque
;
354 env
->tsc_valid
= false;
358 int kvm_arch_init_vcpu(CPUState
*env
)
361 struct kvm_cpuid2 cpuid
;
362 struct kvm_cpuid_entry2 entries
[100];
363 } __attribute__((packed
)) cpuid_data
;
364 uint32_t limit
, i
, j
, cpuid_i
;
366 struct kvm_cpuid_entry2
*c
;
367 uint32_t signature
[3];
369 env
->cpuid_features
&= kvm_arch_get_supported_cpuid(env
, 1, 0, R_EDX
);
371 i
= env
->cpuid_ext_features
& CPUID_EXT_HYPERVISOR
;
372 env
->cpuid_ext_features
&= kvm_arch_get_supported_cpuid(env
, 1, 0, R_ECX
);
373 env
->cpuid_ext_features
|= i
;
375 env
->cpuid_ext2_features
&= kvm_arch_get_supported_cpuid(env
, 0x80000001,
377 env
->cpuid_ext3_features
&= kvm_arch_get_supported_cpuid(env
, 0x80000001,
379 env
->cpuid_svm_features
&= kvm_arch_get_supported_cpuid(env
, 0x8000000A,
385 /* Paravirtualization CPUIDs */
386 memcpy(signature
, "KVMKVMKVM\0\0\0", 12);
387 c
= &cpuid_data
.entries
[cpuid_i
++];
388 memset(c
, 0, sizeof(*c
));
389 c
->function
= KVM_CPUID_SIGNATURE
;
391 c
->ebx
= signature
[0];
392 c
->ecx
= signature
[1];
393 c
->edx
= signature
[2];
395 c
= &cpuid_data
.entries
[cpuid_i
++];
396 memset(c
, 0, sizeof(*c
));
397 c
->function
= KVM_CPUID_FEATURES
;
398 c
->eax
= env
->cpuid_kvm_features
& kvm_arch_get_supported_cpuid(env
,
399 KVM_CPUID_FEATURES
, 0, R_EAX
);
401 #ifdef KVM_CAP_ASYNC_PF
402 has_msr_async_pf_en
= c
->eax
& (1 << KVM_FEATURE_ASYNC_PF
);
405 cpu_x86_cpuid(env
, 0, 0, &limit
, &unused
, &unused
, &unused
);
407 for (i
= 0; i
<= limit
; i
++) {
408 c
= &cpuid_data
.entries
[cpuid_i
++];
412 /* Keep reading function 2 till all the input is received */
416 c
->flags
= KVM_CPUID_FLAG_STATEFUL_FUNC
|
417 KVM_CPUID_FLAG_STATE_READ_NEXT
;
418 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
419 times
= c
->eax
& 0xff;
421 for (j
= 1; j
< times
; ++j
) {
422 c
= &cpuid_data
.entries
[cpuid_i
++];
424 c
->flags
= KVM_CPUID_FLAG_STATEFUL_FUNC
;
425 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
434 c
->flags
= KVM_CPUID_FLAG_SIGNIFCANT_INDEX
;
436 cpu_x86_cpuid(env
, i
, j
, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
438 if (i
== 4 && c
->eax
== 0) {
441 if (i
== 0xb && !(c
->ecx
& 0xff00)) {
444 if (i
== 0xd && c
->eax
== 0) {
447 c
= &cpuid_data
.entries
[cpuid_i
++];
453 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
457 cpu_x86_cpuid(env
, 0x80000000, 0, &limit
, &unused
, &unused
, &unused
);
459 for (i
= 0x80000000; i
<= limit
; i
++) {
460 c
= &cpuid_data
.entries
[cpuid_i
++];
464 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
467 /* Call Centaur's CPUID instructions they are supported. */
468 if (env
->cpuid_xlevel2
> 0) {
469 env
->cpuid_ext4_features
&=
470 kvm_arch_get_supported_cpuid(env
, 0xC0000001, 0, R_EDX
);
471 cpu_x86_cpuid(env
, 0xC0000000, 0, &limit
, &unused
, &unused
, &unused
);
473 for (i
= 0xC0000000; i
<= limit
; i
++) {
474 c
= &cpuid_data
.entries
[cpuid_i
++];
478 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
482 cpuid_data
.cpuid
.nent
= cpuid_i
;
485 if (((env
->cpuid_version
>> 8)&0xF) >= 6
486 && (env
->cpuid_features
&(CPUID_MCE
|CPUID_MCA
)) == (CPUID_MCE
|CPUID_MCA
)
487 && kvm_check_extension(env
->kvm_state
, KVM_CAP_MCE
) > 0) {
492 ret
= kvm_get_mce_cap_supported(env
->kvm_state
, &mcg_cap
, &banks
);
494 fprintf(stderr
, "kvm_get_mce_cap_supported: %s", strerror(-ret
));
498 if (banks
> MCE_BANKS_DEF
) {
499 banks
= MCE_BANKS_DEF
;
501 mcg_cap
&= MCE_CAP_DEF
;
503 ret
= kvm_vcpu_ioctl(env
, KVM_X86_SETUP_MCE
, &mcg_cap
);
505 fprintf(stderr
, "KVM_X86_SETUP_MCE: %s", strerror(-ret
));
509 env
->mcg_cap
= mcg_cap
;
513 qemu_add_vm_change_state_handler(cpu_update_state
, env
);
515 return kvm_vcpu_ioctl(env
, KVM_SET_CPUID2
, &cpuid_data
);
518 void kvm_arch_reset_vcpu(CPUState
*env
)
520 env
->exception_injected
= -1;
521 env
->interrupt_injected
= -1;
523 if (kvm_irqchip_in_kernel()) {
524 env
->mp_state
= cpu_is_bsp(env
) ? KVM_MP_STATE_RUNNABLE
:
525 KVM_MP_STATE_UNINITIALIZED
;
527 env
->mp_state
= KVM_MP_STATE_RUNNABLE
;
531 static int kvm_get_supported_msrs(KVMState
*s
)
533 static int kvm_supported_msrs
;
537 if (kvm_supported_msrs
== 0) {
538 struct kvm_msr_list msr_list
, *kvm_msr_list
;
540 kvm_supported_msrs
= -1;
542 /* Obtain MSR list from KVM. These are the MSRs that we must
545 ret
= kvm_ioctl(s
, KVM_GET_MSR_INDEX_LIST
, &msr_list
);
546 if (ret
< 0 && ret
!= -E2BIG
) {
549 /* Old kernel modules had a bug and could write beyond the provided
550 memory. Allocate at least a safe amount of 1K. */
551 kvm_msr_list
= qemu_mallocz(MAX(1024, sizeof(msr_list
) +
553 sizeof(msr_list
.indices
[0])));
555 kvm_msr_list
->nmsrs
= msr_list
.nmsrs
;
556 ret
= kvm_ioctl(s
, KVM_GET_MSR_INDEX_LIST
, kvm_msr_list
);
560 for (i
= 0; i
< kvm_msr_list
->nmsrs
; i
++) {
561 if (kvm_msr_list
->indices
[i
] == MSR_STAR
) {
565 if (kvm_msr_list
->indices
[i
] == MSR_VM_HSAVE_PA
) {
566 has_msr_hsave_pa
= true;
572 qemu_free(kvm_msr_list
);
578 int kvm_arch_init(KVMState
*s
)
580 uint64_t identity_base
= 0xfffbc000;
582 struct utsname utsname
;
584 ret
= kvm_get_supported_msrs(s
);
590 lm_capable_kernel
= strcmp(utsname
.machine
, "x86_64") == 0;
593 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
594 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
595 * Since these must be part of guest physical memory, we need to allocate
596 * them, both by setting their start addresses in the kernel and by
597 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
599 * Older KVM versions may not support setting the identity map base. In
600 * that case we need to stick with the default, i.e. a 256K maximum BIOS
603 #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR
604 if (kvm_check_extension(s
, KVM_CAP_SET_IDENTITY_MAP_ADDR
)) {
605 /* Allows up to 16M BIOSes. */
606 identity_base
= 0xfeffc000;
608 ret
= kvm_vm_ioctl(s
, KVM_SET_IDENTITY_MAP_ADDR
, &identity_base
);
614 /* Set TSS base one page after EPT identity map. */
615 ret
= kvm_vm_ioctl(s
, KVM_SET_TSS_ADDR
, identity_base
+ 0x1000);
620 /* Tell fw_cfg to notify the BIOS to reserve the range. */
621 ret
= e820_add_entry(identity_base
, 0x4000, E820_RESERVED
);
623 fprintf(stderr
, "e820_add_entry() table is full\n");
626 qemu_register_reset(kvm_unpoison_all
, NULL
);
631 static void set_v8086_seg(struct kvm_segment
*lhs
, const SegmentCache
*rhs
)
633 lhs
->selector
= rhs
->selector
;
634 lhs
->base
= rhs
->base
;
635 lhs
->limit
= rhs
->limit
;
647 static void set_seg(struct kvm_segment
*lhs
, const SegmentCache
*rhs
)
649 unsigned flags
= rhs
->flags
;
650 lhs
->selector
= rhs
->selector
;
651 lhs
->base
= rhs
->base
;
652 lhs
->limit
= rhs
->limit
;
653 lhs
->type
= (flags
>> DESC_TYPE_SHIFT
) & 15;
654 lhs
->present
= (flags
& DESC_P_MASK
) != 0;
655 lhs
->dpl
= (flags
>> DESC_DPL_SHIFT
) & 3;
656 lhs
->db
= (flags
>> DESC_B_SHIFT
) & 1;
657 lhs
->s
= (flags
& DESC_S_MASK
) != 0;
658 lhs
->l
= (flags
>> DESC_L_SHIFT
) & 1;
659 lhs
->g
= (flags
& DESC_G_MASK
) != 0;
660 lhs
->avl
= (flags
& DESC_AVL_MASK
) != 0;
664 static void get_seg(SegmentCache
*lhs
, const struct kvm_segment
*rhs
)
666 lhs
->selector
= rhs
->selector
;
667 lhs
->base
= rhs
->base
;
668 lhs
->limit
= rhs
->limit
;
669 lhs
->flags
= (rhs
->type
<< DESC_TYPE_SHIFT
) |
670 (rhs
->present
* DESC_P_MASK
) |
671 (rhs
->dpl
<< DESC_DPL_SHIFT
) |
672 (rhs
->db
<< DESC_B_SHIFT
) |
673 (rhs
->s
* DESC_S_MASK
) |
674 (rhs
->l
<< DESC_L_SHIFT
) |
675 (rhs
->g
* DESC_G_MASK
) |
676 (rhs
->avl
* DESC_AVL_MASK
);
679 static void kvm_getput_reg(__u64
*kvm_reg
, target_ulong
*qemu_reg
, int set
)
682 *kvm_reg
= *qemu_reg
;
684 *qemu_reg
= *kvm_reg
;
688 static int kvm_getput_regs(CPUState
*env
, int set
)
690 struct kvm_regs regs
;
694 ret
= kvm_vcpu_ioctl(env
, KVM_GET_REGS
, ®s
);
700 kvm_getput_reg(®s
.rax
, &env
->regs
[R_EAX
], set
);
701 kvm_getput_reg(®s
.rbx
, &env
->regs
[R_EBX
], set
);
702 kvm_getput_reg(®s
.rcx
, &env
->regs
[R_ECX
], set
);
703 kvm_getput_reg(®s
.rdx
, &env
->regs
[R_EDX
], set
);
704 kvm_getput_reg(®s
.rsi
, &env
->regs
[R_ESI
], set
);
705 kvm_getput_reg(®s
.rdi
, &env
->regs
[R_EDI
], set
);
706 kvm_getput_reg(®s
.rsp
, &env
->regs
[R_ESP
], set
);
707 kvm_getput_reg(®s
.rbp
, &env
->regs
[R_EBP
], set
);
709 kvm_getput_reg(®s
.r8
, &env
->regs
[8], set
);
710 kvm_getput_reg(®s
.r9
, &env
->regs
[9], set
);
711 kvm_getput_reg(®s
.r10
, &env
->regs
[10], set
);
712 kvm_getput_reg(®s
.r11
, &env
->regs
[11], set
);
713 kvm_getput_reg(®s
.r12
, &env
->regs
[12], set
);
714 kvm_getput_reg(®s
.r13
, &env
->regs
[13], set
);
715 kvm_getput_reg(®s
.r14
, &env
->regs
[14], set
);
716 kvm_getput_reg(®s
.r15
, &env
->regs
[15], set
);
719 kvm_getput_reg(®s
.rflags
, &env
->eflags
, set
);
720 kvm_getput_reg(®s
.rip
, &env
->eip
, set
);
723 ret
= kvm_vcpu_ioctl(env
, KVM_SET_REGS
, ®s
);
729 static int kvm_put_fpu(CPUState
*env
)
734 memset(&fpu
, 0, sizeof fpu
);
735 fpu
.fsw
= env
->fpus
& ~(7 << 11);
736 fpu
.fsw
|= (env
->fpstt
& 7) << 11;
738 fpu
.last_opcode
= env
->fpop
;
739 fpu
.last_ip
= env
->fpip
;
740 fpu
.last_dp
= env
->fpdp
;
741 for (i
= 0; i
< 8; ++i
) {
742 fpu
.ftwx
|= (!env
->fptags
[i
]) << i
;
744 memcpy(fpu
.fpr
, env
->fpregs
, sizeof env
->fpregs
);
745 memcpy(fpu
.xmm
, env
->xmm_regs
, sizeof env
->xmm_regs
);
746 fpu
.mxcsr
= env
->mxcsr
;
748 return kvm_vcpu_ioctl(env
, KVM_SET_FPU
, &fpu
);
752 #define XSAVE_CWD_RIP 2
753 #define XSAVE_CWD_RDP 4
754 #define XSAVE_MXCSR 6
755 #define XSAVE_ST_SPACE 8
756 #define XSAVE_XMM_SPACE 40
757 #define XSAVE_XSTATE_BV 128
758 #define XSAVE_YMMH_SPACE 144
761 static int kvm_put_xsave(CPUState
*env
)
765 struct kvm_xsave
* xsave
;
766 uint16_t cwd
, swd
, twd
;
768 if (!kvm_has_xsave()) {
769 return kvm_put_fpu(env
);
772 xsave
= qemu_memalign(4096, sizeof(struct kvm_xsave
));
773 memset(xsave
, 0, sizeof(struct kvm_xsave
));
775 swd
= env
->fpus
& ~(7 << 11);
776 swd
|= (env
->fpstt
& 7) << 11;
778 for (i
= 0; i
< 8; ++i
) {
779 twd
|= (!env
->fptags
[i
]) << i
;
781 xsave
->region
[0] = (uint32_t)(swd
<< 16) + cwd
;
782 xsave
->region
[1] = (uint32_t)(env
->fpop
<< 16) + twd
;
783 memcpy(&xsave
->region
[XSAVE_CWD_RIP
], &env
->fpip
, sizeof(env
->fpip
));
784 memcpy(&xsave
->region
[XSAVE_CWD_RDP
], &env
->fpdp
, sizeof(env
->fpdp
));
785 memcpy(&xsave
->region
[XSAVE_ST_SPACE
], env
->fpregs
,
787 memcpy(&xsave
->region
[XSAVE_XMM_SPACE
], env
->xmm_regs
,
788 sizeof env
->xmm_regs
);
789 xsave
->region
[XSAVE_MXCSR
] = env
->mxcsr
;
790 *(uint64_t *)&xsave
->region
[XSAVE_XSTATE_BV
] = env
->xstate_bv
;
791 memcpy(&xsave
->region
[XSAVE_YMMH_SPACE
], env
->ymmh_regs
,
792 sizeof env
->ymmh_regs
);
793 r
= kvm_vcpu_ioctl(env
, KVM_SET_XSAVE
, xsave
);
797 return kvm_put_fpu(env
);
801 static int kvm_put_xcrs(CPUState
*env
)
804 struct kvm_xcrs xcrs
;
806 if (!kvm_has_xcrs()) {
812 xcrs
.xcrs
[0].xcr
= 0;
813 xcrs
.xcrs
[0].value
= env
->xcr0
;
814 return kvm_vcpu_ioctl(env
, KVM_SET_XCRS
, &xcrs
);
820 static int kvm_put_sregs(CPUState
*env
)
822 struct kvm_sregs sregs
;
824 memset(sregs
.interrupt_bitmap
, 0, sizeof(sregs
.interrupt_bitmap
));
825 if (env
->interrupt_injected
>= 0) {
826 sregs
.interrupt_bitmap
[env
->interrupt_injected
/ 64] |=
827 (uint64_t)1 << (env
->interrupt_injected
% 64);
830 if ((env
->eflags
& VM_MASK
)) {
831 set_v8086_seg(&sregs
.cs
, &env
->segs
[R_CS
]);
832 set_v8086_seg(&sregs
.ds
, &env
->segs
[R_DS
]);
833 set_v8086_seg(&sregs
.es
, &env
->segs
[R_ES
]);
834 set_v8086_seg(&sregs
.fs
, &env
->segs
[R_FS
]);
835 set_v8086_seg(&sregs
.gs
, &env
->segs
[R_GS
]);
836 set_v8086_seg(&sregs
.ss
, &env
->segs
[R_SS
]);
838 set_seg(&sregs
.cs
, &env
->segs
[R_CS
]);
839 set_seg(&sregs
.ds
, &env
->segs
[R_DS
]);
840 set_seg(&sregs
.es
, &env
->segs
[R_ES
]);
841 set_seg(&sregs
.fs
, &env
->segs
[R_FS
]);
842 set_seg(&sregs
.gs
, &env
->segs
[R_GS
]);
843 set_seg(&sregs
.ss
, &env
->segs
[R_SS
]);
846 set_seg(&sregs
.tr
, &env
->tr
);
847 set_seg(&sregs
.ldt
, &env
->ldt
);
849 sregs
.idt
.limit
= env
->idt
.limit
;
850 sregs
.idt
.base
= env
->idt
.base
;
851 sregs
.gdt
.limit
= env
->gdt
.limit
;
852 sregs
.gdt
.base
= env
->gdt
.base
;
854 sregs
.cr0
= env
->cr
[0];
855 sregs
.cr2
= env
->cr
[2];
856 sregs
.cr3
= env
->cr
[3];
857 sregs
.cr4
= env
->cr
[4];
859 sregs
.cr8
= cpu_get_apic_tpr(env
->apic_state
);
860 sregs
.apic_base
= cpu_get_apic_base(env
->apic_state
);
862 sregs
.efer
= env
->efer
;
864 return kvm_vcpu_ioctl(env
, KVM_SET_SREGS
, &sregs
);
867 static void kvm_msr_entry_set(struct kvm_msr_entry
*entry
,
868 uint32_t index
, uint64_t value
)
870 entry
->index
= index
;
874 static int kvm_put_msrs(CPUState
*env
, int level
)
877 struct kvm_msrs info
;
878 struct kvm_msr_entry entries
[100];
880 struct kvm_msr_entry
*msrs
= msr_data
.entries
;
883 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_SYSENTER_CS
, env
->sysenter_cs
);
884 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_SYSENTER_ESP
, env
->sysenter_esp
);
885 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_SYSENTER_EIP
, env
->sysenter_eip
);
886 kvm_msr_entry_set(&msrs
[n
++], MSR_PAT
, env
->pat
);
888 kvm_msr_entry_set(&msrs
[n
++], MSR_STAR
, env
->star
);
890 if (has_msr_hsave_pa
) {
891 kvm_msr_entry_set(&msrs
[n
++], MSR_VM_HSAVE_PA
, env
->vm_hsave
);
894 if (lm_capable_kernel
) {
895 kvm_msr_entry_set(&msrs
[n
++], MSR_CSTAR
, env
->cstar
);
896 kvm_msr_entry_set(&msrs
[n
++], MSR_KERNELGSBASE
, env
->kernelgsbase
);
897 kvm_msr_entry_set(&msrs
[n
++], MSR_FMASK
, env
->fmask
);
898 kvm_msr_entry_set(&msrs
[n
++], MSR_LSTAR
, env
->lstar
);
901 if (level
== KVM_PUT_FULL_STATE
) {
903 * KVM is yet unable to synchronize TSC values of multiple VCPUs on
904 * writeback. Until this is fixed, we only write the offset to SMP
905 * guests after migration, desynchronizing the VCPUs, but avoiding
906 * huge jump-backs that would occur without any writeback at all.
908 if (smp_cpus
== 1 || env
->tsc
!= 0) {
909 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_TSC
, env
->tsc
);
913 * The following paravirtual MSRs have side effects on the guest or are
914 * too heavy for normal writeback. Limit them to reset or full state
917 if (level
>= KVM_PUT_RESET_STATE
) {
918 kvm_msr_entry_set(&msrs
[n
++], MSR_KVM_SYSTEM_TIME
,
919 env
->system_time_msr
);
920 kvm_msr_entry_set(&msrs
[n
++], MSR_KVM_WALL_CLOCK
, env
->wall_clock_msr
);
921 if (has_msr_async_pf_en
) {
922 kvm_msr_entry_set(&msrs
[n
++], MSR_KVM_ASYNC_PF_EN
,
923 env
->async_pf_en_msr
);
930 kvm_msr_entry_set(&msrs
[n
++], MSR_MCG_STATUS
, env
->mcg_status
);
931 kvm_msr_entry_set(&msrs
[n
++], MSR_MCG_CTL
, env
->mcg_ctl
);
932 for (i
= 0; i
< (env
->mcg_cap
& 0xff) * 4; i
++) {
933 kvm_msr_entry_set(&msrs
[n
++], MSR_MC0_CTL
+ i
, env
->mce_banks
[i
]);
938 msr_data
.info
.nmsrs
= n
;
940 return kvm_vcpu_ioctl(env
, KVM_SET_MSRS
, &msr_data
);
945 static int kvm_get_fpu(CPUState
*env
)
950 ret
= kvm_vcpu_ioctl(env
, KVM_GET_FPU
, &fpu
);
955 env
->fpstt
= (fpu
.fsw
>> 11) & 7;
958 env
->fpop
= fpu
.last_opcode
;
959 env
->fpip
= fpu
.last_ip
;
960 env
->fpdp
= fpu
.last_dp
;
961 for (i
= 0; i
< 8; ++i
) {
962 env
->fptags
[i
] = !((fpu
.ftwx
>> i
) & 1);
964 memcpy(env
->fpregs
, fpu
.fpr
, sizeof env
->fpregs
);
965 memcpy(env
->xmm_regs
, fpu
.xmm
, sizeof env
->xmm_regs
);
966 env
->mxcsr
= fpu
.mxcsr
;
971 static int kvm_get_xsave(CPUState
*env
)
974 struct kvm_xsave
* xsave
;
976 uint16_t cwd
, swd
, twd
;
978 if (!kvm_has_xsave()) {
979 return kvm_get_fpu(env
);
982 xsave
= qemu_memalign(4096, sizeof(struct kvm_xsave
));
983 ret
= kvm_vcpu_ioctl(env
, KVM_GET_XSAVE
, xsave
);
989 cwd
= (uint16_t)xsave
->region
[0];
990 swd
= (uint16_t)(xsave
->region
[0] >> 16);
991 twd
= (uint16_t)xsave
->region
[1];
992 env
->fpop
= (uint16_t)(xsave
->region
[1] >> 16);
993 env
->fpstt
= (swd
>> 11) & 7;
996 for (i
= 0; i
< 8; ++i
) {
997 env
->fptags
[i
] = !((twd
>> i
) & 1);
999 memcpy(&env
->fpip
, &xsave
->region
[XSAVE_CWD_RIP
], sizeof(env
->fpip
));
1000 memcpy(&env
->fpdp
, &xsave
->region
[XSAVE_CWD_RDP
], sizeof(env
->fpdp
));
1001 env
->mxcsr
= xsave
->region
[XSAVE_MXCSR
];
1002 memcpy(env
->fpregs
, &xsave
->region
[XSAVE_ST_SPACE
],
1003 sizeof env
->fpregs
);
1004 memcpy(env
->xmm_regs
, &xsave
->region
[XSAVE_XMM_SPACE
],
1005 sizeof env
->xmm_regs
);
1006 env
->xstate_bv
= *(uint64_t *)&xsave
->region
[XSAVE_XSTATE_BV
];
1007 memcpy(env
->ymmh_regs
, &xsave
->region
[XSAVE_YMMH_SPACE
],
1008 sizeof env
->ymmh_regs
);
1012 return kvm_get_fpu(env
);
1016 static int kvm_get_xcrs(CPUState
*env
)
1020 struct kvm_xcrs xcrs
;
1022 if (!kvm_has_xcrs()) {
1026 ret
= kvm_vcpu_ioctl(env
, KVM_GET_XCRS
, &xcrs
);
1031 for (i
= 0; i
< xcrs
.nr_xcrs
; i
++) {
1032 /* Only support xcr0 now */
1033 if (xcrs
.xcrs
[0].xcr
== 0) {
1034 env
->xcr0
= xcrs
.xcrs
[0].value
;
1044 static int kvm_get_sregs(CPUState
*env
)
1046 struct kvm_sregs sregs
;
1050 ret
= kvm_vcpu_ioctl(env
, KVM_GET_SREGS
, &sregs
);
1055 /* There can only be one pending IRQ set in the bitmap at a time, so try
1056 to find it and save its number instead (-1 for none). */
1057 env
->interrupt_injected
= -1;
1058 for (i
= 0; i
< ARRAY_SIZE(sregs
.interrupt_bitmap
); i
++) {
1059 if (sregs
.interrupt_bitmap
[i
]) {
1060 bit
= ctz64(sregs
.interrupt_bitmap
[i
]);
1061 env
->interrupt_injected
= i
* 64 + bit
;
1066 get_seg(&env
->segs
[R_CS
], &sregs
.cs
);
1067 get_seg(&env
->segs
[R_DS
], &sregs
.ds
);
1068 get_seg(&env
->segs
[R_ES
], &sregs
.es
);
1069 get_seg(&env
->segs
[R_FS
], &sregs
.fs
);
1070 get_seg(&env
->segs
[R_GS
], &sregs
.gs
);
1071 get_seg(&env
->segs
[R_SS
], &sregs
.ss
);
1073 get_seg(&env
->tr
, &sregs
.tr
);
1074 get_seg(&env
->ldt
, &sregs
.ldt
);
1076 env
->idt
.limit
= sregs
.idt
.limit
;
1077 env
->idt
.base
= sregs
.idt
.base
;
1078 env
->gdt
.limit
= sregs
.gdt
.limit
;
1079 env
->gdt
.base
= sregs
.gdt
.base
;
1081 env
->cr
[0] = sregs
.cr0
;
1082 env
->cr
[2] = sregs
.cr2
;
1083 env
->cr
[3] = sregs
.cr3
;
1084 env
->cr
[4] = sregs
.cr4
;
1086 cpu_set_apic_base(env
->apic_state
, sregs
.apic_base
);
1088 env
->efer
= sregs
.efer
;
1089 //cpu_set_apic_tpr(env->apic_state, sregs.cr8);
1091 #define HFLAG_COPY_MASK \
1092 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1093 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1094 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1095 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1097 hflags
= (env
->segs
[R_CS
].flags
>> DESC_DPL_SHIFT
) & HF_CPL_MASK
;
1098 hflags
|= (env
->cr
[0] & CR0_PE_MASK
) << (HF_PE_SHIFT
- CR0_PE_SHIFT
);
1099 hflags
|= (env
->cr
[0] << (HF_MP_SHIFT
- CR0_MP_SHIFT
)) &
1100 (HF_MP_MASK
| HF_EM_MASK
| HF_TS_MASK
);
1101 hflags
|= (env
->eflags
& (HF_TF_MASK
| HF_VM_MASK
| HF_IOPL_MASK
));
1102 hflags
|= (env
->cr
[4] & CR4_OSFXSR_MASK
) <<
1103 (HF_OSFXSR_SHIFT
- CR4_OSFXSR_SHIFT
);
1105 if (env
->efer
& MSR_EFER_LMA
) {
1106 hflags
|= HF_LMA_MASK
;
1109 if ((hflags
& HF_LMA_MASK
) && (env
->segs
[R_CS
].flags
& DESC_L_MASK
)) {
1110 hflags
|= HF_CS32_MASK
| HF_SS32_MASK
| HF_CS64_MASK
;
1112 hflags
|= (env
->segs
[R_CS
].flags
& DESC_B_MASK
) >>
1113 (DESC_B_SHIFT
- HF_CS32_SHIFT
);
1114 hflags
|= (env
->segs
[R_SS
].flags
& DESC_B_MASK
) >>
1115 (DESC_B_SHIFT
- HF_SS32_SHIFT
);
1116 if (!(env
->cr
[0] & CR0_PE_MASK
) || (env
->eflags
& VM_MASK
) ||
1117 !(hflags
& HF_CS32_MASK
)) {
1118 hflags
|= HF_ADDSEG_MASK
;
1120 hflags
|= ((env
->segs
[R_DS
].base
| env
->segs
[R_ES
].base
|
1121 env
->segs
[R_SS
].base
) != 0) << HF_ADDSEG_SHIFT
;
1124 env
->hflags
= (env
->hflags
& HFLAG_COPY_MASK
) | hflags
;
1129 static int kvm_get_msrs(CPUState
*env
)
1132 struct kvm_msrs info
;
1133 struct kvm_msr_entry entries
[100];
1135 struct kvm_msr_entry
*msrs
= msr_data
.entries
;
1139 msrs
[n
++].index
= MSR_IA32_SYSENTER_CS
;
1140 msrs
[n
++].index
= MSR_IA32_SYSENTER_ESP
;
1141 msrs
[n
++].index
= MSR_IA32_SYSENTER_EIP
;
1142 msrs
[n
++].index
= MSR_PAT
;
1144 msrs
[n
++].index
= MSR_STAR
;
1146 if (has_msr_hsave_pa
) {
1147 msrs
[n
++].index
= MSR_VM_HSAVE_PA
;
1150 if (!env
->tsc_valid
) {
1151 msrs
[n
++].index
= MSR_IA32_TSC
;
1152 env
->tsc_valid
= !vm_running
;
1155 #ifdef TARGET_X86_64
1156 if (lm_capable_kernel
) {
1157 msrs
[n
++].index
= MSR_CSTAR
;
1158 msrs
[n
++].index
= MSR_KERNELGSBASE
;
1159 msrs
[n
++].index
= MSR_FMASK
;
1160 msrs
[n
++].index
= MSR_LSTAR
;
1163 msrs
[n
++].index
= MSR_KVM_SYSTEM_TIME
;
1164 msrs
[n
++].index
= MSR_KVM_WALL_CLOCK
;
1165 if (has_msr_async_pf_en
) {
1166 msrs
[n
++].index
= MSR_KVM_ASYNC_PF_EN
;
1171 msrs
[n
++].index
= MSR_MCG_STATUS
;
1172 msrs
[n
++].index
= MSR_MCG_CTL
;
1173 for (i
= 0; i
< (env
->mcg_cap
& 0xff) * 4; i
++) {
1174 msrs
[n
++].index
= MSR_MC0_CTL
+ i
;
1179 msr_data
.info
.nmsrs
= n
;
1180 ret
= kvm_vcpu_ioctl(env
, KVM_GET_MSRS
, &msr_data
);
1185 for (i
= 0; i
< ret
; i
++) {
1186 switch (msrs
[i
].index
) {
1187 case MSR_IA32_SYSENTER_CS
:
1188 env
->sysenter_cs
= msrs
[i
].data
;
1190 case MSR_IA32_SYSENTER_ESP
:
1191 env
->sysenter_esp
= msrs
[i
].data
;
1193 case MSR_IA32_SYSENTER_EIP
:
1194 env
->sysenter_eip
= msrs
[i
].data
;
1197 env
->pat
= msrs
[i
].data
;
1200 env
->star
= msrs
[i
].data
;
1202 #ifdef TARGET_X86_64
1204 env
->cstar
= msrs
[i
].data
;
1206 case MSR_KERNELGSBASE
:
1207 env
->kernelgsbase
= msrs
[i
].data
;
1210 env
->fmask
= msrs
[i
].data
;
1213 env
->lstar
= msrs
[i
].data
;
1217 env
->tsc
= msrs
[i
].data
;
1219 case MSR_VM_HSAVE_PA
:
1220 env
->vm_hsave
= msrs
[i
].data
;
1222 case MSR_KVM_SYSTEM_TIME
:
1223 env
->system_time_msr
= msrs
[i
].data
;
1225 case MSR_KVM_WALL_CLOCK
:
1226 env
->wall_clock_msr
= msrs
[i
].data
;
1229 case MSR_MCG_STATUS
:
1230 env
->mcg_status
= msrs
[i
].data
;
1233 env
->mcg_ctl
= msrs
[i
].data
;
1238 if (msrs
[i
].index
>= MSR_MC0_CTL
&&
1239 msrs
[i
].index
< MSR_MC0_CTL
+ (env
->mcg_cap
& 0xff) * 4) {
1240 env
->mce_banks
[msrs
[i
].index
- MSR_MC0_CTL
] = msrs
[i
].data
;
1244 case MSR_KVM_ASYNC_PF_EN
:
1245 env
->async_pf_en_msr
= msrs
[i
].data
;
1253 static int kvm_put_mp_state(CPUState
*env
)
1255 struct kvm_mp_state mp_state
= { .mp_state
= env
->mp_state
};
1257 return kvm_vcpu_ioctl(env
, KVM_SET_MP_STATE
, &mp_state
);
1260 static int kvm_get_mp_state(CPUState
*env
)
1262 struct kvm_mp_state mp_state
;
1265 ret
= kvm_vcpu_ioctl(env
, KVM_GET_MP_STATE
, &mp_state
);
1269 env
->mp_state
= mp_state
.mp_state
;
1270 if (kvm_irqchip_in_kernel()) {
1271 env
->halted
= (mp_state
.mp_state
== KVM_MP_STATE_HALTED
);
1276 static int kvm_put_vcpu_events(CPUState
*env
, int level
)
1278 #ifdef KVM_CAP_VCPU_EVENTS
1279 struct kvm_vcpu_events events
;
1281 if (!kvm_has_vcpu_events()) {
1285 events
.exception
.injected
= (env
->exception_injected
>= 0);
1286 events
.exception
.nr
= env
->exception_injected
;
1287 events
.exception
.has_error_code
= env
->has_error_code
;
1288 events
.exception
.error_code
= env
->error_code
;
1290 events
.interrupt
.injected
= (env
->interrupt_injected
>= 0);
1291 events
.interrupt
.nr
= env
->interrupt_injected
;
1292 events
.interrupt
.soft
= env
->soft_interrupt
;
1294 events
.nmi
.injected
= env
->nmi_injected
;
1295 events
.nmi
.pending
= env
->nmi_pending
;
1296 events
.nmi
.masked
= !!(env
->hflags2
& HF2_NMI_MASK
);
1298 events
.sipi_vector
= env
->sipi_vector
;
1301 if (level
>= KVM_PUT_RESET_STATE
) {
1303 KVM_VCPUEVENT_VALID_NMI_PENDING
| KVM_VCPUEVENT_VALID_SIPI_VECTOR
;
1306 return kvm_vcpu_ioctl(env
, KVM_SET_VCPU_EVENTS
, &events
);
1312 static int kvm_get_vcpu_events(CPUState
*env
)
1314 #ifdef KVM_CAP_VCPU_EVENTS
1315 struct kvm_vcpu_events events
;
1318 if (!kvm_has_vcpu_events()) {
1322 ret
= kvm_vcpu_ioctl(env
, KVM_GET_VCPU_EVENTS
, &events
);
1326 env
->exception_injected
=
1327 events
.exception
.injected
? events
.exception
.nr
: -1;
1328 env
->has_error_code
= events
.exception
.has_error_code
;
1329 env
->error_code
= events
.exception
.error_code
;
1331 env
->interrupt_injected
=
1332 events
.interrupt
.injected
? events
.interrupt
.nr
: -1;
1333 env
->soft_interrupt
= events
.interrupt
.soft
;
1335 env
->nmi_injected
= events
.nmi
.injected
;
1336 env
->nmi_pending
= events
.nmi
.pending
;
1337 if (events
.nmi
.masked
) {
1338 env
->hflags2
|= HF2_NMI_MASK
;
1340 env
->hflags2
&= ~HF2_NMI_MASK
;
1343 env
->sipi_vector
= events
.sipi_vector
;
1349 static int kvm_guest_debug_workarounds(CPUState
*env
)
1352 #ifdef KVM_CAP_SET_GUEST_DEBUG
1353 unsigned long reinject_trap
= 0;
1355 if (!kvm_has_vcpu_events()) {
1356 if (env
->exception_injected
== 1) {
1357 reinject_trap
= KVM_GUESTDBG_INJECT_DB
;
1358 } else if (env
->exception_injected
== 3) {
1359 reinject_trap
= KVM_GUESTDBG_INJECT_BP
;
1361 env
->exception_injected
= -1;
1365 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1366 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1367 * by updating the debug state once again if single-stepping is on.
1368 * Another reason to call kvm_update_guest_debug here is a pending debug
1369 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1370 * reinject them via SET_GUEST_DEBUG.
1372 if (reinject_trap
||
1373 (!kvm_has_robust_singlestep() && env
->singlestep_enabled
)) {
1374 ret
= kvm_update_guest_debug(env
, reinject_trap
);
1376 #endif /* KVM_CAP_SET_GUEST_DEBUG */
1380 static int kvm_put_debugregs(CPUState
*env
)
1382 #ifdef KVM_CAP_DEBUGREGS
1383 struct kvm_debugregs dbgregs
;
1386 if (!kvm_has_debugregs()) {
1390 for (i
= 0; i
< 4; i
++) {
1391 dbgregs
.db
[i
] = env
->dr
[i
];
1393 dbgregs
.dr6
= env
->dr
[6];
1394 dbgregs
.dr7
= env
->dr
[7];
1397 return kvm_vcpu_ioctl(env
, KVM_SET_DEBUGREGS
, &dbgregs
);
1403 static int kvm_get_debugregs(CPUState
*env
)
1405 #ifdef KVM_CAP_DEBUGREGS
1406 struct kvm_debugregs dbgregs
;
1409 if (!kvm_has_debugregs()) {
1413 ret
= kvm_vcpu_ioctl(env
, KVM_GET_DEBUGREGS
, &dbgregs
);
1417 for (i
= 0; i
< 4; i
++) {
1418 env
->dr
[i
] = dbgregs
.db
[i
];
1420 env
->dr
[4] = env
->dr
[6] = dbgregs
.dr6
;
1421 env
->dr
[5] = env
->dr
[7] = dbgregs
.dr7
;
1427 int kvm_arch_put_registers(CPUState
*env
, int level
)
1431 assert(cpu_is_stopped(env
) || qemu_cpu_is_self(env
));
1433 ret
= kvm_getput_regs(env
, 1);
1437 ret
= kvm_put_xsave(env
);
1441 ret
= kvm_put_xcrs(env
);
1445 ret
= kvm_put_sregs(env
);
1449 /* must be before kvm_put_msrs */
1450 ret
= kvm_inject_mce_oldstyle(env
);
1454 ret
= kvm_put_msrs(env
, level
);
1458 if (level
>= KVM_PUT_RESET_STATE
) {
1459 ret
= kvm_put_mp_state(env
);
1464 ret
= kvm_put_vcpu_events(env
, level
);
1468 ret
= kvm_put_debugregs(env
);
1473 ret
= kvm_guest_debug_workarounds(env
);
1480 int kvm_arch_get_registers(CPUState
*env
)
1484 assert(cpu_is_stopped(env
) || qemu_cpu_is_self(env
));
1486 ret
= kvm_getput_regs(env
, 0);
1490 ret
= kvm_get_xsave(env
);
1494 ret
= kvm_get_xcrs(env
);
1498 ret
= kvm_get_sregs(env
);
1502 ret
= kvm_get_msrs(env
);
1506 ret
= kvm_get_mp_state(env
);
1510 ret
= kvm_get_vcpu_events(env
);
1514 ret
= kvm_get_debugregs(env
);
1521 void kvm_arch_pre_run(CPUState
*env
, struct kvm_run
*run
)
1526 if (env
->interrupt_request
& CPU_INTERRUPT_NMI
) {
1527 env
->interrupt_request
&= ~CPU_INTERRUPT_NMI
;
1528 DPRINTF("injected NMI\n");
1529 ret
= kvm_vcpu_ioctl(env
, KVM_NMI
);
1531 fprintf(stderr
, "KVM: injection failed, NMI lost (%s)\n",
1536 if (!kvm_irqchip_in_kernel()) {
1537 /* Force the VCPU out of its inner loop to process the INIT request */
1538 if (env
->interrupt_request
& CPU_INTERRUPT_INIT
) {
1539 env
->exit_request
= 1;
1542 /* Try to inject an interrupt if the guest can accept it */
1543 if (run
->ready_for_interrupt_injection
&&
1544 (env
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
1545 (env
->eflags
& IF_MASK
)) {
1548 env
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
1549 irq
= cpu_get_pic_interrupt(env
);
1551 struct kvm_interrupt intr
;
1554 DPRINTF("injected interrupt %d\n", irq
);
1555 ret
= kvm_vcpu_ioctl(env
, KVM_INTERRUPT
, &intr
);
1558 "KVM: injection failed, interrupt lost (%s)\n",
1564 /* If we have an interrupt but the guest is not ready to receive an
1565 * interrupt, request an interrupt window exit. This will
1566 * cause a return to userspace as soon as the guest is ready to
1567 * receive interrupts. */
1568 if ((env
->interrupt_request
& CPU_INTERRUPT_HARD
)) {
1569 run
->request_interrupt_window
= 1;
1571 run
->request_interrupt_window
= 0;
1574 DPRINTF("setting tpr\n");
1575 run
->cr8
= cpu_get_apic_tpr(env
->apic_state
);
1579 void kvm_arch_post_run(CPUState
*env
, struct kvm_run
*run
)
1582 env
->eflags
|= IF_MASK
;
1584 env
->eflags
&= ~IF_MASK
;
1586 cpu_set_apic_tpr(env
->apic_state
, run
->cr8
);
1587 cpu_set_apic_base(env
->apic_state
, run
->apic_base
);
1590 int kvm_arch_process_async_events(CPUState
*env
)
1592 if (env
->interrupt_request
& CPU_INTERRUPT_MCE
) {
1593 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
1594 assert(env
->mcg_cap
);
1596 env
->interrupt_request
&= ~CPU_INTERRUPT_MCE
;
1598 kvm_cpu_synchronize_state(env
);
1600 if (env
->exception_injected
== EXCP08_DBLE
) {
1601 /* this means triple fault */
1602 qemu_system_reset_request();
1603 env
->exit_request
= 1;
1606 env
->exception_injected
= EXCP12_MCHK
;
1607 env
->has_error_code
= 0;
1610 if (kvm_irqchip_in_kernel() && env
->mp_state
== KVM_MP_STATE_HALTED
) {
1611 env
->mp_state
= KVM_MP_STATE_RUNNABLE
;
1615 if (kvm_irqchip_in_kernel()) {
1619 if (((env
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
1620 (env
->eflags
& IF_MASK
)) ||
1621 (env
->interrupt_request
& CPU_INTERRUPT_NMI
)) {
1624 if (env
->interrupt_request
& CPU_INTERRUPT_INIT
) {
1625 kvm_cpu_synchronize_state(env
);
1628 if (env
->interrupt_request
& CPU_INTERRUPT_SIPI
) {
1629 kvm_cpu_synchronize_state(env
);
1636 static int kvm_handle_halt(CPUState
*env
)
1638 if (!((env
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
1639 (env
->eflags
& IF_MASK
)) &&
1640 !(env
->interrupt_request
& CPU_INTERRUPT_NMI
)) {
1648 #ifdef KVM_CAP_SET_GUEST_DEBUG
1649 int kvm_arch_insert_sw_breakpoint(CPUState
*env
, struct kvm_sw_breakpoint
*bp
)
1651 static const uint8_t int3
= 0xcc;
1653 if (cpu_memory_rw_debug(env
, bp
->pc
, (uint8_t *)&bp
->saved_insn
, 1, 0) ||
1654 cpu_memory_rw_debug(env
, bp
->pc
, (uint8_t *)&int3
, 1, 1)) {
1660 int kvm_arch_remove_sw_breakpoint(CPUState
*env
, struct kvm_sw_breakpoint
*bp
)
1664 if (cpu_memory_rw_debug(env
, bp
->pc
, &int3
, 1, 0) || int3
!= 0xcc ||
1665 cpu_memory_rw_debug(env
, bp
->pc
, (uint8_t *)&bp
->saved_insn
, 1, 1)) {
1677 static int nb_hw_breakpoint
;
1679 static int find_hw_breakpoint(target_ulong addr
, int len
, int type
)
1683 for (n
= 0; n
< nb_hw_breakpoint
; n
++) {
1684 if (hw_breakpoint
[n
].addr
== addr
&& hw_breakpoint
[n
].type
== type
&&
1685 (hw_breakpoint
[n
].len
== len
|| len
== -1)) {
1692 int kvm_arch_insert_hw_breakpoint(target_ulong addr
,
1693 target_ulong len
, int type
)
1696 case GDB_BREAKPOINT_HW
:
1699 case GDB_WATCHPOINT_WRITE
:
1700 case GDB_WATCHPOINT_ACCESS
:
1707 if (addr
& (len
- 1)) {
1719 if (nb_hw_breakpoint
== 4) {
1722 if (find_hw_breakpoint(addr
, len
, type
) >= 0) {
1725 hw_breakpoint
[nb_hw_breakpoint
].addr
= addr
;
1726 hw_breakpoint
[nb_hw_breakpoint
].len
= len
;
1727 hw_breakpoint
[nb_hw_breakpoint
].type
= type
;
1733 int kvm_arch_remove_hw_breakpoint(target_ulong addr
,
1734 target_ulong len
, int type
)
1738 n
= find_hw_breakpoint(addr
, (type
== GDB_BREAKPOINT_HW
) ? 1 : len
, type
);
1743 hw_breakpoint
[n
] = hw_breakpoint
[nb_hw_breakpoint
];
1748 void kvm_arch_remove_all_hw_breakpoints(void)
1750 nb_hw_breakpoint
= 0;
1753 static CPUWatchpoint hw_watchpoint
;
1755 static int kvm_handle_debug(struct kvm_debug_exit_arch
*arch_info
)
1760 if (arch_info
->exception
== 1) {
1761 if (arch_info
->dr6
& (1 << 14)) {
1762 if (cpu_single_env
->singlestep_enabled
) {
1766 for (n
= 0; n
< 4; n
++) {
1767 if (arch_info
->dr6
& (1 << n
)) {
1768 switch ((arch_info
->dr7
>> (16 + n
*4)) & 0x3) {
1774 cpu_single_env
->watchpoint_hit
= &hw_watchpoint
;
1775 hw_watchpoint
.vaddr
= hw_breakpoint
[n
].addr
;
1776 hw_watchpoint
.flags
= BP_MEM_WRITE
;
1780 cpu_single_env
->watchpoint_hit
= &hw_watchpoint
;
1781 hw_watchpoint
.vaddr
= hw_breakpoint
[n
].addr
;
1782 hw_watchpoint
.flags
= BP_MEM_ACCESS
;
1788 } else if (kvm_find_sw_breakpoint(cpu_single_env
, arch_info
->pc
)) {
1792 cpu_synchronize_state(cpu_single_env
);
1793 assert(cpu_single_env
->exception_injected
== -1);
1796 cpu_single_env
->exception_injected
= arch_info
->exception
;
1797 cpu_single_env
->has_error_code
= 0;
1803 void kvm_arch_update_guest_debug(CPUState
*env
, struct kvm_guest_debug
*dbg
)
1805 const uint8_t type_code
[] = {
1806 [GDB_BREAKPOINT_HW
] = 0x0,
1807 [GDB_WATCHPOINT_WRITE
] = 0x1,
1808 [GDB_WATCHPOINT_ACCESS
] = 0x3
1810 const uint8_t len_code
[] = {
1811 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1815 if (kvm_sw_breakpoints_active(env
)) {
1816 dbg
->control
|= KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
;
1818 if (nb_hw_breakpoint
> 0) {
1819 dbg
->control
|= KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_HW_BP
;
1820 dbg
->arch
.debugreg
[7] = 0x0600;
1821 for (n
= 0; n
< nb_hw_breakpoint
; n
++) {
1822 dbg
->arch
.debugreg
[n
] = hw_breakpoint
[n
].addr
;
1823 dbg
->arch
.debugreg
[7] |= (2 << (n
* 2)) |
1824 (type_code
[hw_breakpoint
[n
].type
] << (16 + n
*4)) |
1825 ((uint32_t)len_code
[hw_breakpoint
[n
].len
] << (18 + n
*4));
1829 #endif /* KVM_CAP_SET_GUEST_DEBUG */
1831 static bool host_supports_vmx(void)
1833 uint32_t ecx
, unused
;
1835 host_cpuid(1, 0, &unused
, &unused
, &ecx
, &unused
);
1836 return ecx
& CPUID_EXT_VMX
;
1839 #define VMX_INVALID_GUEST_STATE 0x80000021
1841 int kvm_arch_handle_exit(CPUState
*env
, struct kvm_run
*run
)
1846 switch (run
->exit_reason
) {
1848 DPRINTF("handle_hlt\n");
1849 ret
= kvm_handle_halt(env
);
1851 case KVM_EXIT_SET_TPR
:
1854 case KVM_EXIT_FAIL_ENTRY
:
1855 code
= run
->fail_entry
.hardware_entry_failure_reason
;
1856 fprintf(stderr
, "KVM: entry failed, hardware error 0x%" PRIx64
"\n",
1858 if (host_supports_vmx() && code
== VMX_INVALID_GUEST_STATE
) {
1860 "\nIf you're runnning a guest on an Intel machine without "
1861 "unrestricted mode\n"
1862 "support, the failure can be most likely due to the guest "
1863 "entering an invalid\n"
1864 "state for Intel VT. For example, the guest maybe running "
1865 "in big real mode\n"
1866 "which is not supported on less recent Intel processors."
1871 case KVM_EXIT_EXCEPTION
:
1872 fprintf(stderr
, "KVM: exception %d exit (error code 0x%x)\n",
1873 run
->ex
.exception
, run
->ex
.error_code
);
1876 #ifdef KVM_CAP_SET_GUEST_DEBUG
1877 case KVM_EXIT_DEBUG
:
1878 DPRINTF("kvm_exit_debug\n");
1879 ret
= kvm_handle_debug(&run
->debug
.arch
);
1881 #endif /* KVM_CAP_SET_GUEST_DEBUG */
1883 fprintf(stderr
, "KVM: unknown exit reason %d\n", run
->exit_reason
);
1891 bool kvm_arch_stop_on_emulation_error(CPUState
*env
)
1893 return !(env
->cr
[0] & CR0_PE_MASK
) ||
1894 ((env
->segs
[R_CS
].selector
& 3) != 3);