?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
target/ppc: moved ppc_cpu_dump_state to cpu_init.c
[qemu.git] / target / ppc / translate.c
blob6c68d7006a26b948131d1994e97bf76a18a69b8e
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "internal.h"
24 #include "disas/disas.h"
25 #include "exec/exec-all.h"
26 #include "tcg/tcg-op.h"
27 #include "tcg/tcg-op-gvec.h"
28 #include "qemu/host-utils.h"
29 #include "qemu/main-loop.h"
30 #include "exec/cpu_ldst.h"
31
32 #include "exec/helper-proto.h"
33 #include "exec/helper-gen.h"
34
35 #include "trace-tcg.h"
36 #include "exec/translator.h"
37 #include "exec/log.h"
38 #include "qemu/atomic128.h"
39 #include "spr_tcg.h"
40
41 #include "qemu/qemu-print.h"
42 #include "qapi/error.h"
43
44 #define CPU_SINGLE_STEP 0x1
45 #define CPU_BRANCH_STEP 0x2
46 #define GDBSTUB_SINGLE_STEP 0x4
47
48 /* Include definitions for instructions classes and implementations flags */
49 /* #define PPC_DEBUG_DISAS */
50 /* #define DO_PPC_STATISTICS */
51
52 #ifdef PPC_DEBUG_DISAS
53 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
54 #else
55 # define LOG_DISAS(...) do { } while (0)
56 #endif
57 /*****************************************************************************/
58 /* Code translation helpers */
59
60 /* global register indexes */
61 static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */
62 + 10 * 4 + 22 * 5 /* SPE GPRh */
63 + 8 * 5 /* CRF */];
64 static TCGv cpu_gpr[32];
65 static TCGv cpu_gprh[32];
66 static TCGv_i32 cpu_crf[8];
67 static TCGv cpu_nip;
68 static TCGv cpu_msr;
69 static TCGv cpu_ctr;
70 static TCGv cpu_lr;
71 #if defined(TARGET_PPC64)
72 static TCGv cpu_cfar;
73 #endif
74 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32;
75 static TCGv cpu_reserve;
76 static TCGv cpu_reserve_val;
77 static TCGv cpu_fpscr;
78 static TCGv_i32 cpu_access_type;
79
80 #include "exec/gen-icount.h"
81
82 void ppc_translate_init(void)
83 {
84 int i;
85 char *p;
86 size_t cpu_reg_names_size;
87
88 p = cpu_reg_names;
89 cpu_reg_names_size = sizeof(cpu_reg_names);
90
91 for (i = 0; i < 8; i++) {
92 snprintf(p, cpu_reg_names_size, "crf%d", i);
93 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env,
94 offsetof(CPUPPCState, crf[i]), p);
95 p += 5;
96 cpu_reg_names_size -= 5;
97 }
98
99 for (i = 0; i < 32; i++) {
100 snprintf(p, cpu_reg_names_size, "r%d", i);
101 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
102 offsetof(CPUPPCState, gpr[i]), p);
103 p += (i < 10) ? 3 : 4;
104 cpu_reg_names_size -= (i < 10) ? 3 : 4;
105 snprintf(p, cpu_reg_names_size, "r%dH", i);
106 cpu_gprh[i] = tcg_global_mem_new(cpu_env,
107 offsetof(CPUPPCState, gprh[i]), p);
108 p += (i < 10) ? 4 : 5;
109 cpu_reg_names_size -= (i < 10) ? 4 : 5;
110 }
111
112 cpu_nip = tcg_global_mem_new(cpu_env,
113 offsetof(CPUPPCState, nip), "nip");
114
115 cpu_msr = tcg_global_mem_new(cpu_env,
116 offsetof(CPUPPCState, msr), "msr");
117
118 cpu_ctr = tcg_global_mem_new(cpu_env,
119 offsetof(CPUPPCState, ctr), "ctr");
120
121 cpu_lr = tcg_global_mem_new(cpu_env,
122 offsetof(CPUPPCState, lr), "lr");
123
124 #if defined(TARGET_PPC64)
125 cpu_cfar = tcg_global_mem_new(cpu_env,
126 offsetof(CPUPPCState, cfar), "cfar");
127 #endif
128
129 cpu_xer = tcg_global_mem_new(cpu_env,
130 offsetof(CPUPPCState, xer), "xer");
131 cpu_so = tcg_global_mem_new(cpu_env,
132 offsetof(CPUPPCState, so), "SO");
133 cpu_ov = tcg_global_mem_new(cpu_env,
134 offsetof(CPUPPCState, ov), "OV");
135 cpu_ca = tcg_global_mem_new(cpu_env,
136 offsetof(CPUPPCState, ca), "CA");
137 cpu_ov32 = tcg_global_mem_new(cpu_env,
138 offsetof(CPUPPCState, ov32), "OV32");
139 cpu_ca32 = tcg_global_mem_new(cpu_env,
140 offsetof(CPUPPCState, ca32), "CA32");
141
142 cpu_reserve = tcg_global_mem_new(cpu_env,
143 offsetof(CPUPPCState, reserve_addr),
144 "reserve_addr");
145 cpu_reserve_val = tcg_global_mem_new(cpu_env,
146 offsetof(CPUPPCState, reserve_val),
147 "reserve_val");
148
149 cpu_fpscr = tcg_global_mem_new(cpu_env,
150 offsetof(CPUPPCState, fpscr), "fpscr");
151
152 cpu_access_type = tcg_global_mem_new_i32(cpu_env,
153 offsetof(CPUPPCState, access_type),
154 "access_type");
155 }
156
157 /* internal defines */
158 struct DisasContext {
159 DisasContextBase base;
160 uint32_t opcode;
161 uint32_t exception;
162 /* Routine used to access memory */
163 bool pr, hv, dr, le_mode;
164 bool lazy_tlb_flush;
165 bool need_access_type;
166 int mem_idx;
167 int access_type;
168 /* Translation flags */
169 MemOp default_tcg_memop_mask;
170 #if defined(TARGET_PPC64)
171 bool sf_mode;
172 bool has_cfar;
173 #endif
174 bool fpu_enabled;
175 bool altivec_enabled;
176 bool vsx_enabled;
177 bool spe_enabled;
178 bool tm_enabled;
179 bool gtse;
180 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
181 int singlestep_enabled;
182 uint32_t flags;
183 uint64_t insns_flags;
184 uint64_t insns_flags2;
185 };
186
187 /* Return true iff byteswap is needed in a scalar memop */
188 static inline bool need_byteswap(const DisasContext *ctx)
189 {
190 #if defined(TARGET_WORDS_BIGENDIAN)
191 return ctx->le_mode;
192 #else
193 return !ctx->le_mode;
194 #endif
195 }
196
197 /* True when active word size < size of target_long. */
198 #ifdef TARGET_PPC64
199 # define NARROW_MODE(C) (!(C)->sf_mode)
200 #else
201 # define NARROW_MODE(C) 0
202 #endif
203
204 struct opc_handler_t {
205 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
206 uint32_t inval1;
207 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
208 uint32_t inval2;
209 /* instruction type */
210 uint64_t type;
211 /* extended instruction type */
212 uint64_t type2;
213 /* handler */
214 void (*handler)(DisasContext *ctx);
215 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
216 const char *oname;
217 #endif
218 #if defined(DO_PPC_STATISTICS)
219 uint64_t count;
220 #endif
221 };
222
223 /* SPR load/store helpers */
224 static inline void gen_load_spr(TCGv t, int reg)
225 {
226 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
227 }
228
229 static inline void gen_store_spr(int reg, TCGv t)
230 {
231 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
232 }
233
234 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
235 {
236 if (ctx->need_access_type && ctx->access_type != access_type) {
237 tcg_gen_movi_i32(cpu_access_type, access_type);
238 ctx->access_type = access_type;
239 }
240 }
241
242 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
243 {
244 if (NARROW_MODE(ctx)) {
245 nip = (uint32_t)nip;
246 }
247 tcg_gen_movi_tl(cpu_nip, nip);
248 }
249
250 static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
251 {
252 TCGv_i32 t0, t1;
253
254 /*
255 * These are all synchronous exceptions, we set the PC back to the
256 * faulting instruction
257 */
258 if (ctx->exception == POWERPC_EXCP_NONE) {
259 gen_update_nip(ctx, ctx->base.pc_next - 4);
260 }
261 t0 = tcg_const_i32(excp);
262 t1 = tcg_const_i32(error);
263 gen_helper_raise_exception_err(cpu_env, t0, t1);
264 tcg_temp_free_i32(t0);
265 tcg_temp_free_i32(t1);
266 ctx->exception = (excp);
267 }
268
269 static void gen_exception(DisasContext *ctx, uint32_t excp)
270 {
271 TCGv_i32 t0;
272
273 /*
274 * These are all synchronous exceptions, we set the PC back to the
275 * faulting instruction
276 */
277 if (ctx->exception == POWERPC_EXCP_NONE) {
278 gen_update_nip(ctx, ctx->base.pc_next - 4);
279 }
280 t0 = tcg_const_i32(excp);
281 gen_helper_raise_exception(cpu_env, t0);
282 tcg_temp_free_i32(t0);
283 ctx->exception = (excp);
284 }
285
286 static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
287 target_ulong nip)
288 {
289 TCGv_i32 t0;
290
291 gen_update_nip(ctx, nip);
292 t0 = tcg_const_i32(excp);
293 gen_helper_raise_exception(cpu_env, t0);
294 tcg_temp_free_i32(t0);
295 ctx->exception = (excp);
296 }
297
298 /*
299 * Tells the caller what is the appropriate exception to generate and prepares
300 * SPR registers for this exception.
301 *
302 * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or
303 * POWERPC_EXCP_DEBUG (on BookE).
304 */
305 static uint32_t gen_prep_dbgex(DisasContext *ctx)
306 {
307 if (ctx->flags & POWERPC_FLAG_DE) {
308 target_ulong dbsr = 0;
309 if (ctx->singlestep_enabled & CPU_SINGLE_STEP) {
310 dbsr = DBCR0_ICMP;
311 } else {
312 /* Must have been branch */
313 dbsr = DBCR0_BRT;
314 }
315 TCGv t0 = tcg_temp_new();
316 gen_load_spr(t0, SPR_BOOKE_DBSR);
317 tcg_gen_ori_tl(t0, t0, dbsr);
318 gen_store_spr(SPR_BOOKE_DBSR, t0);
319 tcg_temp_free(t0);
320 return POWERPC_EXCP_DEBUG;
321 } else {
322 return POWERPC_EXCP_TRACE;
323 }
324 }
325
326 static void gen_debug_exception(DisasContext *ctx)
327 {
328 TCGv_i32 t0;
329
330 /*
331 * These are all synchronous exceptions, we set the PC back to the
332 * faulting instruction
333 */
334 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
335 (ctx->exception != POWERPC_EXCP_SYNC)) {
336 gen_update_nip(ctx, ctx->base.pc_next);
337 }
338 t0 = tcg_const_i32(EXCP_DEBUG);
339 gen_helper_raise_exception(cpu_env, t0);
340 tcg_temp_free_i32(t0);
341 }
342
343 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
344 {
345 /* Will be converted to program check if needed */
346 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error);
347 }
348
349 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error)
350 {
351 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error);
352 }
353
354 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error)
355 {
356 /* Will be converted to program check if needed */
357 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error);
358 }
359
360 /* Stop translation */
361 static inline void gen_stop_exception(DisasContext *ctx)
362 {
363 gen_update_nip(ctx, ctx->base.pc_next);
364 ctx->exception = POWERPC_EXCP_STOP;
365 }
366
367 #ifndef CONFIG_USER_ONLY
368 /* No need to update nip here, as execution flow will change */
369 static inline void gen_sync_exception(DisasContext *ctx)
370 {
371 ctx->exception = POWERPC_EXCP_SYNC;
372 }
373 #endif
374
375 /*****************************************************************************/
376 /* SPR READ/WRITE CALLBACKS */
377
378 void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
379 {
380 #if 0
381 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
382 printf("ERROR: try to access SPR %d !\n", sprn);
383 #endif
384 }
385
386 /* #define PPC_DUMP_SPR_ACCESSES */
387
388 /*
389 * Generic callbacks:
390 * do nothing but store/retrieve spr value
391 */
392 static void spr_load_dump_spr(int sprn)
393 {
394 #ifdef PPC_DUMP_SPR_ACCESSES
395 TCGv_i32 t0 = tcg_const_i32(sprn);
396 gen_helper_load_dump_spr(cpu_env, t0);
397 tcg_temp_free_i32(t0);
398 #endif
399 }
400
401 void spr_read_generic(DisasContext *ctx, int gprn, int sprn)
402 {
403 gen_load_spr(cpu_gpr[gprn], sprn);
404 spr_load_dump_spr(sprn);
405 }
406
407 static void spr_store_dump_spr(int sprn)
408 {
409 #ifdef PPC_DUMP_SPR_ACCESSES
410 TCGv_i32 t0 = tcg_const_i32(sprn);
411 gen_helper_store_dump_spr(cpu_env, t0);
412 tcg_temp_free_i32(t0);
413 #endif
414 }
415
416 void spr_write_generic(DisasContext *ctx, int sprn, int gprn)
417 {
418 gen_store_spr(sprn, cpu_gpr[gprn]);
419 spr_store_dump_spr(sprn);
420 }
421
422 #if !defined(CONFIG_USER_ONLY)
423 void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
424 {
425 #ifdef TARGET_PPC64
426 TCGv t0 = tcg_temp_new();
427 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
428 gen_store_spr(sprn, t0);
429 tcg_temp_free(t0);
430 spr_store_dump_spr(sprn);
431 #else
432 spr_write_generic(ctx, sprn, gprn);
433 #endif
434 }
435
436 void spr_write_clear(DisasContext *ctx, int sprn, int gprn)
437 {
438 TCGv t0 = tcg_temp_new();
439 TCGv t1 = tcg_temp_new();
440 gen_load_spr(t0, sprn);
441 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
442 tcg_gen_and_tl(t0, t0, t1);
443 gen_store_spr(sprn, t0);
444 tcg_temp_free(t0);
445 tcg_temp_free(t1);
446 }
447
448 void spr_access_nop(DisasContext *ctx, int sprn, int gprn)
449 {
450 }
451
452 #endif
453
454 /* SPR common to all PowerPC */
455 /* XER */
456 void spr_read_xer(DisasContext *ctx, int gprn, int sprn)
457 {
458 TCGv dst = cpu_gpr[gprn];
459 TCGv t0 = tcg_temp_new();
460 TCGv t1 = tcg_temp_new();
461 TCGv t2 = tcg_temp_new();
462 tcg_gen_mov_tl(dst, cpu_xer);
463 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
464 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
465 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
466 tcg_gen_or_tl(t0, t0, t1);
467 tcg_gen_or_tl(dst, dst, t2);
468 tcg_gen_or_tl(dst, dst, t0);
469 if (is_isa300(ctx)) {
470 tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32);
471 tcg_gen_or_tl(dst, dst, t0);
472 tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32);
473 tcg_gen_or_tl(dst, dst, t0);
474 }
475 tcg_temp_free(t0);
476 tcg_temp_free(t1);
477 tcg_temp_free(t2);
478 }
479
480 void spr_write_xer(DisasContext *ctx, int sprn, int gprn)
481 {
482 TCGv src = cpu_gpr[gprn];
483 /* Write all flags, while reading back check for isa300 */
484 tcg_gen_andi_tl(cpu_xer, src,
485 ~((1u << XER_SO) |
486 (1u << XER_OV) | (1u << XER_OV32) |
487 (1u << XER_CA) | (1u << XER_CA32)));
488 tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1);
489 tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1);
490 tcg_gen_extract_tl(cpu_so, src, XER_SO, 1);
491 tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1);
492 tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1);
493 }
494
495 /* LR */
496 void spr_read_lr(DisasContext *ctx, int gprn, int sprn)
497 {
498 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
499 }
500
501 void spr_write_lr(DisasContext *ctx, int sprn, int gprn)
502 {
503 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
504 }
505
506 /* CFAR */
507 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
508 void spr_read_cfar(DisasContext *ctx, int gprn, int sprn)
509 {
510 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
511 }
512
513 void spr_write_cfar(DisasContext *ctx, int sprn, int gprn)
514 {
515 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
516 }
517 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
518
519 /* CTR */
520 void spr_read_ctr(DisasContext *ctx, int gprn, int sprn)
521 {
522 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
523 }
524
525 void spr_write_ctr(DisasContext *ctx, int sprn, int gprn)
526 {
527 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
528 }
529
530 /* User read access to SPR */
531 /* USPRx */
532 /* UMMCRx */
533 /* UPMCx */
534 /* USIA */
535 /* UDECR */
536 void spr_read_ureg(DisasContext *ctx, int gprn, int sprn)
537 {
538 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
539 }
540
541 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
542 void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
543 {
544 gen_store_spr(sprn + 0x10, cpu_gpr[gprn]);
545 }
546 #endif
547
548 /* SPR common to all non-embedded PowerPC */
549 /* DECR */
550 #if !defined(CONFIG_USER_ONLY)
551 void spr_read_decr(DisasContext *ctx, int gprn, int sprn)
552 {
553 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
554 gen_io_start();
555 }
556 gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
557 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
558 gen_stop_exception(ctx);
559 }
560 }
561
562 void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
563 {
564 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
565 gen_io_start();
566 }
567 gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
568 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
569 gen_stop_exception(ctx);
570 }
571 }
572 #endif
573
574 /* SPR common to all non-embedded PowerPC, except 601 */
575 /* Time base */
576 void spr_read_tbl(DisasContext *ctx, int gprn, int sprn)
577 {
578 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
579 gen_io_start();
580 }
581 gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
582 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
583 gen_io_end();
584 gen_stop_exception(ctx);
585 }
586 }
587
588 void spr_read_tbu(DisasContext *ctx, int gprn, int sprn)
589 {
590 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
591 gen_io_start();
592 }
593 gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
594 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
595 gen_io_end();
596 gen_stop_exception(ctx);
597 }
598 }
599
600 void spr_read_atbl(DisasContext *ctx, int gprn, int sprn)
601 {
602 gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
603 }
604
605 void spr_read_atbu(DisasContext *ctx, int gprn, int sprn)
606 {
607 gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
608 }
609
610 #if !defined(CONFIG_USER_ONLY)
611 void spr_write_tbl(DisasContext *ctx, int sprn, int gprn)
612 {
613 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
614 gen_io_start();
615 }
616 gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
617 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
618 gen_io_end();
619 gen_stop_exception(ctx);
620 }
621 }
622
623 void spr_write_tbu(DisasContext *ctx, int sprn, int gprn)
624 {
625 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
626 gen_io_start();
627 }
628 gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
629 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
630 gen_io_end();
631 gen_stop_exception(ctx);
632 }
633 }
634
635 void spr_write_atbl(DisasContext *ctx, int sprn, int gprn)
636 {
637 gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
638 }
639
640 void spr_write_atbu(DisasContext *ctx, int sprn, int gprn)
641 {
642 gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
643 }
644
645 #if defined(TARGET_PPC64)
646 void spr_read_purr(DisasContext *ctx, int gprn, int sprn)
647 {
648 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
649 gen_io_start();
650 }
651 gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
652 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
653 gen_stop_exception(ctx);
654 }
655 }
656
657 void spr_write_purr(DisasContext *ctx, int sprn, int gprn)
658 {
659 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
660 gen_io_start();
661 }
662 gen_helper_store_purr(cpu_env, cpu_gpr[gprn]);
663 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
664 gen_stop_exception(ctx);
665 }
666 }
667
668 /* HDECR */
669 void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
670 {
671 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
672 gen_io_start();
673 }
674 gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env);
675 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
676 gen_io_end();
677 gen_stop_exception(ctx);
678 }
679 }
680
681 void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
682 {
683 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
684 gen_io_start();
685 }
686 gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]);
687 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
688 gen_io_end();
689 gen_stop_exception(ctx);
690 }
691 }
692
693 void spr_read_vtb(DisasContext *ctx, int gprn, int sprn)
694 {
695 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
696 gen_io_start();
697 }
698 gen_helper_load_vtb(cpu_gpr[gprn], cpu_env);
699 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
700 gen_stop_exception(ctx);
701 }
702 }
703
704 void spr_write_vtb(DisasContext *ctx, int sprn, int gprn)
705 {
706 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
707 gen_io_start();
708 }
709 gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]);
710 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
711 gen_stop_exception(ctx);
712 }
713 }
714
715 void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn)
716 {
717 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
718 gen_io_start();
719 }
720 gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]);
721 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
722 gen_stop_exception(ctx);
723 }
724 }
725
726 #endif
727 #endif
728
729 #if !defined(CONFIG_USER_ONLY)
730 /* IBAT0U...IBAT0U */
731 /* IBAT0L...IBAT7L */
732 void spr_read_ibat(DisasContext *ctx, int gprn, int sprn)
733 {
734 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
735 offsetof(CPUPPCState,
736 IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
737 }
738
739 void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn)
740 {
741 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
742 offsetof(CPUPPCState,
743 IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4]));
744 }
745
746 void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn)
747 {
748 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
749 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
750 tcg_temp_free_i32(t0);
751 }
752
753 void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn)
754 {
755 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
756 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
757 tcg_temp_free_i32(t0);
758 }
759
760 void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn)
761 {
762 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
763 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
764 tcg_temp_free_i32(t0);
765 }
766
767 void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn)
768 {
769 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
770 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
771 tcg_temp_free_i32(t0);
772 }
773
774 /* DBAT0U...DBAT7U */
775 /* DBAT0L...DBAT7L */
776 void spr_read_dbat(DisasContext *ctx, int gprn, int sprn)
777 {
778 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
779 offsetof(CPUPPCState,
780 DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
781 }
782
783 void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn)
784 {
785 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
786 offsetof(CPUPPCState,
787 DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
788 }
789
790 void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn)
791 {
792 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
793 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
794 tcg_temp_free_i32(t0);
795 }
796
797 void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn)
798 {
799 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
800 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
801 tcg_temp_free_i32(t0);
802 }
803
804 void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn)
805 {
806 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
807 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
808 tcg_temp_free_i32(t0);
809 }
810
811 void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn)
812 {
813 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
814 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
815 tcg_temp_free_i32(t0);
816 }
817
818 /* SDR1 */
819 void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn)
820 {
821 gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
822 }
823
824 #if defined(TARGET_PPC64)
825 /* 64 bits PowerPC specific SPRs */
826 /* PIDR */
827 void spr_write_pidr(DisasContext *ctx, int sprn, int gprn)
828 {
829 gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]);
830 }
831
832 void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn)
833 {
834 gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]);
835 }
836
837 void spr_read_hior(DisasContext *ctx, int gprn, int sprn)
838 {
839 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
840 }
841
842 void spr_write_hior(DisasContext *ctx, int sprn, int gprn)
843 {
844 TCGv t0 = tcg_temp_new();
845 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
846 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
847 tcg_temp_free(t0);
848 }
849 void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn)
850 {
851 gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]);
852 }
853
854 void spr_write_pcr(DisasContext *ctx, int sprn, int gprn)
855 {
856 gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]);
857 }
858
859 /* DPDES */
860 void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn)
861 {
862 gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env);
863 }
864
865 void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn)
866 {
867 gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]);
868 }
869 #endif
870 #endif
871
872 /* PowerPC 601 specific registers */
873 /* RTC */
874 void spr_read_601_rtcl(DisasContext *ctx, int gprn, int sprn)
875 {
876 gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
877 }
878
879 void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn)
880 {
881 gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
882 }
883
884 #if !defined(CONFIG_USER_ONLY)
885 void spr_write_601_rtcu(DisasContext *ctx, int sprn, int gprn)
886 {
887 gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
888 }
889
890 void spr_write_601_rtcl(DisasContext *ctx, int sprn, int gprn)
891 {
892 gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
893 }
894
895 void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn)
896 {
897 gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
898 /* Must stop the translation as endianness may have changed */
899 gen_stop_exception(ctx);
900 }
901 #endif
902
903 /* Unified bats */
904 #if !defined(CONFIG_USER_ONLY)
905 void spr_read_601_ubat(DisasContext *ctx, int gprn, int sprn)
906 {
907 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
908 offsetof(CPUPPCState,
909 IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
910 }
911
912 void spr_write_601_ubatu(DisasContext *ctx, int sprn, int gprn)
913 {
914 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
915 gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
916 tcg_temp_free_i32(t0);
917 }
918
919 void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn)
920 {
921 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
922 gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
923 tcg_temp_free_i32(t0);
924 }
925 #endif
926
927 /* PowerPC 40x specific registers */
928 #if !defined(CONFIG_USER_ONLY)
929 void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn)
930 {
931 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
932 gen_io_start();
933 }
934 gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
935 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
936 gen_stop_exception(ctx);
937 }
938 }
939
940 void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn)
941 {
942 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
943 gen_io_start();
944 }
945 gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
946 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
947 gen_stop_exception(ctx);
948 }
949 }
950
951 void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
952 {
953 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
954 gen_io_start();
955 }
956 gen_store_spr(sprn, cpu_gpr[gprn]);
957 gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
958 /* We must stop translation as we may have rebooted */
959 gen_stop_exception(ctx);
960 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
961 gen_stop_exception(ctx);
962 }
963 }
964
965 void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn)
966 {
967 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
968 gen_io_start();
969 }
970 gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
971 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
972 gen_stop_exception(ctx);
973 }
974 }
975
976 void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn)
977 {
978 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
979 gen_io_start();
980 }
981 gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
982 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
983 gen_stop_exception(ctx);
984 }
985 }
986
987 void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn)
988 {
989 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
990 gen_io_start();
991 }
992 gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
993 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
994 gen_stop_exception(ctx);
995 }
996 }
997 #endif
998
999 /* PowerPC 403 specific registers */
1000 /* PBL1 / PBU1 / PBL2 / PBU2 */
1001 #if !defined(CONFIG_USER_ONLY)
1002 void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn)
1003 {
1004 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
1005 offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
1006 }
1007
1008 void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn)
1009 {
1010 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
1011 gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
1012 tcg_temp_free_i32(t0);
1013 }
1014
1015 void spr_write_pir(DisasContext *ctx, int sprn, int gprn)
1016 {
1017 TCGv t0 = tcg_temp_new();
1018 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
1019 gen_store_spr(SPR_PIR, t0);
1020 tcg_temp_free(t0);
1021 }
1022 #endif
1023
1024 /* SPE specific registers */
1025 void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn)
1026 {
1027 TCGv_i32 t0 = tcg_temp_new_i32();
1028 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
1029 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
1030 tcg_temp_free_i32(t0);
1031 }
1032
1033 void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn)
1034 {
1035 TCGv_i32 t0 = tcg_temp_new_i32();
1036 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
1037 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
1038 tcg_temp_free_i32(t0);
1039 }
1040
1041 #if !defined(CONFIG_USER_ONLY)
1042 /* Callback used to write the exception vector base */
1043 void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn)
1044 {
1045 TCGv t0 = tcg_temp_new();
1046 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
1047 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
1048 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
1049 gen_store_spr(sprn, t0);
1050 tcg_temp_free(t0);
1051 }
1052
1053 void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn)
1054 {
1055 int sprn_offs;
1056
1057 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
1058 sprn_offs = sprn - SPR_BOOKE_IVOR0;
1059 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
1060 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
1061 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
1062 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
1063 } else {
1064 printf("Trying to write an unknown exception vector %d %03x\n",
1065 sprn, sprn);
1066 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
1067 return;
1068 }
1069
1070 TCGv t0 = tcg_temp_new();
1071 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
1072 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
1073 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
1074 gen_store_spr(sprn, t0);
1075 tcg_temp_free(t0);
1076 }
1077 #endif
1078
1079 #ifdef TARGET_PPC64
1080 #ifndef CONFIG_USER_ONLY
1081 void spr_write_amr(DisasContext *ctx, int sprn, int gprn)
1082 {
1083 TCGv t0 = tcg_temp_new();
1084 TCGv t1 = tcg_temp_new();
1085 TCGv t2 = tcg_temp_new();
1086
1087 /*
1088 * Note, the HV=1 PR=0 case is handled earlier by simply using
1089 * spr_write_generic for HV mode in the SPR table
1090 */
1091
1092 /* Build insertion mask into t1 based on context */
1093 if (ctx->pr) {
1094 gen_load_spr(t1, SPR_UAMOR);
1095 } else {
1096 gen_load_spr(t1, SPR_AMOR);
1097 }
1098
1099 /* Mask new bits into t2 */
1100 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1101
1102 /* Load AMR and clear new bits in t0 */
1103 gen_load_spr(t0, SPR_AMR);
1104 tcg_gen_andc_tl(t0, t0, t1);
1105
1106 /* Or'in new bits and write it out */
1107 tcg_gen_or_tl(t0, t0, t2);
1108 gen_store_spr(SPR_AMR, t0);
1109 spr_store_dump_spr(SPR_AMR);
1110
1111 tcg_temp_free(t0);
1112 tcg_temp_free(t1);
1113 tcg_temp_free(t2);
1114 }
1115
1116 void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
1117 {
1118 TCGv t0 = tcg_temp_new();
1119 TCGv t1 = tcg_temp_new();
1120 TCGv t2 = tcg_temp_new();
1121
1122 /*
1123 * Note, the HV=1 case is handled earlier by simply using
1124 * spr_write_generic for HV mode in the SPR table
1125 */
1126
1127 /* Build insertion mask into t1 based on context */
1128 gen_load_spr(t1, SPR_AMOR);
1129
1130 /* Mask new bits into t2 */
1131 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1132
1133 /* Load AMR and clear new bits in t0 */
1134 gen_load_spr(t0, SPR_UAMOR);
1135 tcg_gen_andc_tl(t0, t0, t1);
1136
1137 /* Or'in new bits and write it out */
1138 tcg_gen_or_tl(t0, t0, t2);
1139 gen_store_spr(SPR_UAMOR, t0);
1140 spr_store_dump_spr(SPR_UAMOR);
1141
1142 tcg_temp_free(t0);
1143 tcg_temp_free(t1);
1144 tcg_temp_free(t2);
1145 }
1146
1147 void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
1148 {
1149 TCGv t0 = tcg_temp_new();
1150 TCGv t1 = tcg_temp_new();
1151 TCGv t2 = tcg_temp_new();
1152
1153 /*
1154 * Note, the HV=1 case is handled earlier by simply using
1155 * spr_write_generic for HV mode in the SPR table
1156 */
1157
1158 /* Build insertion mask into t1 based on context */
1159 gen_load_spr(t1, SPR_AMOR);
1160
1161 /* Mask new bits into t2 */
1162 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1163
1164 /* Load AMR and clear new bits in t0 */
1165 gen_load_spr(t0, SPR_IAMR);
1166 tcg_gen_andc_tl(t0, t0, t1);
1167
1168 /* Or'in new bits and write it out */
1169 tcg_gen_or_tl(t0, t0, t2);
1170 gen_store_spr(SPR_IAMR, t0);
1171 spr_store_dump_spr(SPR_IAMR);
1172
1173 tcg_temp_free(t0);
1174 tcg_temp_free(t1);
1175 tcg_temp_free(t2);
1176 }
1177 #endif
1178 #endif
1179
1180 #ifndef CONFIG_USER_ONLY
1181 void spr_read_thrm(DisasContext *ctx, int gprn, int sprn)
1182 {
1183 gen_helper_fixup_thrm(cpu_env);
1184 gen_load_spr(cpu_gpr[gprn], sprn);
1185 spr_load_dump_spr(sprn);
1186 }
1187 #endif /* !CONFIG_USER_ONLY */
1188
1189 #if !defined(CONFIG_USER_ONLY)
1190 void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn)
1191 {
1192 TCGv t0 = tcg_temp_new();
1193
1194 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE);
1195 gen_store_spr(sprn, t0);
1196 tcg_temp_free(t0);
1197 }
1198
1199 void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn)
1200 {
1201 TCGv t0 = tcg_temp_new();
1202
1203 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE);
1204 gen_store_spr(sprn, t0);
1205 tcg_temp_free(t0);
1206 }
1207
1208 void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn)
1209 {
1210 TCGv t0 = tcg_temp_new();
1211
1212 tcg_gen_andi_tl(t0, cpu_gpr[gprn],
1213 ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC));
1214 gen_store_spr(sprn, t0);
1215 tcg_temp_free(t0);
1216 }
1217
1218 void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn)
1219 {
1220 gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]);
1221 }
1222
1223 void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn)
1224 {
1225 TCGv_i32 t0 = tcg_const_i32(sprn);
1226 gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
1227 tcg_temp_free_i32(t0);
1228 }
1229 void spr_write_eplc(DisasContext *ctx, int sprn, int gprn)
1230 {
1231 gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]);
1232 }
1233 void spr_write_epsc(DisasContext *ctx, int sprn, int gprn)
1234 {
1235 gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]);
1236 }
1237
1238 #endif
1239
1240 #if !defined(CONFIG_USER_ONLY)
1241 void spr_write_mas73(DisasContext *ctx, int sprn, int gprn)
1242 {
1243 TCGv val = tcg_temp_new();
1244 tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
1245 gen_store_spr(SPR_BOOKE_MAS3, val);
1246 tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
1247 gen_store_spr(SPR_BOOKE_MAS7, val);
1248 tcg_temp_free(val);
1249 }
1250
1251 void spr_read_mas73(DisasContext *ctx, int gprn, int sprn)
1252 {
1253 TCGv mas7 = tcg_temp_new();
1254 TCGv mas3 = tcg_temp_new();
1255 gen_load_spr(mas7, SPR_BOOKE_MAS7);
1256 tcg_gen_shli_tl(mas7, mas7, 32);
1257 gen_load_spr(mas3, SPR_BOOKE_MAS3);
1258 tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
1259 tcg_temp_free(mas3);
1260 tcg_temp_free(mas7);
1261 }
1262
1263 #endif
1264
1265 #ifdef TARGET_PPC64
1266 static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn,
1267 int bit, int sprn, int cause)
1268 {
1269 TCGv_i32 t1 = tcg_const_i32(bit);
1270 TCGv_i32 t2 = tcg_const_i32(sprn);
1271 TCGv_i32 t3 = tcg_const_i32(cause);
1272
1273 gen_helper_fscr_facility_check(cpu_env, t1, t2, t3);
1274
1275 tcg_temp_free_i32(t3);
1276 tcg_temp_free_i32(t2);
1277 tcg_temp_free_i32(t1);
1278 }
1279
1280 static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn,
1281 int bit, int sprn, int cause)
1282 {
1283 TCGv_i32 t1 = tcg_const_i32(bit);
1284 TCGv_i32 t2 = tcg_const_i32(sprn);
1285 TCGv_i32 t3 = tcg_const_i32(cause);
1286
1287 gen_helper_msr_facility_check(cpu_env, t1, t2, t3);
1288
1289 tcg_temp_free_i32(t3);
1290 tcg_temp_free_i32(t2);
1291 tcg_temp_free_i32(t1);
1292 }
1293
1294 void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn)
1295 {
1296 TCGv spr_up = tcg_temp_new();
1297 TCGv spr = tcg_temp_new();
1298
1299 gen_load_spr(spr, sprn - 1);
1300 tcg_gen_shri_tl(spr_up, spr, 32);
1301 tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up);
1302
1303 tcg_temp_free(spr);
1304 tcg_temp_free(spr_up);
1305 }
1306
1307 void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn)
1308 {
1309 TCGv spr = tcg_temp_new();
1310
1311 gen_load_spr(spr, sprn - 1);
1312 tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32);
1313 gen_store_spr(sprn - 1, spr);
1314
1315 tcg_temp_free(spr);
1316 }
1317
1318 #if !defined(CONFIG_USER_ONLY)
1319 void spr_write_hmer(DisasContext *ctx, int sprn, int gprn)
1320 {
1321 TCGv hmer = tcg_temp_new();
1322
1323 gen_load_spr(hmer, sprn);
1324 tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer);
1325 gen_store_spr(sprn, hmer);
1326 spr_store_dump_spr(sprn);
1327 tcg_temp_free(hmer);
1328 }
1329
1330 void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn)
1331 {
1332 gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]);
1333 }
1334 #endif /* !defined(CONFIG_USER_ONLY) */
1335
1336 void spr_read_tar(DisasContext *ctx, int gprn, int sprn)
1337 {
1338 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
1339 spr_read_generic(ctx, gprn, sprn);
1340 }
1341
1342 void spr_write_tar(DisasContext *ctx, int sprn, int gprn)
1343 {
1344 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
1345 spr_write_generic(ctx, sprn, gprn);
1346 }
1347
1348 void spr_read_tm(DisasContext *ctx, int gprn, int sprn)
1349 {
1350 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
1351 spr_read_generic(ctx, gprn, sprn);
1352 }
1353
1354 void spr_write_tm(DisasContext *ctx, int sprn, int gprn)
1355 {
1356 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
1357 spr_write_generic(ctx, sprn, gprn);
1358 }
1359
1360 void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn)
1361 {
1362 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
1363 spr_read_prev_upper32(ctx, gprn, sprn);
1364 }
1365
1366 void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn)
1367 {
1368 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
1369 spr_write_prev_upper32(ctx, sprn, gprn);
1370 }
1371
1372 void spr_read_ebb(DisasContext *ctx, int gprn, int sprn)
1373 {
1374 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
1375 spr_read_generic(ctx, gprn, sprn);
1376 }
1377
1378 void spr_write_ebb(DisasContext *ctx, int sprn, int gprn)
1379 {
1380 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
1381 spr_write_generic(ctx, sprn, gprn);
1382 }
1383
1384 void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn)
1385 {
1386 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
1387 spr_read_prev_upper32(ctx, gprn, sprn);
1388 }
1389
1390 void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn)
1391 {
1392 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
1393 spr_write_prev_upper32(ctx, sprn, gprn);
1394 }
1395 #endif
1396
1397 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
1398 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
1399
1400 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
1401 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
1402
1403 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
1404 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
1405
1406 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
1407 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
1408
1409 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \
1410 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2)
1411
1412 #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \
1413 GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2)
1414
1415 typedef struct opcode_t {
1416 unsigned char opc1, opc2, opc3, opc4;
1417 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
1418 unsigned char pad[4];
1419 #endif
1420 opc_handler_t handler;
1421 const char *oname;
1422 } opcode_t;
1423
1424 /* Helpers for priv. check */
1425 #define GEN_PRIV \
1426 do { \
1427 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \
1428 } while (0)
1429
1430 #if defined(CONFIG_USER_ONLY)
1431 #define CHK_HV GEN_PRIV
1432 #define CHK_SV GEN_PRIV
1433 #define CHK_HVRM GEN_PRIV
1434 #else
1435 #define CHK_HV \
1436 do { \
1437 if (unlikely(ctx->pr || !ctx->hv)) { \
1438 GEN_PRIV; \
1439 } \
1440 } while (0)
1441 #define CHK_SV \
1442 do { \
1443 if (unlikely(ctx->pr)) { \
1444 GEN_PRIV; \
1445 } \
1446 } while (0)
1447 #define CHK_HVRM \
1448 do { \
1449 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
1450 GEN_PRIV; \
1451 } \
1452 } while (0)
1453 #endif
1454
1455 #define CHK_NONE
1456
1457 /*****************************************************************************/
1458 /* PowerPC instructions table */
1459
1460 #if defined(DO_PPC_STATISTICS)
1461 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
1462 { \
1463 .opc1 = op1, \
1464 .opc2 = op2, \
1465 .opc3 = op3, \
1466 .opc4 = 0xff, \
1467 .handler = { \
1468 .inval1 = invl, \
1469 .type = _typ, \
1470 .type2 = _typ2, \
1471 .handler = &gen_##name, \
1472 .oname = stringify(name), \
1473 }, \
1474 .oname = stringify(name), \
1475 }
1476 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
1477 { \
1478 .opc1 = op1, \
1479 .opc2 = op2, \
1480 .opc3 = op3, \
1481 .opc4 = 0xff, \
1482 .handler = { \
1483 .inval1 = invl1, \
1484 .inval2 = invl2, \
1485 .type = _typ, \
1486 .type2 = _typ2, \
1487 .handler = &gen_##name, \
1488 .oname = stringify(name), \
1489 }, \
1490 .oname = stringify(name), \
1491 }
1492 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
1493 { \
1494 .opc1 = op1, \
1495 .opc2 = op2, \
1496 .opc3 = op3, \
1497 .opc4 = 0xff, \
1498 .handler = { \
1499 .inval1 = invl, \
1500 .type = _typ, \
1501 .type2 = _typ2, \
1502 .handler = &gen_##name, \
1503 .oname = onam, \
1504 }, \
1505 .oname = onam, \
1506 }
1507 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
1508 { \
1509 .opc1 = op1, \
1510 .opc2 = op2, \
1511 .opc3 = op3, \
1512 .opc4 = op4, \
1513 .handler = { \
1514 .inval1 = invl, \
1515 .type = _typ, \
1516 .type2 = _typ2, \
1517 .handler = &gen_##name, \
1518 .oname = stringify(name), \
1519 }, \
1520 .oname = stringify(name), \
1521 }
1522 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \
1523 { \
1524 .opc1 = op1, \
1525 .opc2 = op2, \
1526 .opc3 = op3, \
1527 .opc4 = op4, \
1528 .handler = { \
1529 .inval1 = invl, \
1530 .type = _typ, \
1531 .type2 = _typ2, \
1532 .handler = &gen_##name, \
1533 .oname = onam, \
1534 }, \
1535 .oname = onam, \
1536 }
1537 #else
1538 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
1539 { \
1540 .opc1 = op1, \
1541 .opc2 = op2, \
1542 .opc3 = op3, \
1543 .opc4 = 0xff, \
1544 .handler = { \
1545 .inval1 = invl, \
1546 .type = _typ, \
1547 .type2 = _typ2, \
1548 .handler = &gen_##name, \
1549 }, \
1550 .oname = stringify(name), \
1551 }
1552 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
1553 { \
1554 .opc1 = op1, \
1555 .opc2 = op2, \
1556 .opc3 = op3, \
1557 .opc4 = 0xff, \
1558 .handler = { \
1559 .inval1 = invl1, \
1560 .inval2 = invl2, \
1561 .type = _typ, \
1562 .type2 = _typ2, \
1563 .handler = &gen_##name, \
1564 }, \
1565 .oname = stringify(name), \
1566 }
1567 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
1568 { \
1569 .opc1 = op1, \
1570 .opc2 = op2, \
1571 .opc3 = op3, \
1572 .opc4 = 0xff, \
1573 .handler = { \
1574 .inval1 = invl, \
1575 .type = _typ, \
1576 .type2 = _typ2, \
1577 .handler = &gen_##name, \
1578 }, \
1579 .oname = onam, \
1580 }
1581 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
1582 { \
1583 .opc1 = op1, \
1584 .opc2 = op2, \
1585 .opc3 = op3, \
1586 .opc4 = op4, \
1587 .handler = { \
1588 .inval1 = invl, \
1589 .type = _typ, \
1590 .type2 = _typ2, \
1591 .handler = &gen_##name, \
1592 }, \
1593 .oname = stringify(name), \
1594 }
1595 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \
1596 { \
1597 .opc1 = op1, \
1598 .opc2 = op2, \
1599 .opc3 = op3, \
1600 .opc4 = op4, \
1601 .handler = { \
1602 .inval1 = invl, \
1603 .type = _typ, \
1604 .type2 = _typ2, \
1605 .handler = &gen_##name, \
1606 }, \
1607 .oname = onam, \
1608 }
1609 #endif
1610
1611 /* Invalid instruction */
1612 static void gen_invalid(DisasContext *ctx)
1613 {
1614 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
1615 }
1616
1617 static opc_handler_t invalid_handler = {
1618 .inval1 = 0xFFFFFFFF,
1619 .inval2 = 0xFFFFFFFF,
1620 .type = PPC_NONE,
1621 .type2 = PPC_NONE,
1622 .handler = gen_invalid,
1623 };
1624
1625 /*** Integer comparison ***/
1626
1627 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
1628 {
1629 TCGv t0 = tcg_temp_new();
1630 TCGv t1 = tcg_temp_new();
1631 TCGv_i32 t = tcg_temp_new_i32();
1632
1633 tcg_gen_movi_tl(t0, CRF_EQ);
1634 tcg_gen_movi_tl(t1, CRF_LT);
1635 tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU),
1636 t0, arg0, arg1, t1, t0);
1637 tcg_gen_movi_tl(t1, CRF_GT);
1638 tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU),
1639 t0, arg0, arg1, t1, t0);
1640
1641 tcg_gen_trunc_tl_i32(t, t0);
1642 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
1643 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t);
1644
1645 tcg_temp_free(t0);
1646 tcg_temp_free(t1);
1647 tcg_temp_free_i32(t);
1648 }
1649
1650 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
1651 {
1652 TCGv t0 = tcg_const_tl(arg1);
1653 gen_op_cmp(arg0, t0, s, crf);
1654 tcg_temp_free(t0);
1655 }
1656
1657 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
1658 {
1659 TCGv t0, t1;
1660 t0 = tcg_temp_new();
1661 t1 = tcg_temp_new();
1662 if (s) {
1663 tcg_gen_ext32s_tl(t0, arg0);
1664 tcg_gen_ext32s_tl(t1, arg1);
1665 } else {
1666 tcg_gen_ext32u_tl(t0, arg0);
1667 tcg_gen_ext32u_tl(t1, arg1);
1668 }
1669 gen_op_cmp(t0, t1, s, crf);
1670 tcg_temp_free(t1);
1671 tcg_temp_free(t0);
1672 }
1673
1674 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
1675 {
1676 TCGv t0 = tcg_const_tl(arg1);
1677 gen_op_cmp32(arg0, t0, s, crf);
1678 tcg_temp_free(t0);
1679 }
1680
1681 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
1682 {
1683 if (NARROW_MODE(ctx)) {
1684 gen_op_cmpi32(reg, 0, 1, 0);
1685 } else {
1686 gen_op_cmpi(reg, 0, 1, 0);
1687 }
1688 }
1689
1690 /* cmp */
1691 static void gen_cmp(DisasContext *ctx)
1692 {
1693 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
1694 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
1695 1, crfD(ctx->opcode));
1696 } else {
1697 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
1698 1, crfD(ctx->opcode));
1699 }
1700 }
1701
1702 /* cmpi */
1703 static void gen_cmpi(DisasContext *ctx)
1704 {
1705 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
1706 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
1707 1, crfD(ctx->opcode));
1708 } else {
1709 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
1710 1, crfD(ctx->opcode));
1711 }
1712 }
1713
1714 /* cmpl */
1715 static void gen_cmpl(DisasContext *ctx)
1716 {
1717 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
1718 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
1719 0, crfD(ctx->opcode));
1720 } else {
1721 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
1722 0, crfD(ctx->opcode));
1723 }
1724 }
1725
1726 /* cmpli */
1727 static void gen_cmpli(DisasContext *ctx)
1728 {
1729 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
1730 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
1731 0, crfD(ctx->opcode));
1732 } else {
1733 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
1734 0, crfD(ctx->opcode));
1735 }
1736 }
1737
1738 /* cmprb - range comparison: isupper, isaplha, islower*/
1739 static void gen_cmprb(DisasContext *ctx)
1740 {
1741 TCGv_i32 src1 = tcg_temp_new_i32();
1742 TCGv_i32 src2 = tcg_temp_new_i32();
1743 TCGv_i32 src2lo = tcg_temp_new_i32();
1744 TCGv_i32 src2hi = tcg_temp_new_i32();
1745 TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)];
1746
1747 tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]);
1748 tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]);
1749
1750 tcg_gen_andi_i32(src1, src1, 0xFF);
1751 tcg_gen_ext8u_i32(src2lo, src2);
1752 tcg_gen_shri_i32(src2, src2, 8);
1753 tcg_gen_ext8u_i32(src2hi, src2);
1754
1755 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
1756 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
1757 tcg_gen_and_i32(crf, src2lo, src2hi);
1758
1759 if (ctx->opcode & 0x00200000) {
1760 tcg_gen_shri_i32(src2, src2, 8);
1761 tcg_gen_ext8u_i32(src2lo, src2);
1762 tcg_gen_shri_i32(src2, src2, 8);
1763 tcg_gen_ext8u_i32(src2hi, src2);
1764 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
1765 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
1766 tcg_gen_and_i32(src2lo, src2lo, src2hi);
1767 tcg_gen_or_i32(crf, crf, src2lo);
1768 }
1769 tcg_gen_shli_i32(crf, crf, CRF_GT_BIT);
1770 tcg_temp_free_i32(src1);
1771 tcg_temp_free_i32(src2);
1772 tcg_temp_free_i32(src2lo);
1773 tcg_temp_free_i32(src2hi);
1774 }
1775
1776 #if defined(TARGET_PPC64)
1777 /* cmpeqb */
1778 static void gen_cmpeqb(DisasContext *ctx)
1779 {
1780 gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1781 cpu_gpr[rB(ctx->opcode)]);
1782 }
1783 #endif
1784
1785 /* isel (PowerPC 2.03 specification) */
1786 static void gen_isel(DisasContext *ctx)
1787 {
1788 uint32_t bi = rC(ctx->opcode);
1789 uint32_t mask = 0x08 >> (bi & 0x03);
1790 TCGv t0 = tcg_temp_new();
1791 TCGv zr;
1792
1793 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]);
1794 tcg_gen_andi_tl(t0, t0, mask);
1795
1796 zr = tcg_const_tl(0);
1797 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr,
1798 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr,
1799 cpu_gpr[rB(ctx->opcode)]);
1800 tcg_temp_free(zr);
1801 tcg_temp_free(t0);
1802 }
1803
1804 /* cmpb: PowerPC 2.05 specification */
1805 static void gen_cmpb(DisasContext *ctx)
1806 {
1807 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
1808 cpu_gpr[rB(ctx->opcode)]);
1809 }
1810
1811 /*** Integer arithmetic ***/
1812
1813 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
1814 TCGv arg1, TCGv arg2, int sub)
1815 {
1816 TCGv t0 = tcg_temp_new();
1817
1818 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
1819 tcg_gen_xor_tl(t0, arg1, arg2);
1820 if (sub) {
1821 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
1822 } else {
1823 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
1824 }
1825 tcg_temp_free(t0);
1826 if (NARROW_MODE(ctx)) {
1827 tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1);
1828 if (is_isa300(ctx)) {
1829 tcg_gen_mov_tl(cpu_ov32, cpu_ov);
1830 }
1831 } else {
1832 if (is_isa300(ctx)) {
1833 tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1);
1834 }
1835 tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1);
1836 }
1837 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1838 }
1839
1840 static inline void gen_op_arith_compute_ca32(DisasContext *ctx,
1841 TCGv res, TCGv arg0, TCGv arg1,
1842 TCGv ca32, int sub)
1843 {
1844 TCGv t0;
1845
1846 if (!is_isa300(ctx)) {
1847 return;
1848 }
1849
1850 t0 = tcg_temp_new();
1851 if (sub) {
1852 tcg_gen_eqv_tl(t0, arg0, arg1);
1853 } else {
1854 tcg_gen_xor_tl(t0, arg0, arg1);
1855 }
1856 tcg_gen_xor_tl(t0, t0, res);
1857 tcg_gen_extract_tl(ca32, t0, 32, 1);
1858 tcg_temp_free(t0);
1859 }
1860
1861 /* Common add function */
1862 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
1863 TCGv arg2, TCGv ca, TCGv ca32,
1864 bool add_ca, bool compute_ca,
1865 bool compute_ov, bool compute_rc0)
1866 {
1867 TCGv t0 = ret;
1868
1869 if (compute_ca || compute_ov) {
1870 t0 = tcg_temp_new();
1871 }
1872
1873 if (compute_ca) {
1874 if (NARROW_MODE(ctx)) {
1875 /*
1876 * Caution: a non-obvious corner case of the spec is that
1877 * we must produce the *entire* 64-bit addition, but
1878 * produce the carry into bit 32.
1879 */
1880 TCGv t1 = tcg_temp_new();
1881 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
1882 tcg_gen_add_tl(t0, arg1, arg2);
1883 if (add_ca) {
1884 tcg_gen_add_tl(t0, t0, ca);
1885 }
1886 tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */
1887 tcg_temp_free(t1);
1888 tcg_gen_extract_tl(ca, ca, 32, 1);
1889 if (is_isa300(ctx)) {
1890 tcg_gen_mov_tl(ca32, ca);
1891 }
1892 } else {
1893 TCGv zero = tcg_const_tl(0);
1894 if (add_ca) {
1895 tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero);
1896 tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero);
1897 } else {
1898 tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero);
1899 }
1900 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0);
1901 tcg_temp_free(zero);
1902 }
1903 } else {
1904 tcg_gen_add_tl(t0, arg1, arg2);
1905 if (add_ca) {
1906 tcg_gen_add_tl(t0, t0, ca);
1907 }
1908 }
1909
1910 if (compute_ov) {
1911 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
1912 }
1913 if (unlikely(compute_rc0)) {
1914 gen_set_Rc0(ctx, t0);
1915 }
1916
1917 if (t0 != ret) {
1918 tcg_gen_mov_tl(ret, t0);
1919 tcg_temp_free(t0);
1920 }
1921 }
1922 /* Add functions with two operands */
1923 #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \
1924 static void glue(gen_, name)(DisasContext *ctx) \
1925 { \
1926 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
1927 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1928 ca, glue(ca, 32), \
1929 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1930 }
1931 /* Add functions with one operand and one immediate */
1932 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \
1933 add_ca, compute_ca, compute_ov) \
1934 static void glue(gen_, name)(DisasContext *ctx) \
1935 { \
1936 TCGv t0 = tcg_const_tl(const_val); \
1937 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
1938 cpu_gpr[rA(ctx->opcode)], t0, \
1939 ca, glue(ca, 32), \
1940 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1941 tcg_temp_free(t0); \
1942 }
1943
1944 /* add add. addo addo. */
1945 GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0)
1946 GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1)
1947 /* addc addc. addco addco. */
1948 GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0)
1949 GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1)
1950 /* adde adde. addeo addeo. */
1951 GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0)
1952 GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1)
1953 /* addme addme. addmeo addmeo. */
1954 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0)
1955 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1)
1956 /* addex */
1957 GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0);
1958 /* addze addze. addzeo addzeo.*/
1959 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0)
1960 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1)
1961 /* addi */
1962 static void gen_addi(DisasContext *ctx)
1963 {
1964 target_long simm = SIMM(ctx->opcode);
1965
1966 if (rA(ctx->opcode) == 0) {
1967 /* li case */
1968 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
1969 } else {
1970 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
1971 cpu_gpr[rA(ctx->opcode)], simm);
1972 }
1973 }
1974 /* addic addic.*/
1975 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
1976 {
1977 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1978 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1979 c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0);
1980 tcg_temp_free(c);
1981 }
1982
1983 static void gen_addic(DisasContext *ctx)
1984 {
1985 gen_op_addic(ctx, 0);
1986 }
1987
1988 static void gen_addic_(DisasContext *ctx)
1989 {
1990 gen_op_addic(ctx, 1);
1991 }
1992
1993 /* addis */
1994 static void gen_addis(DisasContext *ctx)
1995 {
1996 target_long simm = SIMM(ctx->opcode);
1997
1998 if (rA(ctx->opcode) == 0) {
1999 /* lis case */
2000 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
2001 } else {
2002 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
2003 cpu_gpr[rA(ctx->opcode)], simm << 16);
2004 }
2005 }
2006
2007 /* addpcis */
2008 static void gen_addpcis(DisasContext *ctx)
2009 {
2010 target_long d = DX(ctx->opcode);
2011
2012 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->base.pc_next + (d << 16));
2013 }
2014
2015 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
2016 TCGv arg2, int sign, int compute_ov)
2017 {
2018 TCGv_i32 t0 = tcg_temp_new_i32();
2019 TCGv_i32 t1 = tcg_temp_new_i32();
2020 TCGv_i32 t2 = tcg_temp_new_i32();
2021 TCGv_i32 t3 = tcg_temp_new_i32();
2022
2023 tcg_gen_trunc_tl_i32(t0, arg1);
2024 tcg_gen_trunc_tl_i32(t1, arg2);
2025 if (sign) {
2026 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
2027 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
2028 tcg_gen_and_i32(t2, t2, t3);
2029 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
2030 tcg_gen_or_i32(t2, t2, t3);
2031 tcg_gen_movi_i32(t3, 0);
2032 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
2033 tcg_gen_div_i32(t3, t0, t1);
2034 tcg_gen_extu_i32_tl(ret, t3);
2035 } else {
2036 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0);
2037 tcg_gen_movi_i32(t3, 0);
2038 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
2039 tcg_gen_divu_i32(t3, t0, t1);
2040 tcg_gen_extu_i32_tl(ret, t3);
2041 }
2042 if (compute_ov) {
2043 tcg_gen_extu_i32_tl(cpu_ov, t2);
2044 if (is_isa300(ctx)) {
2045 tcg_gen_extu_i32_tl(cpu_ov32, t2);
2046 }
2047 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
2048 }
2049 tcg_temp_free_i32(t0);
2050 tcg_temp_free_i32(t1);
2051 tcg_temp_free_i32(t2);
2052 tcg_temp_free_i32(t3);
2053
2054 if (unlikely(Rc(ctx->opcode) != 0)) {
2055 gen_set_Rc0(ctx, ret);
2056 }
2057 }
2058 /* Div functions */
2059 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
2060 static void glue(gen_, name)(DisasContext *ctx) \
2061 { \
2062 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
2063 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
2064 sign, compute_ov); \
2065 }
2066 /* divwu divwu. divwuo divwuo. */
2067 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
2068 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
2069 /* divw divw. divwo divwo. */
2070 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
2071 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
2072
2073 /* div[wd]eu[o][.] */
2074 #define GEN_DIVE(name, hlpr, compute_ov) \
2075 static void gen_##name(DisasContext *ctx) \
2076 { \
2077 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
2078 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
2079 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
2080 tcg_temp_free_i32(t0); \
2081 if (unlikely(Rc(ctx->opcode) != 0)) { \
2082 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
2083 } \
2084 }
2085
2086 GEN_DIVE(divweu, divweu, 0);
2087 GEN_DIVE(divweuo, divweu, 1);
2088 GEN_DIVE(divwe, divwe, 0);
2089 GEN_DIVE(divweo, divwe, 1);
2090
2091 #if defined(TARGET_PPC64)
2092 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
2093 TCGv arg2, int sign, int compute_ov)
2094 {
2095 TCGv_i64 t0 = tcg_temp_new_i64();
2096 TCGv_i64 t1 = tcg_temp_new_i64();
2097 TCGv_i64 t2 = tcg_temp_new_i64();
2098 TCGv_i64 t3 = tcg_temp_new_i64();
2099
2100 tcg_gen_mov_i64(t0, arg1);
2101 tcg_gen_mov_i64(t1, arg2);
2102 if (sign) {
2103 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
2104 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
2105 tcg_gen_and_i64(t2, t2, t3);
2106 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
2107 tcg_gen_or_i64(t2, t2, t3);
2108 tcg_gen_movi_i64(t3, 0);
2109 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
2110 tcg_gen_div_i64(ret, t0, t1);
2111 } else {
2112 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0);
2113 tcg_gen_movi_i64(t3, 0);
2114 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
2115 tcg_gen_divu_i64(ret, t0, t1);
2116 }
2117 if (compute_ov) {
2118 tcg_gen_mov_tl(cpu_ov, t2);
2119 if (is_isa300(ctx)) {
2120 tcg_gen_mov_tl(cpu_ov32, t2);
2121 }
2122 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
2123 }
2124 tcg_temp_free_i64(t0);
2125 tcg_temp_free_i64(t1);
2126 tcg_temp_free_i64(t2);
2127 tcg_temp_free_i64(t3);
2128
2129 if (unlikely(Rc(ctx->opcode) != 0)) {
2130 gen_set_Rc0(ctx, ret);
2131 }
2132 }
2133
2134 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
2135 static void glue(gen_, name)(DisasContext *ctx) \
2136 { \
2137 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
2138 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
2139 sign, compute_ov); \
2140 }
2141 /* divdu divdu. divduo divduo. */
2142 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
2143 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
2144 /* divd divd. divdo divdo. */
2145 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
2146 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
2147
2148 GEN_DIVE(divdeu, divdeu, 0);
2149 GEN_DIVE(divdeuo, divdeu, 1);
2150 GEN_DIVE(divde, divde, 0);
2151 GEN_DIVE(divdeo, divde, 1);
2152 #endif
2153
2154 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1,
2155 TCGv arg2, int sign)
2156 {
2157 TCGv_i32 t0 = tcg_temp_new_i32();
2158 TCGv_i32 t1 = tcg_temp_new_i32();
2159
2160 tcg_gen_trunc_tl_i32(t0, arg1);
2161 tcg_gen_trunc_tl_i32(t1, arg2);
2162 if (sign) {
2163 TCGv_i32 t2 = tcg_temp_new_i32();
2164 TCGv_i32 t3 = tcg_temp_new_i32();
2165 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
2166 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
2167 tcg_gen_and_i32(t2, t2, t3);
2168 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
2169 tcg_gen_or_i32(t2, t2, t3);
2170 tcg_gen_movi_i32(t3, 0);
2171 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
2172 tcg_gen_rem_i32(t3, t0, t1);
2173 tcg_gen_ext_i32_tl(ret, t3);
2174 tcg_temp_free_i32(t2);
2175 tcg_temp_free_i32(t3);
2176 } else {
2177 TCGv_i32 t2 = tcg_const_i32(1);
2178 TCGv_i32 t3 = tcg_const_i32(0);
2179 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1);
2180 tcg_gen_remu_i32(t3, t0, t1);
2181 tcg_gen_extu_i32_tl(ret, t3);
2182 tcg_temp_free_i32(t2);
2183 tcg_temp_free_i32(t3);
2184 }
2185 tcg_temp_free_i32(t0);
2186 tcg_temp_free_i32(t1);
2187 }
2188
2189 #define GEN_INT_ARITH_MODW(name, opc3, sign) \
2190 static void glue(gen_, name)(DisasContext *ctx) \
2191 { \
2192 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \
2193 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
2194 sign); \
2195 }
2196
2197 GEN_INT_ARITH_MODW(moduw, 0x08, 0);
2198 GEN_INT_ARITH_MODW(modsw, 0x18, 1);
2199
2200 #if defined(TARGET_PPC64)
2201 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1,
2202 TCGv arg2, int sign)
2203 {
2204 TCGv_i64 t0 = tcg_temp_new_i64();
2205 TCGv_i64 t1 = tcg_temp_new_i64();
2206
2207 tcg_gen_mov_i64(t0, arg1);
2208 tcg_gen_mov_i64(t1, arg2);
2209 if (sign) {
2210 TCGv_i64 t2 = tcg_temp_new_i64();
2211 TCGv_i64 t3 = tcg_temp_new_i64();
2212 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
2213 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
2214 tcg_gen_and_i64(t2, t2, t3);
2215 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
2216 tcg_gen_or_i64(t2, t2, t3);
2217 tcg_gen_movi_i64(t3, 0);
2218 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
2219 tcg_gen_rem_i64(ret, t0, t1);
2220 tcg_temp_free_i64(t2);
2221 tcg_temp_free_i64(t3);
2222 } else {
2223 TCGv_i64 t2 = tcg_const_i64(1);
2224 TCGv_i64 t3 = tcg_const_i64(0);
2225 tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1);
2226 tcg_gen_remu_i64(ret, t0, t1);
2227 tcg_temp_free_i64(t2);
2228 tcg_temp_free_i64(t3);
2229 }
2230 tcg_temp_free_i64(t0);
2231 tcg_temp_free_i64(t1);
2232 }
2233
2234 #define GEN_INT_ARITH_MODD(name, opc3, sign) \
2235 static void glue(gen_, name)(DisasContext *ctx) \
2236 { \
2237 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \
2238 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
2239 sign); \
2240 }
2241
2242 GEN_INT_ARITH_MODD(modud, 0x08, 0);
2243 GEN_INT_ARITH_MODD(modsd, 0x18, 1);
2244 #endif
2245
2246 /* mulhw mulhw. */
2247 static void gen_mulhw(DisasContext *ctx)
2248 {
2249 TCGv_i32 t0 = tcg_temp_new_i32();
2250 TCGv_i32 t1 = tcg_temp_new_i32();
2251
2252 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
2253 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
2254 tcg_gen_muls2_i32(t0, t1, t0, t1);
2255 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
2256 tcg_temp_free_i32(t0);
2257 tcg_temp_free_i32(t1);
2258 if (unlikely(Rc(ctx->opcode) != 0)) {
2259 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
2260 }
2261 }
2262
2263 /* mulhwu mulhwu. */
2264 static void gen_mulhwu(DisasContext *ctx)
2265 {
2266 TCGv_i32 t0 = tcg_temp_new_i32();
2267 TCGv_i32 t1 = tcg_temp_new_i32();
2268
2269 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
2270 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
2271 tcg_gen_mulu2_i32(t0, t1, t0, t1);
2272 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
2273 tcg_temp_free_i32(t0);
2274 tcg_temp_free_i32(t1);
2275 if (unlikely(Rc(ctx->opcode) != 0)) {
2276 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
2277 }
2278 }
2279
2280 /* mullw mullw. */
2281 static void gen_mullw(DisasContext *ctx)
2282 {
2283 #if defined(TARGET_PPC64)
2284 TCGv_i64 t0, t1;
2285 t0 = tcg_temp_new_i64();
2286 t1 = tcg_temp_new_i64();
2287 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
2288 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
2289 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
2290 tcg_temp_free(t0);
2291 tcg_temp_free(t1);
2292 #else
2293 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
2294 cpu_gpr[rB(ctx->opcode)]);
2295 #endif
2296 if (unlikely(Rc(ctx->opcode) != 0)) {
2297 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
2298 }
2299 }
2300
2301 /* mullwo mullwo. */
2302 static void gen_mullwo(DisasContext *ctx)
2303 {
2304 TCGv_i32 t0 = tcg_temp_new_i32();
2305 TCGv_i32 t1 = tcg_temp_new_i32();
2306
2307 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
2308 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
2309 tcg_gen_muls2_i32(t0, t1, t0, t1);
2310 #if defined(TARGET_PPC64)
2311 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
2312 #else
2313 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
2314 #endif
2315
2316 tcg_gen_sari_i32(t0, t0, 31);
2317 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
2318 tcg_gen_extu_i32_tl(cpu_ov, t0);
2319 if (is_isa300(ctx)) {
2320 tcg_gen_mov_tl(cpu_ov32, cpu_ov);
2321 }
2322 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
2323
2324 tcg_temp_free_i32(t0);
2325 tcg_temp_free_i32(t1);
2326 if (unlikely(Rc(ctx->opcode) != 0)) {
2327 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
2328 }
2329 }
2330
2331 /* mulli */
2332 static void gen_mulli(DisasContext *ctx)
2333 {
2334 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
2335 SIMM(ctx->opcode));
2336 }
2337
2338 #if defined(TARGET_PPC64)
2339 /* mulhd mulhd. */
2340 static void gen_mulhd(DisasContext *ctx)
2341 {
2342 TCGv lo = tcg_temp_new();
2343 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
2344 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2345 tcg_temp_free(lo);
2346 if (unlikely(Rc(ctx->opcode) != 0)) {
2347 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
2348 }
2349 }
2350
2351 /* mulhdu mulhdu. */
2352 static void gen_mulhdu(DisasContext *ctx)
2353 {
2354 TCGv lo = tcg_temp_new();
2355 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
2356 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2357 tcg_temp_free(lo);
2358 if (unlikely(Rc(ctx->opcode) != 0)) {
2359 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
2360 }
2361 }
2362
2363 /* mulld mulld. */
2364 static void gen_mulld(DisasContext *ctx)
2365 {
2366 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
2367 cpu_gpr[rB(ctx->opcode)]);
2368 if (unlikely(Rc(ctx->opcode) != 0)) {
2369 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
2370 }
2371 }
2372
2373 /* mulldo mulldo. */
2374 static void gen_mulldo(DisasContext *ctx)
2375 {
2376 TCGv_i64 t0 = tcg_temp_new_i64();
2377 TCGv_i64 t1 = tcg_temp_new_i64();
2378
2379 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
2380 cpu_gpr[rB(ctx->opcode)]);
2381 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
2382
2383 tcg_gen_sari_i64(t0, t0, 63);
2384 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
2385 if (is_isa300(ctx)) {
2386 tcg_gen_mov_tl(cpu_ov32, cpu_ov);
2387 }
2388 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
2389
2390 tcg_temp_free_i64(t0);
2391 tcg_temp_free_i64(t1);
2392
2393 if (unlikely(Rc(ctx->opcode) != 0)) {
2394 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
2395 }
2396 }
2397 #endif
2398
2399 /* Common subf function */
2400 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
2401 TCGv arg2, bool add_ca, bool compute_ca,
2402 bool compute_ov, bool compute_rc0)
2403 {
2404 TCGv t0 = ret;
2405
2406 if (compute_ca || compute_ov) {
2407 t0 = tcg_temp_new();
2408 }
2409
2410 if (compute_ca) {
2411 /* dest = ~arg1 + arg2 [+ ca]. */
2412 if (NARROW_MODE(ctx)) {
2413 /*
2414 * Caution: a non-obvious corner case of the spec is that
2415 * we must produce the *entire* 64-bit addition, but
2416 * produce the carry into bit 32.
2417 */
2418 TCGv inv1 = tcg_temp_new();
2419 TCGv t1 = tcg_temp_new();
2420 tcg_gen_not_tl(inv1, arg1);
2421 if (add_ca) {
2422 tcg_gen_add_tl(t0, arg2, cpu_ca);
2423 } else {
2424 tcg_gen_addi_tl(t0, arg2, 1);
2425 }
2426 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
2427 tcg_gen_add_tl(t0, t0, inv1);
2428 tcg_temp_free(inv1);
2429 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
2430 tcg_temp_free(t1);
2431 tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1);
2432 if (is_isa300(ctx)) {
2433 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
2434 }
2435 } else if (add_ca) {
2436 TCGv zero, inv1 = tcg_temp_new();
2437 tcg_gen_not_tl(inv1, arg1);
2438 zero = tcg_const_tl(0);
2439 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
2440 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
2441 gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0);
2442 tcg_temp_free(zero);
2443 tcg_temp_free(inv1);
2444 } else {
2445 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
2446 tcg_gen_sub_tl(t0, arg2, arg1);
2447 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1);
2448 }
2449 } else if (add_ca) {
2450 /*
2451 * Since we're ignoring carry-out, we can simplify the
2452 * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1.
2453 */
2454 tcg_gen_sub_tl(t0, arg2, arg1);
2455 tcg_gen_add_tl(t0, t0, cpu_ca);
2456 tcg_gen_subi_tl(t0, t0, 1);
2457 } else {
2458 tcg_gen_sub_tl(t0, arg2, arg1);
2459 }
2460
2461 if (compute_ov) {
2462 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
2463 }
2464 if (unlikely(compute_rc0)) {
2465 gen_set_Rc0(ctx, t0);
2466 }
2467
2468 if (t0 != ret) {
2469 tcg_gen_mov_tl(ret, t0);
2470 tcg_temp_free(t0);
2471 }
2472 }
2473 /* Sub functions with Two operands functions */
2474 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
2475 static void glue(gen_, name)(DisasContext *ctx) \
2476 { \
2477 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
2478 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
2479 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
2480 }
2481 /* Sub functions with one operand and one immediate */
2482 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
2483 add_ca, compute_ca, compute_ov) \
2484 static void glue(gen_, name)(DisasContext *ctx) \
2485 { \
2486 TCGv t0 = tcg_const_tl(const_val); \
2487 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
2488 cpu_gpr[rA(ctx->opcode)], t0, \
2489 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
2490 tcg_temp_free(t0); \
2491 }
2492 /* subf subf. subfo subfo. */
2493 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
2494 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
2495 /* subfc subfc. subfco subfco. */
2496 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
2497 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
2498 /* subfe subfe. subfeo subfo. */
2499 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
2500 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
2501 /* subfme subfme. subfmeo subfmeo. */
2502 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
2503 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
2504 /* subfze subfze. subfzeo subfzeo.*/
2505 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
2506 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
2507
2508 /* subfic */
2509 static void gen_subfic(DisasContext *ctx)
2510 {
2511 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
2512 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
2513 c, 0, 1, 0, 0);
2514 tcg_temp_free(c);
2515 }
2516
2517 /* neg neg. nego nego. */
2518 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
2519 {
2520 TCGv zero = tcg_const_tl(0);
2521 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
2522 zero, 0, 0, compute_ov, Rc(ctx->opcode));
2523 tcg_temp_free(zero);
2524 }
2525
2526 static void gen_neg(DisasContext *ctx)
2527 {
2528 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
2529 if (unlikely(Rc(ctx->opcode))) {
2530 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
2531 }
2532 }
2533
2534 static void gen_nego(DisasContext *ctx)
2535 {
2536 gen_op_arith_neg(ctx, 1);
2537 }
2538
2539 /*** Integer logical ***/
2540 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
2541 static void glue(gen_, name)(DisasContext *ctx) \
2542 { \
2543 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
2544 cpu_gpr[rB(ctx->opcode)]); \
2545 if (unlikely(Rc(ctx->opcode) != 0)) \
2546 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
2547 }
2548
2549 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
2550 static void glue(gen_, name)(DisasContext *ctx) \
2551 { \
2552 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
2553 if (unlikely(Rc(ctx->opcode) != 0)) \
2554 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
2555 }
2556
2557 /* and & and. */
2558 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
2559 /* andc & andc. */
2560 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
2561
2562 /* andi. */
2563 static void gen_andi_(DisasContext *ctx)
2564 {
2565 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
2566 UIMM(ctx->opcode));
2567 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2568 }
2569
2570 /* andis. */
2571 static void gen_andis_(DisasContext *ctx)
2572 {
2573 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
2574 UIMM(ctx->opcode) << 16);
2575 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2576 }
2577
2578 /* cntlzw */
2579 static void gen_cntlzw(DisasContext *ctx)
2580 {
2581 TCGv_i32 t = tcg_temp_new_i32();
2582
2583 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]);
2584 tcg_gen_clzi_i32(t, t, 32);
2585 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t);
2586 tcg_temp_free_i32(t);
2587
2588 if (unlikely(Rc(ctx->opcode) != 0)) {
2589 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2590 }
2591 }
2592
2593 /* cnttzw */
2594 static void gen_cnttzw(DisasContext *ctx)
2595 {
2596 TCGv_i32 t = tcg_temp_new_i32();
2597
2598 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]);
2599 tcg_gen_ctzi_i32(t, t, 32);
2600 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t);
2601 tcg_temp_free_i32(t);
2602
2603 if (unlikely(Rc(ctx->opcode) != 0)) {
2604 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2605 }
2606 }
2607
2608 /* eqv & eqv. */
2609 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
2610 /* extsb & extsb. */
2611 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
2612 /* extsh & extsh. */
2613 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
2614 /* nand & nand. */
2615 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
2616 /* nor & nor. */
2617 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
2618
2619 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
2620 static void gen_pause(DisasContext *ctx)
2621 {
2622 TCGv_i32 t0 = tcg_const_i32(0);
2623 tcg_gen_st_i32(t0, cpu_env,
2624 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
2625 tcg_temp_free_i32(t0);
2626
2627 /* Stop translation, this gives other CPUs a chance to run */
2628 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
2629 }
2630 #endif /* defined(TARGET_PPC64) */
2631
2632 /* or & or. */
2633 static void gen_or(DisasContext *ctx)
2634 {
2635 int rs, ra, rb;
2636
2637 rs = rS(ctx->opcode);
2638 ra = rA(ctx->opcode);
2639 rb = rB(ctx->opcode);
2640 /* Optimisation for mr. ri case */
2641 if (rs != ra || rs != rb) {
2642 if (rs != rb) {
2643 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
2644 } else {
2645 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
2646 }
2647 if (unlikely(Rc(ctx->opcode) != 0)) {
2648 gen_set_Rc0(ctx, cpu_gpr[ra]);
2649 }
2650 } else if (unlikely(Rc(ctx->opcode) != 0)) {
2651 gen_set_Rc0(ctx, cpu_gpr[rs]);
2652 #if defined(TARGET_PPC64)
2653 } else if (rs != 0) { /* 0 is nop */
2654 int prio = 0;
2655
2656 switch (rs) {
2657 case 1:
2658 /* Set process priority to low */
2659 prio = 2;
2660 break;
2661 case 6:
2662 /* Set process priority to medium-low */
2663 prio = 3;
2664 break;
2665 case 2:
2666 /* Set process priority to normal */
2667 prio = 4;
2668 break;
2669 #if !defined(CONFIG_USER_ONLY)
2670 case 31:
2671 if (!ctx->pr) {
2672 /* Set process priority to very low */
2673 prio = 1;
2674 }
2675 break;
2676 case 5:
2677 if (!ctx->pr) {
2678 /* Set process priority to medium-hight */
2679 prio = 5;
2680 }
2681 break;
2682 case 3:
2683 if (!ctx->pr) {
2684 /* Set process priority to high */
2685 prio = 6;
2686 }
2687 break;
2688 case 7:
2689 if (ctx->hv && !ctx->pr) {
2690 /* Set process priority to very high */
2691 prio = 7;
2692 }
2693 break;
2694 #endif
2695 default:
2696 break;
2697 }
2698 if (prio) {
2699 TCGv t0 = tcg_temp_new();
2700 gen_load_spr(t0, SPR_PPR);
2701 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
2702 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
2703 gen_store_spr(SPR_PPR, t0);
2704 tcg_temp_free(t0);
2705 }
2706 #if !defined(CONFIG_USER_ONLY)
2707 /*
2708 * Pause out of TCG otherwise spin loops with smt_low eat too
2709 * much CPU and the kernel hangs. This applies to all
2710 * encodings other than no-op, e.g., miso(rs=26), yield(27),
2711 * mdoio(29), mdoom(30), and all currently undefined.
2712 */
2713 gen_pause(ctx);
2714 #endif
2715 #endif
2716 }
2717 }
2718 /* orc & orc. */
2719 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
2720
2721 /* xor & xor. */
2722 static void gen_xor(DisasContext *ctx)
2723 {
2724 /* Optimisation for "set to zero" case */
2725 if (rS(ctx->opcode) != rB(ctx->opcode)) {
2726 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
2727 cpu_gpr[rB(ctx->opcode)]);
2728 } else {
2729 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2730 }
2731 if (unlikely(Rc(ctx->opcode) != 0)) {
2732 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2733 }
2734 }
2735
2736 /* ori */
2737 static void gen_ori(DisasContext *ctx)
2738 {
2739 target_ulong uimm = UIMM(ctx->opcode);
2740
2741 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
2742 return;
2743 }
2744 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
2745 }
2746
2747 /* oris */
2748 static void gen_oris(DisasContext *ctx)
2749 {
2750 target_ulong uimm = UIMM(ctx->opcode);
2751
2752 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
2753 /* NOP */
2754 return;
2755 }
2756 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
2757 uimm << 16);
2758 }
2759
2760 /* xori */
2761 static void gen_xori(DisasContext *ctx)
2762 {
2763 target_ulong uimm = UIMM(ctx->opcode);
2764
2765 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
2766 /* NOP */
2767 return;
2768 }
2769 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
2770 }
2771
2772 /* xoris */
2773 static void gen_xoris(DisasContext *ctx)
2774 {
2775 target_ulong uimm = UIMM(ctx->opcode);
2776
2777 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
2778 /* NOP */
2779 return;
2780 }
2781 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
2782 uimm << 16);
2783 }
2784
2785 /* popcntb : PowerPC 2.03 specification */
2786 static void gen_popcntb(DisasContext *ctx)
2787 {
2788 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
2789 }
2790
2791 static void gen_popcntw(DisasContext *ctx)
2792 {
2793 #if defined(TARGET_PPC64)
2794 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
2795 #else
2796 tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
2797 #endif
2798 }
2799
2800 #if defined(TARGET_PPC64)
2801 /* popcntd: PowerPC 2.06 specification */
2802 static void gen_popcntd(DisasContext *ctx)
2803 {
2804 tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
2805 }
2806 #endif
2807
2808 /* prtyw: PowerPC 2.05 specification */
2809 static void gen_prtyw(DisasContext *ctx)
2810 {
2811 TCGv ra = cpu_gpr[rA(ctx->opcode)];
2812 TCGv rs = cpu_gpr[rS(ctx->opcode)];
2813 TCGv t0 = tcg_temp_new();
2814 tcg_gen_shri_tl(t0, rs, 16);
2815 tcg_gen_xor_tl(ra, rs, t0);
2816 tcg_gen_shri_tl(t0, ra, 8);
2817 tcg_gen_xor_tl(ra, ra, t0);
2818 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
2819 tcg_temp_free(t0);
2820 }
2821
2822 #if defined(TARGET_PPC64)
2823 /* prtyd: PowerPC 2.05 specification */
2824 static void gen_prtyd(DisasContext *ctx)
2825 {
2826 TCGv ra = cpu_gpr[rA(ctx->opcode)];
2827 TCGv rs = cpu_gpr[rS(ctx->opcode)];
2828 TCGv t0 = tcg_temp_new();
2829 tcg_gen_shri_tl(t0, rs, 32);
2830 tcg_gen_xor_tl(ra, rs, t0);
2831 tcg_gen_shri_tl(t0, ra, 16);
2832 tcg_gen_xor_tl(ra, ra, t0);
2833 tcg_gen_shri_tl(t0, ra, 8);
2834 tcg_gen_xor_tl(ra, ra, t0);
2835 tcg_gen_andi_tl(ra, ra, 1);
2836 tcg_temp_free(t0);
2837 }
2838 #endif
2839
2840 #if defined(TARGET_PPC64)
2841 /* bpermd */
2842 static void gen_bpermd(DisasContext *ctx)
2843 {
2844 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
2845 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2846 }
2847 #endif
2848
2849 #if defined(TARGET_PPC64)
2850 /* extsw & extsw. */
2851 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
2852
2853 /* cntlzd */
2854 static void gen_cntlzd(DisasContext *ctx)
2855 {
2856 tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64);
2857 if (unlikely(Rc(ctx->opcode) != 0)) {
2858 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2859 }
2860 }
2861
2862 /* cnttzd */
2863 static void gen_cnttzd(DisasContext *ctx)
2864 {
2865 tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64);
2866 if (unlikely(Rc(ctx->opcode) != 0)) {
2867 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2868 }
2869 }
2870
2871 /* darn */
2872 static void gen_darn(DisasContext *ctx)
2873 {
2874 int l = L(ctx->opcode);
2875
2876 if (l > 2) {
2877 tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1);
2878 } else {
2879 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
2880 gen_io_start();
2881 }
2882 if (l == 0) {
2883 gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]);
2884 } else {
2885 /* Return 64-bit random for both CRN and RRN */
2886 gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]);
2887 }
2888 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
2889 gen_stop_exception(ctx);
2890 }
2891 }
2892 }
2893 #endif
2894
2895 /*** Integer rotate ***/
2896
2897 /* rlwimi & rlwimi. */
2898 static void gen_rlwimi(DisasContext *ctx)
2899 {
2900 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2901 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2902 uint32_t sh = SH(ctx->opcode);
2903 uint32_t mb = MB(ctx->opcode);
2904 uint32_t me = ME(ctx->opcode);
2905
2906 if (sh == (31 - me) && mb <= me) {
2907 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
2908 } else {
2909 target_ulong mask;
2910 bool mask_in_32b = true;
2911 TCGv t1;
2912
2913 #if defined(TARGET_PPC64)
2914 mb += 32;
2915 me += 32;
2916 #endif
2917 mask = MASK(mb, me);
2918
2919 #if defined(TARGET_PPC64)
2920 if (mask > 0xffffffffu) {
2921 mask_in_32b = false;
2922 }
2923 #endif
2924 t1 = tcg_temp_new();
2925 if (mask_in_32b) {
2926 TCGv_i32 t0 = tcg_temp_new_i32();
2927 tcg_gen_trunc_tl_i32(t0, t_rs);
2928 tcg_gen_rotli_i32(t0, t0, sh);
2929 tcg_gen_extu_i32_tl(t1, t0);
2930 tcg_temp_free_i32(t0);
2931 } else {
2932 #if defined(TARGET_PPC64)
2933 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32);
2934 tcg_gen_rotli_i64(t1, t1, sh);
2935 #else
2936 g_assert_not_reached();
2937 #endif
2938 }
2939
2940 tcg_gen_andi_tl(t1, t1, mask);
2941 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
2942 tcg_gen_or_tl(t_ra, t_ra, t1);
2943 tcg_temp_free(t1);
2944 }
2945 if (unlikely(Rc(ctx->opcode) != 0)) {
2946 gen_set_Rc0(ctx, t_ra);
2947 }
2948 }
2949
2950 /* rlwinm & rlwinm. */
2951 static void gen_rlwinm(DisasContext *ctx)
2952 {
2953 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2954 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2955 int sh = SH(ctx->opcode);
2956 int mb = MB(ctx->opcode);
2957 int me = ME(ctx->opcode);
2958 int len = me - mb + 1;
2959 int rsh = (32 - sh) & 31;
2960
2961 if (sh != 0 && len > 0 && me == (31 - sh)) {
2962 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len);
2963 } else if (me == 31 && rsh + len <= 32) {
2964 tcg_gen_extract_tl(t_ra, t_rs, rsh, len);
2965 } else {
2966 target_ulong mask;
2967 bool mask_in_32b = true;
2968 #if defined(TARGET_PPC64)
2969 mb += 32;
2970 me += 32;
2971 #endif
2972 mask = MASK(mb, me);
2973 #if defined(TARGET_PPC64)
2974 if (mask > 0xffffffffu) {
2975 mask_in_32b = false;
2976 }
2977 #endif
2978 if (mask_in_32b) {
2979 if (sh == 0) {
2980 tcg_gen_andi_tl(t_ra, t_rs, mask);
2981 } else {
2982 TCGv_i32 t0 = tcg_temp_new_i32();
2983 tcg_gen_trunc_tl_i32(t0, t_rs);
2984 tcg_gen_rotli_i32(t0, t0, sh);
2985 tcg_gen_andi_i32(t0, t0, mask);
2986 tcg_gen_extu_i32_tl(t_ra, t0);
2987 tcg_temp_free_i32(t0);
2988 }
2989 } else {
2990 #if defined(TARGET_PPC64)
2991 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
2992 tcg_gen_rotli_i64(t_ra, t_ra, sh);
2993 tcg_gen_andi_i64(t_ra, t_ra, mask);
2994 #else
2995 g_assert_not_reached();
2996 #endif
2997 }
2998 }
2999 if (unlikely(Rc(ctx->opcode) != 0)) {
3000 gen_set_Rc0(ctx, t_ra);
3001 }
3002 }
3003
3004 /* rlwnm & rlwnm. */
3005 static void gen_rlwnm(DisasContext *ctx)
3006 {
3007 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
3008 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
3009 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
3010 uint32_t mb = MB(ctx->opcode);
3011 uint32_t me = ME(ctx->opcode);
3012 target_ulong mask;
3013 bool mask_in_32b = true;
3014
3015 #if defined(TARGET_PPC64)
3016 mb += 32;
3017 me += 32;
3018 #endif
3019 mask = MASK(mb, me);
3020
3021 #if defined(TARGET_PPC64)
3022 if (mask > 0xffffffffu) {
3023 mask_in_32b = false;
3024 }
3025 #endif
3026 if (mask_in_32b) {
3027 TCGv_i32 t0 = tcg_temp_new_i32();
3028 TCGv_i32 t1 = tcg_temp_new_i32();
3029 tcg_gen_trunc_tl_i32(t0, t_rb);
3030 tcg_gen_trunc_tl_i32(t1, t_rs);
3031 tcg_gen_andi_i32(t0, t0, 0x1f);
3032 tcg_gen_rotl_i32(t1, t1, t0);
3033 tcg_gen_extu_i32_tl(t_ra, t1);
3034 tcg_temp_free_i32(t0);
3035 tcg_temp_free_i32(t1);
3036 } else {
3037 #if defined(TARGET_PPC64)
3038 TCGv_i64 t0 = tcg_temp_new_i64();
3039 tcg_gen_andi_i64(t0, t_rb, 0x1f);
3040 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
3041 tcg_gen_rotl_i64(t_ra, t_ra, t0);
3042 tcg_temp_free_i64(t0);
3043 #else
3044 g_assert_not_reached();
3045 #endif
3046 }
3047
3048 tcg_gen_andi_tl(t_ra, t_ra, mask);
3049
3050 if (unlikely(Rc(ctx->opcode) != 0)) {
3051 gen_set_Rc0(ctx, t_ra);
3052 }
3053 }
3054
3055 #if defined(TARGET_PPC64)
3056 #define GEN_PPC64_R2(name, opc1, opc2) \
3057 static void glue(gen_, name##0)(DisasContext *ctx) \
3058 { \
3059 gen_##name(ctx, 0); \
3060 } \
3061 \
3062 static void glue(gen_, name##1)(DisasContext *ctx) \
3063 { \
3064 gen_##name(ctx, 1); \
3065 }
3066 #define GEN_PPC64_R4(name, opc1, opc2) \
3067 static void glue(gen_, name##0)(DisasContext *ctx) \
3068 { \
3069 gen_##name(ctx, 0, 0); \
3070 } \
3071 \
3072 static void glue(gen_, name##1)(DisasContext *ctx) \
3073 { \
3074 gen_##name(ctx, 0, 1); \
3075 } \
3076 \
3077 static void glue(gen_, name##2)(DisasContext *ctx) \
3078 { \
3079 gen_##name(ctx, 1, 0); \
3080 } \
3081 \
3082 static void glue(gen_, name##3)(DisasContext *ctx) \
3083 { \
3084 gen_##name(ctx, 1, 1); \
3085 }
3086
3087 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh)
3088 {
3089 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
3090 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
3091 int len = me - mb + 1;
3092 int rsh = (64 - sh) & 63;
3093
3094 if (sh != 0 && len > 0 && me == (63 - sh)) {
3095 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len);
3096 } else if (me == 63 && rsh + len <= 64) {
3097 tcg_gen_extract_tl(t_ra, t_rs, rsh, len);
3098 } else {
3099 tcg_gen_rotli_tl(t_ra, t_rs, sh);
3100 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
3101 }
3102 if (unlikely(Rc(ctx->opcode) != 0)) {
3103 gen_set_Rc0(ctx, t_ra);
3104 }
3105 }
3106
3107 /* rldicl - rldicl. */
3108 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
3109 {
3110 uint32_t sh, mb;
3111
3112 sh = SH(ctx->opcode) | (shn << 5);
3113 mb = MB(ctx->opcode) | (mbn << 5);
3114 gen_rldinm(ctx, mb, 63, sh);
3115 }
3116 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
3117
3118 /* rldicr - rldicr. */
3119 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
3120 {
3121 uint32_t sh, me;
3122
3123 sh = SH(ctx->opcode) | (shn << 5);
3124 me = MB(ctx->opcode) | (men << 5);
3125 gen_rldinm(ctx, 0, me, sh);
3126 }
3127 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
3128
3129 /* rldic - rldic. */
3130 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
3131 {
3132 uint32_t sh, mb;
3133
3134 sh = SH(ctx->opcode) | (shn << 5);
3135 mb = MB(ctx->opcode) | (mbn << 5);
3136 gen_rldinm(ctx, mb, 63 - sh, sh);
3137 }
3138 GEN_PPC64_R4(rldic, 0x1E, 0x04);
3139
3140 static void gen_rldnm(DisasContext *ctx, int mb, int me)
3141 {
3142 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
3143 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
3144 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
3145 TCGv t0;
3146
3147 t0 = tcg_temp_new();
3148 tcg_gen_andi_tl(t0, t_rb, 0x3f);
3149 tcg_gen_rotl_tl(t_ra, t_rs, t0);
3150 tcg_temp_free(t0);
3151
3152 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
3153 if (unlikely(Rc(ctx->opcode) != 0)) {
3154 gen_set_Rc0(ctx, t_ra);
3155 }
3156 }
3157
3158 /* rldcl - rldcl. */
3159 static inline void gen_rldcl(DisasContext *ctx, int mbn)
3160 {
3161 uint32_t mb;
3162
3163 mb = MB(ctx->opcode) | (mbn << 5);
3164 gen_rldnm(ctx, mb, 63);
3165 }
3166 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
3167
3168 /* rldcr - rldcr. */
3169 static inline void gen_rldcr(DisasContext *ctx, int men)
3170 {
3171 uint32_t me;
3172
3173 me = MB(ctx->opcode) | (men << 5);
3174 gen_rldnm(ctx, 0, me);
3175 }
3176 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
3177
3178 /* rldimi - rldimi. */
3179 static void gen_rldimi(DisasContext *ctx, int mbn, int shn)
3180 {
3181 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
3182 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
3183 uint32_t sh = SH(ctx->opcode) | (shn << 5);
3184 uint32_t mb = MB(ctx->opcode) | (mbn << 5);
3185 uint32_t me = 63 - sh;
3186
3187 if (mb <= me) {
3188 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
3189 } else {
3190 target_ulong mask = MASK(mb, me);
3191 TCGv t1 = tcg_temp_new();
3192
3193 tcg_gen_rotli_tl(t1, t_rs, sh);
3194 tcg_gen_andi_tl(t1, t1, mask);
3195 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
3196 tcg_gen_or_tl(t_ra, t_ra, t1);
3197 tcg_temp_free(t1);
3198 }
3199 if (unlikely(Rc(ctx->opcode) != 0)) {
3200 gen_set_Rc0(ctx, t_ra);
3201 }
3202 }
3203 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
3204 #endif
3205
3206 /*** Integer shift ***/
3207
3208 /* slw & slw. */
3209 static void gen_slw(DisasContext *ctx)
3210 {
3211 TCGv t0, t1;
3212
3213 t0 = tcg_temp_new();
3214 /* AND rS with a mask that is 0 when rB >= 0x20 */
3215 #if defined(TARGET_PPC64)
3216 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
3217 tcg_gen_sari_tl(t0, t0, 0x3f);
3218 #else
3219 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
3220 tcg_gen_sari_tl(t0, t0, 0x1f);
3221 #endif
3222 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
3223 t1 = tcg_temp_new();
3224 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
3225 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
3226 tcg_temp_free(t1);
3227 tcg_temp_free(t0);
3228 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
3229 if (unlikely(Rc(ctx->opcode) != 0)) {
3230 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
3231 }
3232 }
3233
3234 /* sraw & sraw. */
3235 static void gen_sraw(DisasContext *ctx)
3236 {
3237 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
3238 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
3239 if (unlikely(Rc(ctx->opcode) != 0)) {
3240 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
3241 }
3242 }
3243
3244 /* srawi & srawi. */
3245 static void gen_srawi(DisasContext *ctx)
3246 {
3247 int sh = SH(ctx->opcode);
3248 TCGv dst = cpu_gpr[rA(ctx->opcode)];
3249 TCGv src = cpu_gpr[rS(ctx->opcode)];
3250 if (sh == 0) {
3251 tcg_gen_ext32s_tl(dst, src);
3252 tcg_gen_movi_tl(cpu_ca, 0);
3253 if (is_isa300(ctx)) {
3254 tcg_gen_movi_tl(cpu_ca32, 0);
3255 }
3256 } else {
3257 TCGv t0;
3258 tcg_gen_ext32s_tl(dst, src);
3259 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
3260 t0 = tcg_temp_new();
3261 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
3262 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
3263 tcg_temp_free(t0);
3264 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
3265 if (is_isa300(ctx)) {
3266 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
3267 }
3268 tcg_gen_sari_tl(dst, dst, sh);
3269 }
3270 if (unlikely(Rc(ctx->opcode) != 0)) {
3271 gen_set_Rc0(ctx, dst);
3272 }
3273 }
3274
3275 /* srw & srw. */
3276 static void gen_srw(DisasContext *ctx)
3277 {
3278 TCGv t0, t1;
3279
3280 t0 = tcg_temp_new();
3281 /* AND rS with a mask that is 0 when rB >= 0x20 */
3282 #if defined(TARGET_PPC64)
3283 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
3284 tcg_gen_sari_tl(t0, t0, 0x3f);
3285 #else
3286 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
3287 tcg_gen_sari_tl(t0, t0, 0x1f);
3288 #endif
3289 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
3290 tcg_gen_ext32u_tl(t0, t0);
3291 t1 = tcg_temp_new();
3292 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
3293 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
3294 tcg_temp_free(t1);
3295 tcg_temp_free(t0);
3296 if (unlikely(Rc(ctx->opcode) != 0)) {
3297 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
3298 }
3299 }
3300
3301 #if defined(TARGET_PPC64)
3302 /* sld & sld. */
3303 static void gen_sld(DisasContext *ctx)
3304 {
3305 TCGv t0, t1;
3306
3307 t0 = tcg_temp_new();
3308 /* AND rS with a mask that is 0 when rB >= 0x40 */
3309 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
3310 tcg_gen_sari_tl(t0, t0, 0x3f);
3311 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
3312 t1 = tcg_temp_new();
3313 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
3314 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
3315 tcg_temp_free(t1);
3316 tcg_temp_free(t0);
3317 if (unlikely(Rc(ctx->opcode) != 0)) {
3318 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
3319 }
3320 }
3321
3322 /* srad & srad. */
3323 static void gen_srad(DisasContext *ctx)
3324 {
3325 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
3326 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
3327 if (unlikely(Rc(ctx->opcode) != 0)) {
3328 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
3329 }
3330 }
3331 /* sradi & sradi. */
3332 static inline void gen_sradi(DisasContext *ctx, int n)
3333 {
3334 int sh = SH(ctx->opcode) + (n << 5);
3335 TCGv dst = cpu_gpr[rA(ctx->opcode)];
3336 TCGv src = cpu_gpr[rS(ctx->opcode)];
3337 if (sh == 0) {
3338 tcg_gen_mov_tl(dst, src);
3339 tcg_gen_movi_tl(cpu_ca, 0);
3340 if (is_isa300(ctx)) {
3341 tcg_gen_movi_tl(cpu_ca32, 0);
3342 }
3343 } else {
3344 TCGv t0;
3345 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
3346 t0 = tcg_temp_new();
3347 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
3348 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
3349 tcg_temp_free(t0);
3350 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
3351 if (is_isa300(ctx)) {
3352 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
3353 }
3354 tcg_gen_sari_tl(dst, src, sh);
3355 }
3356 if (unlikely(Rc(ctx->opcode) != 0)) {
3357 gen_set_Rc0(ctx, dst);
3358 }
3359 }
3360
3361 static void gen_sradi0(DisasContext *ctx)
3362 {
3363 gen_sradi(ctx, 0);
3364 }
3365
3366 static void gen_sradi1(DisasContext *ctx)
3367 {
3368 gen_sradi(ctx, 1);
3369 }
3370
3371 /* extswsli & extswsli. */
3372 static inline void gen_extswsli(DisasContext *ctx, int n)
3373 {
3374 int sh = SH(ctx->opcode) + (n << 5);
3375 TCGv dst = cpu_gpr[rA(ctx->opcode)];
3376 TCGv src = cpu_gpr[rS(ctx->opcode)];
3377
3378 tcg_gen_ext32s_tl(dst, src);
3379 tcg_gen_shli_tl(dst, dst, sh);
3380 if (unlikely(Rc(ctx->opcode) != 0)) {
3381 gen_set_Rc0(ctx, dst);
3382 }
3383 }
3384
3385 static void gen_extswsli0(DisasContext *ctx)
3386 {
3387 gen_extswsli(ctx, 0);
3388 }
3389
3390 static void gen_extswsli1(DisasContext *ctx)
3391 {
3392 gen_extswsli(ctx, 1);
3393 }
3394
3395 /* srd & srd. */
3396 static void gen_srd(DisasContext *ctx)
3397 {
3398 TCGv t0, t1;
3399
3400 t0 = tcg_temp_new();
3401 /* AND rS with a mask that is 0 when rB >= 0x40 */
3402 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
3403 tcg_gen_sari_tl(t0, t0, 0x3f);
3404 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
3405 t1 = tcg_temp_new();
3406 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
3407 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
3408 tcg_temp_free(t1);
3409 tcg_temp_free(t0);
3410 if (unlikely(Rc(ctx->opcode) != 0)) {
3411 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
3412 }
3413 }
3414 #endif
3415
3416 /*** Addressing modes ***/
3417 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
3418 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
3419 target_long maskl)
3420 {
3421 target_long simm = SIMM(ctx->opcode);
3422
3423 simm &= ~maskl;
3424 if (rA(ctx->opcode) == 0) {
3425 if (NARROW_MODE(ctx)) {
3426 simm = (uint32_t)simm;
3427 }
3428 tcg_gen_movi_tl(EA, simm);
3429 } else if (likely(simm != 0)) {
3430 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
3431 if (NARROW_MODE(ctx)) {
3432 tcg_gen_ext32u_tl(EA, EA);
3433 }
3434 } else {
3435 if (NARROW_MODE(ctx)) {
3436 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
3437 } else {
3438 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
3439 }
3440 }
3441 }
3442
3443 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
3444 {
3445 if (rA(ctx->opcode) == 0) {
3446 if (NARROW_MODE(ctx)) {
3447 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
3448 } else {
3449 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
3450 }
3451 } else {
3452 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
3453 if (NARROW_MODE(ctx)) {
3454 tcg_gen_ext32u_tl(EA, EA);
3455 }
3456 }
3457 }
3458
3459 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
3460 {
3461 if (rA(ctx->opcode) == 0) {
3462 tcg_gen_movi_tl(EA, 0);
3463 } else if (NARROW_MODE(ctx)) {
3464 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
3465 } else {
3466 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
3467 }
3468 }
3469
3470 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
3471 target_long val)
3472 {
3473 tcg_gen_addi_tl(ret, arg1, val);
3474 if (NARROW_MODE(ctx)) {
3475 tcg_gen_ext32u_tl(ret, ret);
3476 }
3477 }
3478
3479 static inline void gen_align_no_le(DisasContext *ctx)
3480 {
3481 gen_exception_err(ctx, POWERPC_EXCP_ALIGN,
3482 (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE);
3483 }
3484
3485 /*** Integer load ***/
3486 #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask)
3487 #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP))
3488
3489 #define GEN_QEMU_LOAD_TL(ldop, op) \
3490 static void glue(gen_qemu_, ldop)(DisasContext *ctx, \
3491 TCGv val, \
3492 TCGv addr) \
3493 { \
3494 tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \
3495 }
3496
3497 GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB))
3498 GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW))
3499 GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW))
3500 GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL))
3501 GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL))
3502
3503 GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW))
3504 GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL))
3505
3506 #define GEN_QEMU_LOAD_64(ldop, op) \
3507 static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \
3508 TCGv_i64 val, \
3509 TCGv addr) \
3510 { \
3511 tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \
3512 }
3513
3514 GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB))
3515 GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW))
3516 GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL))
3517 GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL))
3518 GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q))
3519
3520 #if defined(TARGET_PPC64)
3521 GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q))
3522 #endif
3523
3524 #define GEN_QEMU_STORE_TL(stop, op) \
3525 static void glue(gen_qemu_, stop)(DisasContext *ctx, \
3526 TCGv val, \
3527 TCGv addr) \
3528 { \
3529 tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \
3530 }
3531
3532 GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB))
3533 GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW))
3534 GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL))
3535
3536 GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW))
3537 GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL))
3538
3539 #define GEN_QEMU_STORE_64(stop, op) \
3540 static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \
3541 TCGv_i64 val, \
3542 TCGv addr) \
3543 { \
3544 tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \
3545 }
3546
3547 GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB))
3548 GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW))
3549 GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL))
3550 GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q))
3551
3552 #if defined(TARGET_PPC64)
3553 GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q))
3554 #endif
3555
3556 #define GEN_LD(name, ldop, opc, type) \
3557 static void glue(gen_, name)(DisasContext *ctx) \
3558 { \
3559 TCGv EA; \
3560 gen_set_access_type(ctx, ACCESS_INT); \
3561 EA = tcg_temp_new(); \
3562 gen_addr_imm_index(ctx, EA, 0); \
3563 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
3564 tcg_temp_free(EA); \
3565 }
3566
3567 #define GEN_LDU(name, ldop, opc, type) \
3568 static void glue(gen_, name##u)(DisasContext *ctx) \
3569 { \
3570 TCGv EA; \
3571 if (unlikely(rA(ctx->opcode) == 0 || \
3572 rA(ctx->opcode) == rD(ctx->opcode))) { \
3573 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3574 return; \
3575 } \
3576 gen_set_access_type(ctx, ACCESS_INT); \
3577 EA = tcg_temp_new(); \
3578 if (type == PPC_64B) \
3579 gen_addr_imm_index(ctx, EA, 0x03); \
3580 else \
3581 gen_addr_imm_index(ctx, EA, 0); \
3582 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
3583 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3584 tcg_temp_free(EA); \
3585 }
3586
3587 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
3588 static void glue(gen_, name##ux)(DisasContext *ctx) \
3589 { \
3590 TCGv EA; \
3591 if (unlikely(rA(ctx->opcode) == 0 || \
3592 rA(ctx->opcode) == rD(ctx->opcode))) { \
3593 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3594 return; \
3595 } \
3596 gen_set_access_type(ctx, ACCESS_INT); \
3597 EA = tcg_temp_new(); \
3598 gen_addr_reg_index(ctx, EA); \
3599 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
3600 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3601 tcg_temp_free(EA); \
3602 }
3603
3604 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
3605 static void glue(gen_, name##x)(DisasContext *ctx) \
3606 { \
3607 TCGv EA; \
3608 chk; \
3609 gen_set_access_type(ctx, ACCESS_INT); \
3610 EA = tcg_temp_new(); \
3611 gen_addr_reg_index(ctx, EA); \
3612 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
3613 tcg_temp_free(EA); \
3614 }
3615
3616 #define GEN_LDX(name, ldop, opc2, opc3, type) \
3617 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE)
3618
3619 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \
3620 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
3621
3622 #define GEN_LDS(name, ldop, op, type) \
3623 GEN_LD(name, ldop, op | 0x20, type); \
3624 GEN_LDU(name, ldop, op | 0x21, type); \
3625 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
3626 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
3627
3628 /* lbz lbzu lbzux lbzx */
3629 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
3630 /* lha lhau lhaux lhax */
3631 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
3632 /* lhz lhzu lhzux lhzx */
3633 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
3634 /* lwz lwzu lwzux lwzx */
3635 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
3636
3637 #define GEN_LDEPX(name, ldop, opc2, opc3) \
3638 static void glue(gen_, name##epx)(DisasContext *ctx) \
3639 { \
3640 TCGv EA; \
3641 CHK_SV; \
3642 gen_set_access_type(ctx, ACCESS_INT); \
3643 EA = tcg_temp_new(); \
3644 gen_addr_reg_index(ctx, EA); \
3645 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\
3646 tcg_temp_free(EA); \
3647 }
3648
3649 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02)
3650 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08)
3651 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00)
3652 #if defined(TARGET_PPC64)
3653 GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00)
3654 #endif
3655
3656 #if defined(TARGET_PPC64)
3657 /* lwaux */
3658 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
3659 /* lwax */
3660 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
3661 /* ldux */
3662 GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B);
3663 /* ldx */
3664 GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B);
3665
3666 /* CI load/store variants */
3667 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
3668 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST)
3669 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
3670 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
3671
3672 static void gen_ld(DisasContext *ctx)
3673 {
3674 TCGv EA;
3675 if (Rc(ctx->opcode)) {
3676 if (unlikely(rA(ctx->opcode) == 0 ||
3677 rA(ctx->opcode) == rD(ctx->opcode))) {
3678 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3679 return;
3680 }
3681 }
3682 gen_set_access_type(ctx, ACCESS_INT);
3683 EA = tcg_temp_new();
3684 gen_addr_imm_index(ctx, EA, 0x03);
3685 if (ctx->opcode & 0x02) {
3686 /* lwa (lwau is undefined) */
3687 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
3688 } else {
3689 /* ld - ldu */
3690 gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
3691 }
3692 if (Rc(ctx->opcode)) {
3693 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3694 }
3695 tcg_temp_free(EA);
3696 }
3697
3698 /* lq */
3699 static void gen_lq(DisasContext *ctx)
3700 {
3701 int ra, rd;
3702 TCGv EA, hi, lo;
3703
3704 /* lq is a legal user mode instruction starting in ISA 2.07 */
3705 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3706 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3707
3708 if (!legal_in_user_mode && ctx->pr) {
3709 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3710 return;
3711 }
3712
3713 if (!le_is_supported && ctx->le_mode) {
3714 gen_align_no_le(ctx);
3715 return;
3716 }
3717 ra = rA(ctx->opcode);
3718 rd = rD(ctx->opcode);
3719 if (unlikely((rd & 1) || rd == ra)) {
3720 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3721 return;
3722 }
3723
3724 gen_set_access_type(ctx, ACCESS_INT);
3725 EA = tcg_temp_new();
3726 gen_addr_imm_index(ctx, EA, 0x0F);
3727
3728 /* Note that the low part is always in RD+1, even in LE mode. */
3729 lo = cpu_gpr[rd + 1];
3730 hi = cpu_gpr[rd];
3731
3732 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3733 if (HAVE_ATOMIC128) {
3734 TCGv_i32 oi = tcg_temp_new_i32();
3735 if (ctx->le_mode) {
3736 tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx));
3737 gen_helper_lq_le_parallel(lo, cpu_env, EA, oi);
3738 } else {
3739 tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx));
3740 gen_helper_lq_be_parallel(lo, cpu_env, EA, oi);
3741 }
3742 tcg_temp_free_i32(oi);
3743 tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh));
3744 } else {
3745 /* Restart with exclusive lock. */
3746 gen_helper_exit_atomic(cpu_env);
3747 ctx->base.is_jmp = DISAS_NORETURN;
3748 }
3749 } else if (ctx->le_mode) {
3750 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ);
3751 gen_addr_add(ctx, EA, EA, 8);
3752 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ);
3753 } else {
3754 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ);
3755 gen_addr_add(ctx, EA, EA, 8);
3756 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ);
3757 }
3758 tcg_temp_free(EA);
3759 }
3760 #endif
3761
3762 /*** Integer store ***/
3763 #define GEN_ST(name, stop, opc, type) \
3764 static void glue(gen_, name)(DisasContext *ctx) \
3765 { \
3766 TCGv EA; \
3767 gen_set_access_type(ctx, ACCESS_INT); \
3768 EA = tcg_temp_new(); \
3769 gen_addr_imm_index(ctx, EA, 0); \
3770 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3771 tcg_temp_free(EA); \
3772 }
3773
3774 #define GEN_STU(name, stop, opc, type) \
3775 static void glue(gen_, stop##u)(DisasContext *ctx) \
3776 { \
3777 TCGv EA; \
3778 if (unlikely(rA(ctx->opcode) == 0)) { \
3779 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3780 return; \
3781 } \
3782 gen_set_access_type(ctx, ACCESS_INT); \
3783 EA = tcg_temp_new(); \
3784 if (type == PPC_64B) \
3785 gen_addr_imm_index(ctx, EA, 0x03); \
3786 else \
3787 gen_addr_imm_index(ctx, EA, 0); \
3788 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3789 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3790 tcg_temp_free(EA); \
3791 }
3792
3793 #define GEN_STUX(name, stop, opc2, opc3, type) \
3794 static void glue(gen_, name##ux)(DisasContext *ctx) \
3795 { \
3796 TCGv EA; \
3797 if (unlikely(rA(ctx->opcode) == 0)) { \
3798 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3799 return; \
3800 } \
3801 gen_set_access_type(ctx, ACCESS_INT); \
3802 EA = tcg_temp_new(); \
3803 gen_addr_reg_index(ctx, EA); \
3804 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3805 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3806 tcg_temp_free(EA); \
3807 }
3808
3809 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
3810 static void glue(gen_, name##x)(DisasContext *ctx) \
3811 { \
3812 TCGv EA; \
3813 chk; \
3814 gen_set_access_type(ctx, ACCESS_INT); \
3815 EA = tcg_temp_new(); \
3816 gen_addr_reg_index(ctx, EA); \
3817 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3818 tcg_temp_free(EA); \
3819 }
3820 #define GEN_STX(name, stop, opc2, opc3, type) \
3821 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE)
3822
3823 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \
3824 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
3825
3826 #define GEN_STS(name, stop, op, type) \
3827 GEN_ST(name, stop, op | 0x20, type); \
3828 GEN_STU(name, stop, op | 0x21, type); \
3829 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
3830 GEN_STX(name, stop, 0x17, op | 0x00, type)
3831
3832 /* stb stbu stbux stbx */
3833 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
3834 /* sth sthu sthux sthx */
3835 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
3836 /* stw stwu stwux stwx */
3837 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
3838
3839 #define GEN_STEPX(name, stop, opc2, opc3) \
3840 static void glue(gen_, name##epx)(DisasContext *ctx) \
3841 { \
3842 TCGv EA; \
3843 CHK_SV; \
3844 gen_set_access_type(ctx, ACCESS_INT); \
3845 EA = tcg_temp_new(); \
3846 gen_addr_reg_index(ctx, EA); \
3847 tcg_gen_qemu_st_tl( \
3848 cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \
3849 tcg_temp_free(EA); \
3850 }
3851
3852 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06)
3853 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C)
3854 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04)
3855 #if defined(TARGET_PPC64)
3856 GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1d, 0x04)
3857 #endif
3858
3859 #if defined(TARGET_PPC64)
3860 GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B);
3861 GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B);
3862 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
3863 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
3864 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
3865 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
3866
3867 static void gen_std(DisasContext *ctx)
3868 {
3869 int rs;
3870 TCGv EA;
3871
3872 rs = rS(ctx->opcode);
3873 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
3874 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3875 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3876 TCGv hi, lo;
3877
3878 if (!(ctx->insns_flags & PPC_64BX)) {
3879 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3880 }
3881
3882 if (!legal_in_user_mode && ctx->pr) {
3883 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3884 return;
3885 }
3886
3887 if (!le_is_supported && ctx->le_mode) {
3888 gen_align_no_le(ctx);
3889 return;
3890 }
3891
3892 if (unlikely(rs & 1)) {
3893 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3894 return;
3895 }
3896 gen_set_access_type(ctx, ACCESS_INT);
3897 EA = tcg_temp_new();
3898 gen_addr_imm_index(ctx, EA, 0x03);
3899
3900 /* Note that the low part is always in RS+1, even in LE mode. */
3901 lo = cpu_gpr[rs + 1];
3902 hi = cpu_gpr[rs];
3903
3904 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3905 if (HAVE_ATOMIC128) {
3906 TCGv_i32 oi = tcg_temp_new_i32();
3907 if (ctx->le_mode) {
3908 tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx));
3909 gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi);
3910 } else {
3911 tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx));
3912 gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi);
3913 }
3914 tcg_temp_free_i32(oi);
3915 } else {
3916 /* Restart with exclusive lock. */
3917 gen_helper_exit_atomic(cpu_env);
3918 ctx->base.is_jmp = DISAS_NORETURN;
3919 }
3920 } else if (ctx->le_mode) {
3921 tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_LEQ);
3922 gen_addr_add(ctx, EA, EA, 8);
3923 tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_LEQ);
3924 } else {
3925 tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_BEQ);
3926 gen_addr_add(ctx, EA, EA, 8);
3927 tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_BEQ);
3928 }
3929 tcg_temp_free(EA);
3930 } else {
3931 /* std / stdu */
3932 if (Rc(ctx->opcode)) {
3933 if (unlikely(rA(ctx->opcode) == 0)) {
3934 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3935 return;
3936 }
3937 }
3938 gen_set_access_type(ctx, ACCESS_INT);
3939 EA = tcg_temp_new();
3940 gen_addr_imm_index(ctx, EA, 0x03);
3941 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA);
3942 if (Rc(ctx->opcode)) {
3943 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3944 }
3945 tcg_temp_free(EA);
3946 }
3947 }
3948 #endif
3949 /*** Integer load and store with byte reverse ***/
3950
3951 /* lhbrx */
3952 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
3953
3954 /* lwbrx */
3955 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
3956
3957 #if defined(TARGET_PPC64)
3958 /* ldbrx */
3959 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE);
3960 /* stdbrx */
3961 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE);
3962 #endif /* TARGET_PPC64 */
3963
3964 /* sthbrx */
3965 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
3966 /* stwbrx */
3967 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
3968
3969 /*** Integer load and store multiple ***/
3970
3971 /* lmw */
3972 static void gen_lmw(DisasContext *ctx)
3973 {
3974 TCGv t0;
3975 TCGv_i32 t1;
3976
3977 if (ctx->le_mode) {
3978 gen_align_no_le(ctx);
3979 return;
3980 }
3981 gen_set_access_type(ctx, ACCESS_INT);
3982 t0 = tcg_temp_new();
3983 t1 = tcg_const_i32(rD(ctx->opcode));
3984 gen_addr_imm_index(ctx, t0, 0);
3985 gen_helper_lmw(cpu_env, t0, t1);
3986 tcg_temp_free(t0);
3987 tcg_temp_free_i32(t1);
3988 }
3989
3990 /* stmw */
3991 static void gen_stmw(DisasContext *ctx)
3992 {
3993 TCGv t0;
3994 TCGv_i32 t1;
3995
3996 if (ctx->le_mode) {
3997 gen_align_no_le(ctx);
3998 return;
3999 }
4000 gen_set_access_type(ctx, ACCESS_INT);
4001 t0 = tcg_temp_new();
4002 t1 = tcg_const_i32(rS(ctx->opcode));
4003 gen_addr_imm_index(ctx, t0, 0);
4004 gen_helper_stmw(cpu_env, t0, t1);
4005 tcg_temp_free(t0);
4006 tcg_temp_free_i32(t1);
4007 }
4008
4009 /*** Integer load and store strings ***/
4010
4011 /* lswi */
4012 /*
4013 * PowerPC32 specification says we must generate an exception if rA is
4014 * in the range of registers to be loaded. In an other hand, IBM says
4015 * this is valid, but rA won't be loaded. For now, I'll follow the
4016 * spec...
4017 */
4018 static void gen_lswi(DisasContext *ctx)
4019 {
4020 TCGv t0;
4021 TCGv_i32 t1, t2;
4022 int nb = NB(ctx->opcode);
4023 int start = rD(ctx->opcode);
4024 int ra = rA(ctx->opcode);
4025 int nr;
4026
4027 if (ctx->le_mode) {
4028 gen_align_no_le(ctx);
4029 return;
4030 }
4031 if (nb == 0) {
4032 nb = 32;
4033 }
4034 nr = DIV_ROUND_UP(nb, 4);
4035 if (unlikely(lsw_reg_in_range(start, nr, ra))) {
4036 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4037 return;
4038 }
4039 gen_set_access_type(ctx, ACCESS_INT);
4040 t0 = tcg_temp_new();
4041 gen_addr_register(ctx, t0);
4042 t1 = tcg_const_i32(nb);
4043 t2 = tcg_const_i32(start);
4044 gen_helper_lsw(cpu_env, t0, t1, t2);
4045 tcg_temp_free(t0);
4046 tcg_temp_free_i32(t1);
4047 tcg_temp_free_i32(t2);
4048 }
4049
4050 /* lswx */
4051 static void gen_lswx(DisasContext *ctx)
4052 {
4053 TCGv t0;
4054 TCGv_i32 t1, t2, t3;
4055
4056 if (ctx->le_mode) {
4057 gen_align_no_le(ctx);
4058 return;
4059 }
4060 gen_set_access_type(ctx, ACCESS_INT);
4061 t0 = tcg_temp_new();
4062 gen_addr_reg_index(ctx, t0);
4063 t1 = tcg_const_i32(rD(ctx->opcode));
4064 t2 = tcg_const_i32(rA(ctx->opcode));
4065 t3 = tcg_const_i32(rB(ctx->opcode));
4066 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
4067 tcg_temp_free(t0);
4068 tcg_temp_free_i32(t1);
4069 tcg_temp_free_i32(t2);
4070 tcg_temp_free_i32(t3);
4071 }
4072
4073 /* stswi */
4074 static void gen_stswi(DisasContext *ctx)
4075 {
4076 TCGv t0;
4077 TCGv_i32 t1, t2;
4078 int nb = NB(ctx->opcode);
4079
4080 if (ctx->le_mode) {
4081 gen_align_no_le(ctx);
4082 return;
4083 }
4084 gen_set_access_type(ctx, ACCESS_INT);
4085 t0 = tcg_temp_new();
4086 gen_addr_register(ctx, t0);
4087 if (nb == 0) {
4088 nb = 32;
4089 }
4090 t1 = tcg_const_i32(nb);
4091 t2 = tcg_const_i32(rS(ctx->opcode));
4092 gen_helper_stsw(cpu_env, t0, t1, t2);
4093 tcg_temp_free(t0);
4094 tcg_temp_free_i32(t1);
4095 tcg_temp_free_i32(t2);
4096 }
4097
4098 /* stswx */
4099 static void gen_stswx(DisasContext *ctx)
4100 {
4101 TCGv t0;
4102 TCGv_i32 t1, t2;
4103
4104 if (ctx->le_mode) {
4105 gen_align_no_le(ctx);
4106 return;
4107 }
4108 gen_set_access_type(ctx, ACCESS_INT);
4109 t0 = tcg_temp_new();
4110 gen_addr_reg_index(ctx, t0);
4111 t1 = tcg_temp_new_i32();
4112 tcg_gen_trunc_tl_i32(t1, cpu_xer);
4113 tcg_gen_andi_i32(t1, t1, 0x7F);
4114 t2 = tcg_const_i32(rS(ctx->opcode));
4115 gen_helper_stsw(cpu_env, t0, t1, t2);
4116 tcg_temp_free(t0);
4117 tcg_temp_free_i32(t1);
4118 tcg_temp_free_i32(t2);
4119 }
4120
4121 /*** Memory synchronisation ***/
4122 /* eieio */
4123 static void gen_eieio(DisasContext *ctx)
4124 {
4125 TCGBar bar = TCG_MO_LD_ST;
4126
4127 /*
4128 * POWER9 has a eieio instruction variant using bit 6 as a hint to
4129 * tell the CPU it is a store-forwarding barrier.
4130 */
4131 if (ctx->opcode & 0x2000000) {
4132 /*
4133 * ISA says that "Reserved fields in instructions are ignored
4134 * by the processor". So ignore the bit 6 on non-POWER9 CPU but
4135 * as this is not an instruction software should be using,
4136 * complain to the user.
4137 */
4138 if (!(ctx->insns_flags2 & PPC2_ISA300)) {
4139 qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @"
4140 TARGET_FMT_lx "\n", ctx->base.pc_next - 4);
4141 } else {
4142 bar = TCG_MO_ST_LD;
4143 }
4144 }
4145
4146 tcg_gen_mb(bar | TCG_BAR_SC);
4147 }
4148
4149 #if !defined(CONFIG_USER_ONLY)
4150 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global)
4151 {
4152 TCGv_i32 t;
4153 TCGLabel *l;
4154
4155 if (!ctx->lazy_tlb_flush) {
4156 return;
4157 }
4158 l = gen_new_label();
4159 t = tcg_temp_new_i32();
4160 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
4161 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l);
4162 if (global) {
4163 gen_helper_check_tlb_flush_global(cpu_env);
4164 } else {
4165 gen_helper_check_tlb_flush_local(cpu_env);
4166 }
4167 gen_set_label(l);
4168 tcg_temp_free_i32(t);
4169 }
4170 #else
4171 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { }
4172 #endif
4173
4174 /* isync */
4175 static void gen_isync(DisasContext *ctx)
4176 {
4177 /*
4178 * We need to check for a pending TLB flush. This can only happen in
4179 * kernel mode however so check MSR_PR
4180 */
4181 if (!ctx->pr) {
4182 gen_check_tlb_flush(ctx, false);
4183 }
4184 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
4185 gen_stop_exception(ctx);
4186 }
4187
4188 #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE))
4189
4190 static void gen_load_locked(DisasContext *ctx, MemOp memop)
4191 {
4192 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
4193 TCGv t0 = tcg_temp_new();
4194
4195 gen_set_access_type(ctx, ACCESS_RES);
4196 gen_addr_reg_index(ctx, t0);
4197 tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN);
4198 tcg_gen_mov_tl(cpu_reserve, t0);
4199 tcg_gen_mov_tl(cpu_reserve_val, gpr);
4200 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
4201 tcg_temp_free(t0);
4202 }
4203
4204 #define LARX(name, memop) \
4205 static void gen_##name(DisasContext *ctx) \
4206 { \
4207 gen_load_locked(ctx, memop); \
4208 }
4209
4210 /* lwarx */
4211 LARX(lbarx, DEF_MEMOP(MO_UB))
4212 LARX(lharx, DEF_MEMOP(MO_UW))
4213 LARX(lwarx, DEF_MEMOP(MO_UL))
4214
4215 static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop,
4216 TCGv EA, TCGCond cond, int addend)
4217 {
4218 TCGv t = tcg_temp_new();
4219 TCGv t2 = tcg_temp_new();
4220 TCGv u = tcg_temp_new();
4221
4222 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop);
4223 tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop));
4224 tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop);
4225 tcg_gen_addi_tl(u, t, addend);
4226
4227 /* E.g. for fetch and increment bounded... */
4228 /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */
4229 tcg_gen_movcond_tl(cond, u, t, t2, u, t);
4230 tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop);
4231
4232 /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */
4233 tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1));
4234 tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u);
4235
4236 tcg_temp_free(t);
4237 tcg_temp_free(t2);
4238 tcg_temp_free(u);
4239 }
4240
4241 static void gen_ld_atomic(DisasContext *ctx, MemOp memop)
4242 {
4243 uint32_t gpr_FC = FC(ctx->opcode);
4244 TCGv EA = tcg_temp_new();
4245 int rt = rD(ctx->opcode);
4246 bool need_serial;
4247 TCGv src, dst;
4248
4249 gen_addr_register(ctx, EA);
4250 dst = cpu_gpr[rt];
4251 src = cpu_gpr[(rt + 1) & 31];
4252
4253 need_serial = false;
4254 memop |= MO_ALIGN;
4255 switch (gpr_FC) {
4256 case 0: /* Fetch and add */
4257 tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop);
4258 break;
4259 case 1: /* Fetch and xor */
4260 tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop);
4261 break;
4262 case 2: /* Fetch and or */
4263 tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop);
4264 break;
4265 case 3: /* Fetch and 'and' */
4266 tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop);
4267 break;
4268 case 4: /* Fetch and max unsigned */
4269 tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop);
4270 break;
4271 case 5: /* Fetch and max signed */
4272 tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop);
4273 break;
4274 case 6: /* Fetch and min unsigned */
4275 tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop);
4276 break;
4277 case 7: /* Fetch and min signed */
4278 tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop);
4279 break;
4280 case 8: /* Swap */
4281 tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop);
4282 break;
4283
4284 case 16: /* Compare and swap not equal */
4285 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
4286 need_serial = true;
4287 } else {
4288 TCGv t0 = tcg_temp_new();
4289 TCGv t1 = tcg_temp_new();
4290
4291 tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop);
4292 if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) {
4293 tcg_gen_mov_tl(t1, src);
4294 } else {
4295 tcg_gen_ext32u_tl(t1, src);
4296 }
4297 tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1,
4298 cpu_gpr[(rt + 2) & 31], t0);
4299 tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop);
4300 tcg_gen_mov_tl(dst, t0);
4301
4302 tcg_temp_free(t0);
4303 tcg_temp_free(t1);
4304 }
4305 break;
4306
4307 case 24: /* Fetch and increment bounded */
4308 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
4309 need_serial = true;
4310 } else {
4311 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1);
4312 }
4313 break;
4314 case 25: /* Fetch and increment equal */
4315 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
4316 need_serial = true;
4317 } else {
4318 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1);
4319 }
4320 break;
4321 case 28: /* Fetch and decrement bounded */
4322 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
4323 need_serial = true;
4324 } else {
4325 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1);
4326 }
4327 break;
4328
4329 default:
4330 /* invoke data storage error handler */
4331 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL);
4332 }
4333 tcg_temp_free(EA);
4334
4335 if (need_serial) {
4336 /* Restart with exclusive lock. */
4337 gen_helper_exit_atomic(cpu_env);
4338 ctx->base.is_jmp = DISAS_NORETURN;
4339 }
4340 }
4341
4342 static void gen_lwat(DisasContext *ctx)
4343 {
4344 gen_ld_atomic(ctx, DEF_MEMOP(MO_UL));
4345 }
4346
4347 #ifdef TARGET_PPC64
4348 static void gen_ldat(DisasContext *ctx)
4349 {
4350 gen_ld_atomic(ctx, DEF_MEMOP(MO_Q));
4351 }
4352 #endif
4353
4354 static void gen_st_atomic(DisasContext *ctx, MemOp memop)
4355 {
4356 uint32_t gpr_FC = FC(ctx->opcode);
4357 TCGv EA = tcg_temp_new();
4358 TCGv src, discard;
4359
4360 gen_addr_register(ctx, EA);
4361 src = cpu_gpr[rD(ctx->opcode)];
4362 discard = tcg_temp_new();
4363
4364 memop |= MO_ALIGN;
4365 switch (gpr_FC) {
4366 case 0: /* add and Store */
4367 tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
4368 break;
4369 case 1: /* xor and Store */
4370 tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
4371 break;
4372 case 2: /* Or and Store */
4373 tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
4374 break;
4375 case 3: /* 'and' and Store */
4376 tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
4377 break;
4378 case 4: /* Store max unsigned */
4379 tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
4380 break;
4381 case 5: /* Store max signed */
4382 tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
4383 break;
4384 case 6: /* Store min unsigned */
4385 tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
4386 break;
4387 case 7: /* Store min signed */
4388 tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
4389 break;
4390 case 24: /* Store twin */
4391 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
4392 /* Restart with exclusive lock. */
4393 gen_helper_exit_atomic(cpu_env);
4394 ctx->base.is_jmp = DISAS_NORETURN;
4395 } else {
4396 TCGv t = tcg_temp_new();
4397 TCGv t2 = tcg_temp_new();
4398 TCGv s = tcg_temp_new();
4399 TCGv s2 = tcg_temp_new();
4400 TCGv ea_plus_s = tcg_temp_new();
4401
4402 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop);
4403 tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop));
4404 tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop);
4405 tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t);
4406 tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2);
4407 tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop);
4408 tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop);
4409
4410 tcg_temp_free(ea_plus_s);
4411 tcg_temp_free(s2);
4412 tcg_temp_free(s);
4413 tcg_temp_free(t2);
4414 tcg_temp_free(t);
4415 }
4416 break;
4417 default:
4418 /* invoke data storage error handler */
4419 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL);
4420 }
4421 tcg_temp_free(discard);
4422 tcg_temp_free(EA);
4423 }
4424
4425 static void gen_stwat(DisasContext *ctx)
4426 {
4427 gen_st_atomic(ctx, DEF_MEMOP(MO_UL));
4428 }
4429
4430 #ifdef TARGET_PPC64
4431 static void gen_stdat(DisasContext *ctx)
4432 {
4433 gen_st_atomic(ctx, DEF_MEMOP(MO_Q));
4434 }
4435 #endif
4436
4437 static void gen_conditional_store(DisasContext *ctx, MemOp memop)
4438 {
4439 TCGLabel *l1 = gen_new_label();
4440 TCGLabel *l2 = gen_new_label();
4441 TCGv t0 = tcg_temp_new();
4442 int reg = rS(ctx->opcode);
4443
4444 gen_set_access_type(ctx, ACCESS_RES);
4445 gen_addr_reg_index(ctx, t0);
4446 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
4447 tcg_temp_free(t0);
4448
4449 t0 = tcg_temp_new();
4450 tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val,
4451 cpu_gpr[reg], ctx->mem_idx,
4452 DEF_MEMOP(memop) | MO_ALIGN);
4453 tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val);
4454 tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT);
4455 tcg_gen_or_tl(t0, t0, cpu_so);
4456 tcg_gen_trunc_tl_i32(cpu_crf[0], t0);
4457 tcg_temp_free(t0);
4458 tcg_gen_br(l2);
4459
4460 gen_set_label(l1);
4461
4462 /*
4463 * Address mismatch implies failure. But we still need to provide
4464 * the memory barrier semantics of the instruction.
4465 */
4466 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
4467 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
4468
4469 gen_set_label(l2);
4470 tcg_gen_movi_tl(cpu_reserve, -1);
4471 }
4472
4473 #define STCX(name, memop) \
4474 static void gen_##name(DisasContext *ctx) \
4475 { \
4476 gen_conditional_store(ctx, memop); \
4477 }
4478
4479 STCX(stbcx_, DEF_MEMOP(MO_UB))
4480 STCX(sthcx_, DEF_MEMOP(MO_UW))
4481 STCX(stwcx_, DEF_MEMOP(MO_UL))
4482
4483 #if defined(TARGET_PPC64)
4484 /* ldarx */
4485 LARX(ldarx, DEF_MEMOP(MO_Q))
4486 /* stdcx. */
4487 STCX(stdcx_, DEF_MEMOP(MO_Q))
4488
4489 /* lqarx */
4490 static void gen_lqarx(DisasContext *ctx)
4491 {
4492 int rd = rD(ctx->opcode);
4493 TCGv EA, hi, lo;
4494
4495 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
4496 (rd == rB(ctx->opcode)))) {
4497 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4498 return;
4499 }
4500
4501 gen_set_access_type(ctx, ACCESS_RES);
4502 EA = tcg_temp_new();
4503 gen_addr_reg_index(ctx, EA);
4504
4505 /* Note that the low part is always in RD+1, even in LE mode. */
4506 lo = cpu_gpr[rd + 1];
4507 hi = cpu_gpr[rd];
4508
4509 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
4510 if (HAVE_ATOMIC128) {
4511 TCGv_i32 oi = tcg_temp_new_i32();
4512 if (ctx->le_mode) {
4513 tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ | MO_ALIGN_16,
4514 ctx->mem_idx));
4515 gen_helper_lq_le_parallel(lo, cpu_env, EA, oi);
4516 } else {
4517 tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ | MO_ALIGN_16,
4518 ctx->mem_idx));
4519 gen_helper_lq_be_parallel(lo, cpu_env, EA, oi);
4520 }
4521 tcg_temp_free_i32(oi);
4522 tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh));
4523 } else {
4524 /* Restart with exclusive lock. */
4525 gen_helper_exit_atomic(cpu_env);
4526 ctx->base.is_jmp = DISAS_NORETURN;
4527 tcg_temp_free(EA);
4528 return;
4529 }
4530 } else if (ctx->le_mode) {
4531 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ | MO_ALIGN_16);
4532 tcg_gen_mov_tl(cpu_reserve, EA);
4533 gen_addr_add(ctx, EA, EA, 8);
4534 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ);
4535 } else {
4536 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ | MO_ALIGN_16);
4537 tcg_gen_mov_tl(cpu_reserve, EA);
4538 gen_addr_add(ctx, EA, EA, 8);
4539 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ);
4540 }
4541 tcg_temp_free(EA);
4542
4543 tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val));
4544 tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2));
4545 }
4546
4547 /* stqcx. */
4548 static void gen_stqcx_(DisasContext *ctx)
4549 {
4550 int rs = rS(ctx->opcode);
4551 TCGv EA, hi, lo;
4552
4553 if (unlikely(rs & 1)) {
4554 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4555 return;
4556 }
4557
4558 gen_set_access_type(ctx, ACCESS_RES);
4559 EA = tcg_temp_new();
4560 gen_addr_reg_index(ctx, EA);
4561
4562 /* Note that the low part is always in RS+1, even in LE mode. */
4563 lo = cpu_gpr[rs + 1];
4564 hi = cpu_gpr[rs];
4565
4566 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
4567 if (HAVE_CMPXCHG128) {
4568 TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_Q) | MO_ALIGN_16);
4569 if (ctx->le_mode) {
4570 gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env,
4571 EA, lo, hi, oi);
4572 } else {
4573 gen_helper_stqcx_be_parallel(cpu_crf[0], cpu_env,
4574 EA, lo, hi, oi);
4575 }
4576 tcg_temp_free_i32(oi);
4577 } else {
4578 /* Restart with exclusive lock. */
4579 gen_helper_exit_atomic(cpu_env);
4580 ctx->base.is_jmp = DISAS_NORETURN;
4581 }
4582 tcg_temp_free(EA);
4583 } else {
4584 TCGLabel *lab_fail = gen_new_label();
4585 TCGLabel *lab_over = gen_new_label();
4586 TCGv_i64 t0 = tcg_temp_new_i64();
4587 TCGv_i64 t1 = tcg_temp_new_i64();
4588
4589 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail);
4590 tcg_temp_free(EA);
4591
4592 gen_qemu_ld64_i64(ctx, t0, cpu_reserve);
4593 tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode
4594 ? offsetof(CPUPPCState, reserve_val2)
4595 : offsetof(CPUPPCState, reserve_val)));
4596 tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail);
4597
4598 tcg_gen_addi_i64(t0, cpu_reserve, 8);
4599 gen_qemu_ld64_i64(ctx, t0, t0);
4600 tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode
4601 ? offsetof(CPUPPCState, reserve_val)
4602 : offsetof(CPUPPCState, reserve_val2)));
4603 tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail);
4604
4605 /* Success */
4606 gen_qemu_st64_i64(ctx, ctx->le_mode ? lo : hi, cpu_reserve);
4607 tcg_gen_addi_i64(t0, cpu_reserve, 8);
4608 gen_qemu_st64_i64(ctx, ctx->le_mode ? hi : lo, t0);
4609
4610 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
4611 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
4612 tcg_gen_br(lab_over);
4613
4614 gen_set_label(lab_fail);
4615 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
4616
4617 gen_set_label(lab_over);
4618 tcg_gen_movi_tl(cpu_reserve, -1);
4619 tcg_temp_free_i64(t0);
4620 tcg_temp_free_i64(t1);
4621 }
4622 }
4623 #endif /* defined(TARGET_PPC64) */
4624
4625 /* sync */
4626 static void gen_sync(DisasContext *ctx)
4627 {
4628 uint32_t l = (ctx->opcode >> 21) & 3;
4629
4630 /*
4631 * We may need to check for a pending TLB flush.
4632 *
4633 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
4634 *
4635 * Additionally, this can only happen in kernel mode however so
4636 * check MSR_PR as well.
4637 */
4638 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) {
4639 gen_check_tlb_flush(ctx, true);
4640 }
4641 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
4642 }
4643
4644 /* wait */
4645 static void gen_wait(DisasContext *ctx)
4646 {
4647 TCGv_i32 t0 = tcg_const_i32(1);
4648 tcg_gen_st_i32(t0, cpu_env,
4649 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
4650 tcg_temp_free_i32(t0);
4651 /* Stop translation, as the CPU is supposed to sleep from now */
4652 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
4653 }
4654
4655 #if defined(TARGET_PPC64)
4656 static void gen_doze(DisasContext *ctx)
4657 {
4658 #if defined(CONFIG_USER_ONLY)
4659 GEN_PRIV;
4660 #else
4661 TCGv_i32 t;
4662
4663 CHK_HV;
4664 t = tcg_const_i32(PPC_PM_DOZE);
4665 gen_helper_pminsn(cpu_env, t);
4666 tcg_temp_free_i32(t);
4667 /* Stop translation, as the CPU is supposed to sleep from now */
4668 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
4669 #endif /* defined(CONFIG_USER_ONLY) */
4670 }
4671
4672 static void gen_nap(DisasContext *ctx)
4673 {
4674 #if defined(CONFIG_USER_ONLY)
4675 GEN_PRIV;
4676 #else
4677 TCGv_i32 t;
4678
4679 CHK_HV;
4680 t = tcg_const_i32(PPC_PM_NAP);
4681 gen_helper_pminsn(cpu_env, t);
4682 tcg_temp_free_i32(t);
4683 /* Stop translation, as the CPU is supposed to sleep from now */
4684 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
4685 #endif /* defined(CONFIG_USER_ONLY) */
4686 }
4687
4688 static void gen_stop(DisasContext *ctx)
4689 {
4690 #if defined(CONFIG_USER_ONLY)
4691 GEN_PRIV;
4692 #else
4693 TCGv_i32 t;
4694
4695 CHK_HV;
4696 t = tcg_const_i32(PPC_PM_STOP);
4697 gen_helper_pminsn(cpu_env, t);
4698 tcg_temp_free_i32(t);
4699 /* Stop translation, as the CPU is supposed to sleep from now */
4700 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
4701 #endif /* defined(CONFIG_USER_ONLY) */
4702 }
4703
4704 static void gen_sleep(DisasContext *ctx)
4705 {
4706 #if defined(CONFIG_USER_ONLY)
4707 GEN_PRIV;
4708 #else
4709 TCGv_i32 t;
4710
4711 CHK_HV;
4712 t = tcg_const_i32(PPC_PM_SLEEP);
4713 gen_helper_pminsn(cpu_env, t);
4714 tcg_temp_free_i32(t);
4715 /* Stop translation, as the CPU is supposed to sleep from now */
4716 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
4717 #endif /* defined(CONFIG_USER_ONLY) */
4718 }
4719
4720 static void gen_rvwinkle(DisasContext *ctx)
4721 {
4722 #if defined(CONFIG_USER_ONLY)
4723 GEN_PRIV;
4724 #else
4725 TCGv_i32 t;
4726
4727 CHK_HV;
4728 t = tcg_const_i32(PPC_PM_RVWINKLE);
4729 gen_helper_pminsn(cpu_env, t);
4730 tcg_temp_free_i32(t);
4731 /* Stop translation, as the CPU is supposed to sleep from now */
4732 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
4733 #endif /* defined(CONFIG_USER_ONLY) */
4734 }
4735 #endif /* #if defined(TARGET_PPC64) */
4736
4737 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
4738 {
4739 #if defined(TARGET_PPC64)
4740 if (ctx->has_cfar) {
4741 tcg_gen_movi_tl(cpu_cfar, nip);
4742 }
4743 #endif
4744 }
4745
4746 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
4747 {
4748 if (unlikely(ctx->singlestep_enabled)) {
4749 return false;
4750 }
4751
4752 #ifndef CONFIG_USER_ONLY
4753 return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
4754 #else
4755 return true;
4756 #endif
4757 }
4758
4759 static void gen_lookup_and_goto_ptr(DisasContext *ctx)
4760 {
4761 int sse = ctx->singlestep_enabled;
4762 if (unlikely(sse)) {
4763 if (sse & GDBSTUB_SINGLE_STEP) {
4764 gen_debug_exception(ctx);
4765 } else if (sse & (CPU_SINGLE_STEP | CPU_BRANCH_STEP)) {
4766 uint32_t excp = gen_prep_dbgex(ctx);
4767 gen_exception(ctx, excp);
4768 }
4769 tcg_gen_exit_tb(NULL, 0);
4770 } else {
4771 tcg_gen_lookup_and_goto_ptr();
4772 }
4773 }
4774
4775 /*** Branch ***/
4776 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
4777 {
4778 if (NARROW_MODE(ctx)) {
4779 dest = (uint32_t) dest;
4780 }
4781 if (use_goto_tb(ctx, dest)) {
4782 tcg_gen_goto_tb(n);
4783 tcg_gen_movi_tl(cpu_nip, dest & ~3);
4784 tcg_gen_exit_tb(ctx->base.tb, n);
4785 } else {
4786 tcg_gen_movi_tl(cpu_nip, dest & ~3);
4787 gen_lookup_and_goto_ptr(ctx);
4788 }
4789 }
4790
4791 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
4792 {
4793 if (NARROW_MODE(ctx)) {
4794 nip = (uint32_t)nip;
4795 }
4796 tcg_gen_movi_tl(cpu_lr, nip);
4797 }
4798
4799 /* b ba bl bla */
4800 static void gen_b(DisasContext *ctx)
4801 {
4802 target_ulong li, target;
4803
4804 ctx->exception = POWERPC_EXCP_BRANCH;
4805 /* sign extend LI */
4806 li = LI(ctx->opcode);
4807 li = (li ^ 0x02000000) - 0x02000000;
4808 if (likely(AA(ctx->opcode) == 0)) {
4809 target = ctx->base.pc_next + li - 4;
4810 } else {
4811 target = li;
4812 }
4813 if (LK(ctx->opcode)) {
4814 gen_setlr(ctx, ctx->base.pc_next);
4815 }
4816 gen_update_cfar(ctx, ctx->base.pc_next - 4);
4817 gen_goto_tb(ctx, 0, target);
4818 }
4819
4820 #define BCOND_IM 0
4821 #define BCOND_LR 1
4822 #define BCOND_CTR 2
4823 #define BCOND_TAR 3
4824
4825 static void gen_bcond(DisasContext *ctx, int type)
4826 {
4827 uint32_t bo = BO(ctx->opcode);
4828 TCGLabel *l1;
4829 TCGv target;
4830 ctx->exception = POWERPC_EXCP_BRANCH;
4831
4832 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
4833 target = tcg_temp_local_new();
4834 if (type == BCOND_CTR) {
4835 tcg_gen_mov_tl(target, cpu_ctr);
4836 } else if (type == BCOND_TAR) {
4837 gen_load_spr(target, SPR_TAR);
4838 } else {
4839 tcg_gen_mov_tl(target, cpu_lr);
4840 }
4841 } else {
4842 target = NULL;
4843 }
4844 if (LK(ctx->opcode)) {
4845 gen_setlr(ctx, ctx->base.pc_next);
4846 }
4847 l1 = gen_new_label();
4848 if ((bo & 0x4) == 0) {
4849 /* Decrement and test CTR */
4850 TCGv temp = tcg_temp_new();
4851
4852 if (type == BCOND_CTR) {
4853 /*
4854 * All ISAs up to v3 describe this form of bcctr as invalid but
4855 * some processors, ie. 64-bit server processors compliant with
4856 * arch 2.x, do implement a "test and decrement" logic instead,
4857 * as described in their respective UMs. This logic involves CTR
4858 * to act as both the branch target and a counter, which makes
4859 * it basically useless and thus never used in real code.
4860 *
4861 * This form was hence chosen to trigger extra micro-architectural
4862 * side-effect on real HW needed for the Spectre v2 workaround.
4863 * It is up to guests that implement such workaround, ie. linux, to
4864 * use this form in a way it just triggers the side-effect without
4865 * doing anything else harmful.
4866 */
4867 if (unlikely(!is_book3s_arch2x(ctx))) {
4868 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4869 tcg_temp_free(temp);
4870 tcg_temp_free(target);
4871 return;
4872 }
4873
4874 if (NARROW_MODE(ctx)) {
4875 tcg_gen_ext32u_tl(temp, cpu_ctr);
4876 } else {
4877 tcg_gen_mov_tl(temp, cpu_ctr);
4878 }
4879 if (bo & 0x2) {
4880 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
4881 } else {
4882 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
4883 }
4884 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
4885 } else {
4886 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
4887 if (NARROW_MODE(ctx)) {
4888 tcg_gen_ext32u_tl(temp, cpu_ctr);
4889 } else {
4890 tcg_gen_mov_tl(temp, cpu_ctr);
4891 }
4892 if (bo & 0x2) {
4893 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
4894 } else {
4895 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
4896 }
4897 }
4898 tcg_temp_free(temp);
4899 }
4900 if ((bo & 0x10) == 0) {
4901 /* Test CR */
4902 uint32_t bi = BI(ctx->opcode);
4903 uint32_t mask = 0x08 >> (bi & 0x03);
4904 TCGv_i32 temp = tcg_temp_new_i32();
4905
4906 if (bo & 0x8) {
4907 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
4908 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
4909 } else {
4910 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
4911 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
4912 }
4913 tcg_temp_free_i32(temp);
4914 }
4915 gen_update_cfar(ctx, ctx->base.pc_next - 4);
4916 if (type == BCOND_IM) {
4917 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
4918 if (likely(AA(ctx->opcode) == 0)) {
4919 gen_goto_tb(ctx, 0, ctx->base.pc_next + li - 4);
4920 } else {
4921 gen_goto_tb(ctx, 0, li);
4922 }
4923 } else {
4924 if (NARROW_MODE(ctx)) {
4925 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
4926 } else {
4927 tcg_gen_andi_tl(cpu_nip, target, ~3);
4928 }
4929 gen_lookup_and_goto_ptr(ctx);
4930 tcg_temp_free(target);
4931 }
4932 if ((bo & 0x14) != 0x14) {
4933 /* fallthrough case */
4934 gen_set_label(l1);
4935 gen_goto_tb(ctx, 1, ctx->base.pc_next);
4936 }
4937 }
4938
4939 static void gen_bc(DisasContext *ctx)
4940 {
4941 gen_bcond(ctx, BCOND_IM);
4942 }
4943
4944 static void gen_bcctr(DisasContext *ctx)
4945 {
4946 gen_bcond(ctx, BCOND_CTR);
4947 }
4948
4949 static void gen_bclr(DisasContext *ctx)
4950 {
4951 gen_bcond(ctx, BCOND_LR);
4952 }
4953
4954 static void gen_bctar(DisasContext *ctx)
4955 {
4956 gen_bcond(ctx, BCOND_TAR);
4957 }
4958
4959 /*** Condition register logical ***/
4960 #define GEN_CRLOGIC(name, tcg_op, opc) \
4961 static void glue(gen_, name)(DisasContext *ctx) \
4962 { \
4963 uint8_t bitmask; \
4964 int sh; \
4965 TCGv_i32 t0, t1; \
4966 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
4967 t0 = tcg_temp_new_i32(); \
4968 if (sh > 0) \
4969 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
4970 else if (sh < 0) \
4971 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
4972 else \
4973 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
4974 t1 = tcg_temp_new_i32(); \
4975 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
4976 if (sh > 0) \
4977 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
4978 else if (sh < 0) \
4979 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
4980 else \
4981 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
4982 tcg_op(t0, t0, t1); \
4983 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
4984 tcg_gen_andi_i32(t0, t0, bitmask); \
4985 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
4986 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
4987 tcg_temp_free_i32(t0); \
4988 tcg_temp_free_i32(t1); \
4989 }
4990
4991 /* crand */
4992 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
4993 /* crandc */
4994 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
4995 /* creqv */
4996 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
4997 /* crnand */
4998 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
4999 /* crnor */
5000 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
5001 /* cror */
5002 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
5003 /* crorc */
5004 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
5005 /* crxor */
5006 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
5007
5008 /* mcrf */
5009 static void gen_mcrf(DisasContext *ctx)
5010 {
5011 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
5012 }
5013
5014 /*** System linkage ***/
5015
5016 /* rfi (supervisor only) */
5017 static void gen_rfi(DisasContext *ctx)
5018 {
5019 #if defined(CONFIG_USER_ONLY)
5020 GEN_PRIV;
5021 #else
5022 /*
5023 * This instruction doesn't exist anymore on 64-bit server
5024 * processors compliant with arch 2.x
5025 */
5026 if (is_book3s_arch2x(ctx)) {
5027 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5028 return;
5029 }
5030 /* Restore CPU state */
5031 CHK_SV;
5032 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
5033 gen_io_start();
5034 }
5035 gen_update_cfar(ctx, ctx->base.pc_next - 4);
5036 gen_helper_rfi(cpu_env);
5037 gen_sync_exception(ctx);
5038 #endif
5039 }
5040
5041 #if defined(TARGET_PPC64)
5042 static void gen_rfid(DisasContext *ctx)
5043 {
5044 #if defined(CONFIG_USER_ONLY)
5045 GEN_PRIV;
5046 #else
5047 /* Restore CPU state */
5048 CHK_SV;
5049 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
5050 gen_io_start();
5051 }
5052 gen_update_cfar(ctx, ctx->base.pc_next - 4);
5053 gen_helper_rfid(cpu_env);
5054 gen_sync_exception(ctx);
5055 #endif
5056 }
5057
5058 #if !defined(CONFIG_USER_ONLY)
5059 static void gen_rfscv(DisasContext *ctx)
5060 {
5061 #if defined(CONFIG_USER_ONLY)
5062 GEN_PRIV;
5063 #else
5064 /* Restore CPU state */
5065 CHK_SV;
5066 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
5067 gen_io_start();
5068 }
5069 gen_update_cfar(ctx, ctx->base.pc_next - 4);
5070 gen_helper_rfscv(cpu_env);
5071 gen_sync_exception(ctx);
5072 #endif
5073 }
5074 #endif
5075
5076 static void gen_hrfid(DisasContext *ctx)
5077 {
5078 #if defined(CONFIG_USER_ONLY)
5079 GEN_PRIV;
5080 #else
5081 /* Restore CPU state */
5082 CHK_HV;
5083 gen_helper_hrfid(cpu_env);
5084 gen_sync_exception(ctx);
5085 #endif
5086 }
5087 #endif
5088
5089 /* sc */
5090 #if defined(CONFIG_USER_ONLY)
5091 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
5092 #else
5093 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
5094 #define POWERPC_SYSCALL_VECTORED POWERPC_EXCP_SYSCALL_VECTORED
5095 #endif
5096 static void gen_sc(DisasContext *ctx)
5097 {
5098 uint32_t lev;
5099
5100 lev = (ctx->opcode >> 5) & 0x7F;
5101 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
5102 }
5103
5104 #if defined(TARGET_PPC64)
5105 #if !defined(CONFIG_USER_ONLY)
5106 static void gen_scv(DisasContext *ctx)
5107 {
5108 uint32_t lev = (ctx->opcode >> 5) & 0x7F;
5109
5110 /* Set the PC back to the faulting instruction. */
5111 if (ctx->exception == POWERPC_EXCP_NONE) {
5112 gen_update_nip(ctx, ctx->base.pc_next - 4);
5113 }
5114 gen_helper_scv(cpu_env, tcg_constant_i32(lev));
5115
5116 /* This need not be exact, just not POWERPC_EXCP_NONE */
5117 ctx->exception = POWERPC_SYSCALL_VECTORED;
5118 }
5119 #endif
5120 #endif
5121
5122 /*** Trap ***/
5123
5124 /* Check for unconditional traps (always or never) */
5125 static bool check_unconditional_trap(DisasContext *ctx)
5126 {
5127 /* Trap never */
5128 if (TO(ctx->opcode) == 0) {
5129 return true;
5130 }
5131 /* Trap always */
5132 if (TO(ctx->opcode) == 31) {
5133 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
5134 return true;
5135 }
5136 return false;
5137 }
5138
5139 /* tw */
5140 static void gen_tw(DisasContext *ctx)
5141 {
5142 TCGv_i32 t0;
5143
5144 if (check_unconditional_trap(ctx)) {
5145 return;
5146 }
5147 t0 = tcg_const_i32(TO(ctx->opcode));
5148 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
5149 t0);
5150 tcg_temp_free_i32(t0);
5151 }
5152
5153 /* twi */
5154 static void gen_twi(DisasContext *ctx)
5155 {
5156 TCGv t0;
5157 TCGv_i32 t1;
5158
5159 if (check_unconditional_trap(ctx)) {
5160 return;
5161 }
5162 t0 = tcg_const_tl(SIMM(ctx->opcode));
5163 t1 = tcg_const_i32(TO(ctx->opcode));
5164 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
5165 tcg_temp_free(t0);
5166 tcg_temp_free_i32(t1);
5167 }
5168
5169 #if defined(TARGET_PPC64)
5170 /* td */
5171 static void gen_td(DisasContext *ctx)
5172 {
5173 TCGv_i32 t0;
5174
5175 if (check_unconditional_trap(ctx)) {
5176 return;
5177 }
5178 t0 = tcg_const_i32(TO(ctx->opcode));
5179 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
5180 t0);
5181 tcg_temp_free_i32(t0);
5182 }
5183
5184 /* tdi */
5185 static void gen_tdi(DisasContext *ctx)
5186 {
5187 TCGv t0;
5188 TCGv_i32 t1;
5189
5190 if (check_unconditional_trap(ctx)) {
5191 return;
5192 }
5193 t0 = tcg_const_tl(SIMM(ctx->opcode));
5194 t1 = tcg_const_i32(TO(ctx->opcode));
5195 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
5196 tcg_temp_free(t0);
5197 tcg_temp_free_i32(t1);
5198 }
5199 #endif
5200
5201 /*** Processor control ***/
5202
5203 /* mcrxr */
5204 static void gen_mcrxr(DisasContext *ctx)
5205 {
5206 TCGv_i32 t0 = tcg_temp_new_i32();
5207 TCGv_i32 t1 = tcg_temp_new_i32();
5208 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
5209
5210 tcg_gen_trunc_tl_i32(t0, cpu_so);
5211 tcg_gen_trunc_tl_i32(t1, cpu_ov);
5212 tcg_gen_trunc_tl_i32(dst, cpu_ca);
5213 tcg_gen_shli_i32(t0, t0, 3);
5214 tcg_gen_shli_i32(t1, t1, 2);
5215 tcg_gen_shli_i32(dst, dst, 1);
5216 tcg_gen_or_i32(dst, dst, t0);
5217 tcg_gen_or_i32(dst, dst, t1);
5218 tcg_temp_free_i32(t0);
5219 tcg_temp_free_i32(t1);
5220
5221 tcg_gen_movi_tl(cpu_so, 0);
5222 tcg_gen_movi_tl(cpu_ov, 0);
5223 tcg_gen_movi_tl(cpu_ca, 0);
5224 }
5225
5226 #ifdef TARGET_PPC64
5227 /* mcrxrx */
5228 static void gen_mcrxrx(DisasContext *ctx)
5229 {
5230 TCGv t0 = tcg_temp_new();
5231 TCGv t1 = tcg_temp_new();
5232 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
5233
5234 /* copy OV and OV32 */
5235 tcg_gen_shli_tl(t0, cpu_ov, 1);
5236 tcg_gen_or_tl(t0, t0, cpu_ov32);
5237 tcg_gen_shli_tl(t0, t0, 2);
5238 /* copy CA and CA32 */
5239 tcg_gen_shli_tl(t1, cpu_ca, 1);
5240 tcg_gen_or_tl(t1, t1, cpu_ca32);
5241 tcg_gen_or_tl(t0, t0, t1);
5242 tcg_gen_trunc_tl_i32(dst, t0);
5243 tcg_temp_free(t0);
5244 tcg_temp_free(t1);
5245 }
5246 #endif
5247
5248 /* mfcr mfocrf */
5249 static void gen_mfcr(DisasContext *ctx)
5250 {
5251 uint32_t crm, crn;
5252
5253 if (likely(ctx->opcode & 0x00100000)) {
5254 crm = CRM(ctx->opcode);
5255 if (likely(crm && ((crm & (crm - 1)) == 0))) {
5256 crn = ctz32(crm);
5257 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
5258 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
5259 cpu_gpr[rD(ctx->opcode)], crn * 4);
5260 }
5261 } else {
5262 TCGv_i32 t0 = tcg_temp_new_i32();
5263 tcg_gen_mov_i32(t0, cpu_crf[0]);
5264 tcg_gen_shli_i32(t0, t0, 4);
5265 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
5266 tcg_gen_shli_i32(t0, t0, 4);
5267 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
5268 tcg_gen_shli_i32(t0, t0, 4);
5269 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
5270 tcg_gen_shli_i32(t0, t0, 4);
5271 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
5272 tcg_gen_shli_i32(t0, t0, 4);
5273 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
5274 tcg_gen_shli_i32(t0, t0, 4);
5275 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
5276 tcg_gen_shli_i32(t0, t0, 4);
5277 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
5278 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
5279 tcg_temp_free_i32(t0);
5280 }
5281 }
5282
5283 /* mfmsr */
5284 static void gen_mfmsr(DisasContext *ctx)
5285 {
5286 CHK_SV;
5287 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
5288 }
5289
5290 /* mfspr */
5291 static inline void gen_op_mfspr(DisasContext *ctx)
5292 {
5293 void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
5294 uint32_t sprn = SPR(ctx->opcode);
5295
5296 #if defined(CONFIG_USER_ONLY)
5297 read_cb = ctx->spr_cb[sprn].uea_read;
5298 #else
5299 if (ctx->pr) {
5300 read_cb = ctx->spr_cb[sprn].uea_read;
5301 } else if (ctx->hv) {
5302 read_cb = ctx->spr_cb[sprn].hea_read;
5303 } else {
5304 read_cb = ctx->spr_cb[sprn].oea_read;
5305 }
5306 #endif
5307 if (likely(read_cb != NULL)) {
5308 if (likely(read_cb != SPR_NOACCESS)) {
5309 (*read_cb)(ctx, rD(ctx->opcode), sprn);
5310 } else {
5311 /* Privilege exception */
5312 /*
5313 * This is a hack to avoid warnings when running Linux:
5314 * this OS breaks the PowerPC virtualisation model,
5315 * allowing userland application to read the PVR
5316 */
5317 if (sprn != SPR_PVR) {
5318 qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr "
5319 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn,
5320 ctx->base.pc_next - 4);
5321 }
5322 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
5323 }
5324 } else {
5325 /* ISA 2.07 defines these as no-ops */
5326 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
5327 (sprn >= 808 && sprn <= 811)) {
5328 /* This is a nop */
5329 return;
5330 }
5331 /* Not defined */
5332 qemu_log_mask(LOG_GUEST_ERROR,
5333 "Trying to read invalid spr %d (0x%03x) at "
5334 TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4);
5335
5336 /*
5337 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can
5338 * generate a priv, a hv emu or a no-op
5339 */
5340 if (sprn & 0x10) {
5341 if (ctx->pr) {
5342 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
5343 }
5344 } else {
5345 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) {
5346 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
5347 }
5348 }
5349 }
5350 }
5351
5352 static void gen_mfspr(DisasContext *ctx)
5353 {
5354 gen_op_mfspr(ctx);
5355 }
5356
5357 /* mftb */
5358 static void gen_mftb(DisasContext *ctx)
5359 {
5360 gen_op_mfspr(ctx);
5361 }
5362
5363 /* mtcrf mtocrf*/
5364 static void gen_mtcrf(DisasContext *ctx)
5365 {
5366 uint32_t crm, crn;
5367
5368 crm = CRM(ctx->opcode);
5369 if (likely((ctx->opcode & 0x00100000))) {
5370 if (crm && ((crm & (crm - 1)) == 0)) {
5371 TCGv_i32 temp = tcg_temp_new_i32();
5372 crn = ctz32(crm);
5373 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
5374 tcg_gen_shri_i32(temp, temp, crn * 4);
5375 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
5376 tcg_temp_free_i32(temp);
5377 }
5378 } else {
5379 TCGv_i32 temp = tcg_temp_new_i32();
5380 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
5381 for (crn = 0 ; crn < 8 ; crn++) {
5382 if (crm & (1 << crn)) {
5383 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
5384 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
5385 }
5386 }
5387 tcg_temp_free_i32(temp);
5388 }
5389 }
5390
5391 /* mtmsr */
5392 #if defined(TARGET_PPC64)
5393 static void gen_mtmsrd(DisasContext *ctx)
5394 {
5395 CHK_SV;
5396
5397 #if !defined(CONFIG_USER_ONLY)
5398 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
5399 gen_io_start();
5400 }
5401 if (ctx->opcode & 0x00010000) {
5402 /* L=1 form only updates EE and RI */
5403 TCGv t0 = tcg_temp_new();
5404 TCGv t1 = tcg_temp_new();
5405 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)],
5406 (1 << MSR_RI) | (1 << MSR_EE));
5407 tcg_gen_andi_tl(t1, cpu_msr,
5408 ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
5409 tcg_gen_or_tl(t1, t1, t0);
5410
5411 gen_helper_store_msr(cpu_env, t1);
5412 tcg_temp_free(t0);
5413 tcg_temp_free(t1);
5414
5415 } else {
5416 /*
5417 * XXX: we need to update nip before the store if we enter
5418 * power saving mode, we will exit the loop directly from
5419 * ppc_store_msr
5420 */
5421 gen_update_nip(ctx, ctx->base.pc_next);
5422 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
5423 }
5424 /* Must stop the translation as machine state (may have) changed */
5425 gen_stop_exception(ctx);
5426 #endif /* !defined(CONFIG_USER_ONLY) */
5427 }
5428 #endif /* defined(TARGET_PPC64) */
5429
5430 static void gen_mtmsr(DisasContext *ctx)
5431 {
5432 CHK_SV;
5433
5434 #if !defined(CONFIG_USER_ONLY)
5435 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
5436 gen_io_start();
5437 }
5438 if (ctx->opcode & 0x00010000) {
5439 /* L=1 form only updates EE and RI */
5440 TCGv t0 = tcg_temp_new();
5441 TCGv t1 = tcg_temp_new();
5442 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)],
5443 (1 << MSR_RI) | (1 << MSR_EE));
5444 tcg_gen_andi_tl(t1, cpu_msr,
5445 ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
5446 tcg_gen_or_tl(t1, t1, t0);
5447
5448 gen_helper_store_msr(cpu_env, t1);
5449 tcg_temp_free(t0);
5450 tcg_temp_free(t1);
5451
5452 } else {
5453 TCGv msr = tcg_temp_new();
5454
5455 /*
5456 * XXX: we need to update nip before the store if we enter
5457 * power saving mode, we will exit the loop directly from
5458 * ppc_store_msr
5459 */
5460 gen_update_nip(ctx, ctx->base.pc_next);
5461 #if defined(TARGET_PPC64)
5462 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
5463 #else
5464 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
5465 #endif
5466 gen_helper_store_msr(cpu_env, msr);
5467 tcg_temp_free(msr);
5468 }
5469 /* Must stop the translation as machine state (may have) changed */
5470 gen_stop_exception(ctx);
5471 #endif
5472 }
5473
5474 /* mtspr */
5475 static void gen_mtspr(DisasContext *ctx)
5476 {
5477 void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
5478 uint32_t sprn = SPR(ctx->opcode);
5479
5480 #if defined(CONFIG_USER_ONLY)
5481 write_cb = ctx->spr_cb[sprn].uea_write;
5482 #else
5483 if (ctx->pr) {
5484 write_cb = ctx->spr_cb[sprn].uea_write;
5485 } else if (ctx->hv) {
5486 write_cb = ctx->spr_cb[sprn].hea_write;
5487 } else {
5488 write_cb = ctx->spr_cb[sprn].oea_write;
5489 }
5490 #endif
5491 if (likely(write_cb != NULL)) {
5492 if (likely(write_cb != SPR_NOACCESS)) {
5493 (*write_cb)(ctx, sprn, rS(ctx->opcode));
5494 } else {
5495 /* Privilege exception */
5496 qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr "
5497 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn,
5498 ctx->base.pc_next - 4);
5499 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
5500 }
5501 } else {
5502 /* ISA 2.07 defines these as no-ops */
5503 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
5504 (sprn >= 808 && sprn <= 811)) {
5505 /* This is a nop */
5506 return;
5507 }
5508
5509 /* Not defined */
5510 qemu_log_mask(LOG_GUEST_ERROR,
5511 "Trying to write invalid spr %d (0x%03x) at "
5512 TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4);
5513
5514
5515 /*
5516 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can
5517 * generate a priv, a hv emu or a no-op
5518 */
5519 if (sprn & 0x10) {
5520 if (ctx->pr) {
5521 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
5522 }
5523 } else {
5524 if (ctx->pr || sprn == 0) {
5525 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
5526 }
5527 }
5528 }
5529 }
5530
5531 #if defined(TARGET_PPC64)
5532 /* setb */
5533 static void gen_setb(DisasContext *ctx)
5534 {
5535 TCGv_i32 t0 = tcg_temp_new_i32();
5536 TCGv_i32 t8 = tcg_temp_new_i32();
5537 TCGv_i32 tm1 = tcg_temp_new_i32();
5538 int crf = crfS(ctx->opcode);
5539
5540 tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4);
5541 tcg_gen_movi_i32(t8, 8);
5542 tcg_gen_movi_i32(tm1, -1);
5543 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0);
5544 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
5545
5546 tcg_temp_free_i32(t0);
5547 tcg_temp_free_i32(t8);
5548 tcg_temp_free_i32(tm1);
5549 }
5550 #endif
5551
5552 /*** Cache management ***/
5553
5554 /* dcbf */
5555 static void gen_dcbf(DisasContext *ctx)
5556 {
5557 /* XXX: specification says this is treated as a load by the MMU */
5558 TCGv t0;
5559 gen_set_access_type(ctx, ACCESS_CACHE);
5560 t0 = tcg_temp_new();
5561 gen_addr_reg_index(ctx, t0);
5562 gen_qemu_ld8u(ctx, t0, t0);
5563 tcg_temp_free(t0);
5564 }
5565
5566 /* dcbfep (external PID dcbf) */
5567 static void gen_dcbfep(DisasContext *ctx)
5568 {
5569 /* XXX: specification says this is treated as a load by the MMU */
5570 TCGv t0;
5571 CHK_SV;
5572 gen_set_access_type(ctx, ACCESS_CACHE);
5573 t0 = tcg_temp_new();
5574 gen_addr_reg_index(ctx, t0);
5575 tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB));
5576 tcg_temp_free(t0);
5577 }
5578
5579 /* dcbi (Supervisor only) */
5580 static void gen_dcbi(DisasContext *ctx)
5581 {
5582 #if defined(CONFIG_USER_ONLY)
5583 GEN_PRIV;
5584 #else
5585 TCGv EA, val;
5586
5587 CHK_SV;
5588 EA = tcg_temp_new();
5589 gen_set_access_type(ctx, ACCESS_CACHE);
5590 gen_addr_reg_index(ctx, EA);
5591 val = tcg_temp_new();
5592 /* XXX: specification says this should be treated as a store by the MMU */
5593 gen_qemu_ld8u(ctx, val, EA);
5594 gen_qemu_st8(ctx, val, EA);
5595 tcg_temp_free(val);
5596 tcg_temp_free(EA);
5597 #endif /* defined(CONFIG_USER_ONLY) */
5598 }
5599
5600 /* dcdst */
5601 static void gen_dcbst(DisasContext *ctx)
5602 {
5603 /* XXX: specification say this is treated as a load by the MMU */
5604 TCGv t0;
5605 gen_set_access_type(ctx, ACCESS_CACHE);
5606 t0 = tcg_temp_new();
5607 gen_addr_reg_index(ctx, t0);
5608 gen_qemu_ld8u(ctx, t0, t0);
5609 tcg_temp_free(t0);
5610 }
5611
5612 /* dcbstep (dcbstep External PID version) */
5613 static void gen_dcbstep(DisasContext *ctx)
5614 {
5615 /* XXX: specification say this is treated as a load by the MMU */
5616 TCGv t0;
5617 gen_set_access_type(ctx, ACCESS_CACHE);
5618 t0 = tcg_temp_new();
5619 gen_addr_reg_index(ctx, t0);
5620 tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB));
5621 tcg_temp_free(t0);
5622 }
5623
5624 /* dcbt */
5625 static void gen_dcbt(DisasContext *ctx)
5626 {
5627 /*
5628 * interpreted as no-op
5629 * XXX: specification say this is treated as a load by the MMU but
5630 * does not generate any exception
5631 */
5632 }
5633
5634 /* dcbtep */
5635 static void gen_dcbtep(DisasContext *ctx)
5636 {
5637 /*
5638 * interpreted as no-op
5639 * XXX: specification say this is treated as a load by the MMU but
5640 * does not generate any exception
5641 */
5642 }
5643
5644 /* dcbtst */
5645 static void gen_dcbtst(DisasContext *ctx)
5646 {
5647 /*
5648 * interpreted as no-op
5649 * XXX: specification say this is treated as a load by the MMU but
5650 * does not generate any exception
5651 */
5652 }
5653
5654 /* dcbtstep */
5655 static void gen_dcbtstep(DisasContext *ctx)
5656 {
5657 /*
5658 * interpreted as no-op
5659 * XXX: specification say this is treated as a load by the MMU but
5660 * does not generate any exception
5661 */
5662 }
5663
5664 /* dcbtls */
5665 static void gen_dcbtls(DisasContext *ctx)
5666 {
5667 /* Always fails locking the cache */
5668 TCGv t0 = tcg_temp_new();
5669 gen_load_spr(t0, SPR_Exxx_L1CSR0);
5670 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
5671 gen_store_spr(SPR_Exxx_L1CSR0, t0);
5672 tcg_temp_free(t0);
5673 }
5674
5675 /* dcbz */
5676 static void gen_dcbz(DisasContext *ctx)
5677 {
5678 TCGv tcgv_addr;
5679 TCGv_i32 tcgv_op;
5680
5681 gen_set_access_type(ctx, ACCESS_CACHE);
5682 tcgv_addr = tcg_temp_new();
5683 tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000);
5684 gen_addr_reg_index(ctx, tcgv_addr);
5685 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op);
5686 tcg_temp_free(tcgv_addr);
5687 tcg_temp_free_i32(tcgv_op);
5688 }
5689
5690 /* dcbzep */
5691 static void gen_dcbzep(DisasContext *ctx)
5692 {
5693 TCGv tcgv_addr;
5694 TCGv_i32 tcgv_op;
5695
5696 gen_set_access_type(ctx, ACCESS_CACHE);
5697 tcgv_addr = tcg_temp_new();
5698 tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000);
5699 gen_addr_reg_index(ctx, tcgv_addr);
5700 gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op);
5701 tcg_temp_free(tcgv_addr);
5702 tcg_temp_free_i32(tcgv_op);
5703 }
5704
5705 /* dst / dstt */
5706 static void gen_dst(DisasContext *ctx)
5707 {
5708 if (rA(ctx->opcode) == 0) {
5709 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5710 } else {
5711 /* interpreted as no-op */
5712 }
5713 }
5714
5715 /* dstst /dststt */
5716 static void gen_dstst(DisasContext *ctx)
5717 {
5718 if (rA(ctx->opcode) == 0) {
5719 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5720 } else {
5721 /* interpreted as no-op */
5722 }
5723
5724 }
5725
5726 /* dss / dssall */
5727 static void gen_dss(DisasContext *ctx)
5728 {
5729 /* interpreted as no-op */
5730 }
5731
5732 /* icbi */
5733 static void gen_icbi(DisasContext *ctx)
5734 {
5735 TCGv t0;
5736 gen_set_access_type(ctx, ACCESS_CACHE);
5737 t0 = tcg_temp_new();
5738 gen_addr_reg_index(ctx, t0);
5739 gen_helper_icbi(cpu_env, t0);
5740 tcg_temp_free(t0);
5741 }
5742
5743 /* icbiep */
5744 static void gen_icbiep(DisasContext *ctx)
5745 {
5746 TCGv t0;
5747 gen_set_access_type(ctx, ACCESS_CACHE);
5748 t0 = tcg_temp_new();
5749 gen_addr_reg_index(ctx, t0);
5750 gen_helper_icbiep(cpu_env, t0);
5751 tcg_temp_free(t0);
5752 }
5753
5754 /* Optional: */
5755 /* dcba */
5756 static void gen_dcba(DisasContext *ctx)
5757 {
5758 /*
5759 * interpreted as no-op
5760 * XXX: specification say this is treated as a store by the MMU
5761 * but does not generate any exception
5762 */
5763 }
5764
5765 /*** Segment register manipulation ***/
5766 /* Supervisor only: */
5767
5768 /* mfsr */
5769 static void gen_mfsr(DisasContext *ctx)
5770 {
5771 #if defined(CONFIG_USER_ONLY)
5772 GEN_PRIV;
5773 #else
5774 TCGv t0;
5775
5776 CHK_SV;
5777 t0 = tcg_const_tl(SR(ctx->opcode));
5778 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5779 tcg_temp_free(t0);
5780 #endif /* defined(CONFIG_USER_ONLY) */
5781 }
5782
5783 /* mfsrin */
5784 static void gen_mfsrin(DisasContext *ctx)
5785 {
5786 #if defined(CONFIG_USER_ONLY)
5787 GEN_PRIV;
5788 #else
5789 TCGv t0;
5790
5791 CHK_SV;
5792 t0 = tcg_temp_new();
5793 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
5794 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5795 tcg_temp_free(t0);
5796 #endif /* defined(CONFIG_USER_ONLY) */
5797 }
5798
5799 /* mtsr */
5800 static void gen_mtsr(DisasContext *ctx)
5801 {
5802 #if defined(CONFIG_USER_ONLY)
5803 GEN_PRIV;
5804 #else
5805 TCGv t0;
5806
5807 CHK_SV;
5808 t0 = tcg_const_tl(SR(ctx->opcode));
5809 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
5810 tcg_temp_free(t0);
5811 #endif /* defined(CONFIG_USER_ONLY) */
5812 }
5813
5814 /* mtsrin */
5815 static void gen_mtsrin(DisasContext *ctx)
5816 {
5817 #if defined(CONFIG_USER_ONLY)
5818 GEN_PRIV;
5819 #else
5820 TCGv t0;
5821 CHK_SV;
5822
5823 t0 = tcg_temp_new();
5824 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
5825 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
5826 tcg_temp_free(t0);
5827 #endif /* defined(CONFIG_USER_ONLY) */
5828 }
5829
5830 #if defined(TARGET_PPC64)
5831 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
5832
5833 /* mfsr */
5834 static void gen_mfsr_64b(DisasContext *ctx)
5835 {
5836 #if defined(CONFIG_USER_ONLY)
5837 GEN_PRIV;
5838 #else
5839 TCGv t0;
5840
5841 CHK_SV;
5842 t0 = tcg_const_tl(SR(ctx->opcode));
5843 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5844 tcg_temp_free(t0);
5845 #endif /* defined(CONFIG_USER_ONLY) */
5846 }
5847
5848 /* mfsrin */
5849 static void gen_mfsrin_64b(DisasContext *ctx)
5850 {
5851 #if defined(CONFIG_USER_ONLY)
5852 GEN_PRIV;
5853 #else
5854 TCGv t0;
5855
5856 CHK_SV;
5857 t0 = tcg_temp_new();
5858 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
5859 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5860 tcg_temp_free(t0);
5861 #endif /* defined(CONFIG_USER_ONLY) */
5862 }
5863
5864 /* mtsr */
5865 static void gen_mtsr_64b(DisasContext *ctx)
5866 {
5867 #if defined(CONFIG_USER_ONLY)
5868 GEN_PRIV;
5869 #else
5870 TCGv t0;
5871
5872 CHK_SV;
5873 t0 = tcg_const_tl(SR(ctx->opcode));
5874 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
5875 tcg_temp_free(t0);
5876 #endif /* defined(CONFIG_USER_ONLY) */
5877 }
5878
5879 /* mtsrin */
5880 static void gen_mtsrin_64b(DisasContext *ctx)
5881 {
5882 #if defined(CONFIG_USER_ONLY)
5883 GEN_PRIV;
5884 #else
5885 TCGv t0;
5886
5887 CHK_SV;
5888 t0 = tcg_temp_new();
5889 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
5890 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
5891 tcg_temp_free(t0);
5892 #endif /* defined(CONFIG_USER_ONLY) */
5893 }
5894
5895 /* slbmte */
5896 static void gen_slbmte(DisasContext *ctx)
5897 {
5898 #if defined(CONFIG_USER_ONLY)
5899 GEN_PRIV;
5900 #else
5901 CHK_SV;
5902
5903 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
5904 cpu_gpr[rS(ctx->opcode)]);
5905 #endif /* defined(CONFIG_USER_ONLY) */
5906 }
5907
5908 static void gen_slbmfee(DisasContext *ctx)
5909 {
5910 #if defined(CONFIG_USER_ONLY)
5911 GEN_PRIV;
5912 #else
5913 CHK_SV;
5914
5915 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
5916 cpu_gpr[rB(ctx->opcode)]);
5917 #endif /* defined(CONFIG_USER_ONLY) */
5918 }
5919
5920 static void gen_slbmfev(DisasContext *ctx)
5921 {
5922 #if defined(CONFIG_USER_ONLY)
5923 GEN_PRIV;
5924 #else
5925 CHK_SV;
5926
5927 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
5928 cpu_gpr[rB(ctx->opcode)]);
5929 #endif /* defined(CONFIG_USER_ONLY) */
5930 }
5931
5932 static void gen_slbfee_(DisasContext *ctx)
5933 {
5934 #if defined(CONFIG_USER_ONLY)
5935 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5936 #else
5937 TCGLabel *l1, *l2;
5938
5939 if (unlikely(ctx->pr)) {
5940 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5941 return;
5942 }
5943 gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
5944 cpu_gpr[rB(ctx->opcode)]);
5945 l1 = gen_new_label();
5946 l2 = gen_new_label();
5947 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5948 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1);
5949 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
5950 tcg_gen_br(l2);
5951 gen_set_label(l1);
5952 tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0);
5953 gen_set_label(l2);
5954 #endif
5955 }
5956 #endif /* defined(TARGET_PPC64) */
5957
5958 /*** Lookaside buffer management ***/
5959 /* Optional & supervisor only: */
5960
5961 /* tlbia */
5962 static void gen_tlbia(DisasContext *ctx)
5963 {
5964 #if defined(CONFIG_USER_ONLY)
5965 GEN_PRIV;
5966 #else
5967 CHK_HV;
5968
5969 gen_helper_tlbia(cpu_env);
5970 #endif /* defined(CONFIG_USER_ONLY) */
5971 }
5972
5973 /* tlbiel */
5974 static void gen_tlbiel(DisasContext *ctx)
5975 {
5976 #if defined(CONFIG_USER_ONLY)
5977 GEN_PRIV;
5978 #else
5979 CHK_SV;
5980
5981 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5982 #endif /* defined(CONFIG_USER_ONLY) */
5983 }
5984
5985 /* tlbie */
5986 static void gen_tlbie(DisasContext *ctx)
5987 {
5988 #if defined(CONFIG_USER_ONLY)
5989 GEN_PRIV;
5990 #else
5991 TCGv_i32 t1;
5992
5993 if (ctx->gtse) {
5994 CHK_SV; /* If gtse is set then tlbie is supervisor privileged */
5995 } else {
5996 CHK_HV; /* Else hypervisor privileged */
5997 }
5998
5999 if (NARROW_MODE(ctx)) {
6000 TCGv t0 = tcg_temp_new();
6001 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
6002 gen_helper_tlbie(cpu_env, t0);
6003 tcg_temp_free(t0);
6004 } else {
6005 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6006 }
6007 t1 = tcg_temp_new_i32();
6008 tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
6009 tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH);
6010 tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
6011 tcg_temp_free_i32(t1);
6012 #endif /* defined(CONFIG_USER_ONLY) */
6013 }
6014
6015 /* tlbsync */
6016 static void gen_tlbsync(DisasContext *ctx)
6017 {
6018 #if defined(CONFIG_USER_ONLY)
6019 GEN_PRIV;
6020 #else
6021
6022 if (ctx->gtse) {
6023 CHK_SV; /* If gtse is set then tlbsync is supervisor privileged */
6024 } else {
6025 CHK_HV; /* Else hypervisor privileged */
6026 }
6027
6028 /* BookS does both ptesync and tlbsync make tlbsync a nop for server */
6029 if (ctx->insns_flags & PPC_BOOKE) {
6030 gen_check_tlb_flush(ctx, true);
6031 }
6032 #endif /* defined(CONFIG_USER_ONLY) */
6033 }
6034
6035 #if defined(TARGET_PPC64)
6036 /* slbia */
6037 static void gen_slbia(DisasContext *ctx)
6038 {
6039 #if defined(CONFIG_USER_ONLY)
6040 GEN_PRIV;
6041 #else
6042 uint32_t ih = (ctx->opcode >> 21) & 0x7;
6043 TCGv_i32 t0 = tcg_const_i32(ih);
6044
6045 CHK_SV;
6046
6047 gen_helper_slbia(cpu_env, t0);
6048 tcg_temp_free_i32(t0);
6049 #endif /* defined(CONFIG_USER_ONLY) */
6050 }
6051
6052 /* slbie */
6053 static void gen_slbie(DisasContext *ctx)
6054 {
6055 #if defined(CONFIG_USER_ONLY)
6056 GEN_PRIV;
6057 #else
6058 CHK_SV;
6059
6060 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6061 #endif /* defined(CONFIG_USER_ONLY) */
6062 }
6063
6064 /* slbieg */
6065 static void gen_slbieg(DisasContext *ctx)
6066 {
6067 #if defined(CONFIG_USER_ONLY)
6068 GEN_PRIV;
6069 #else
6070 CHK_SV;
6071
6072 gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6073 #endif /* defined(CONFIG_USER_ONLY) */
6074 }
6075
6076 /* slbsync */
6077 static void gen_slbsync(DisasContext *ctx)
6078 {
6079 #if defined(CONFIG_USER_ONLY)
6080 GEN_PRIV;
6081 #else
6082 CHK_SV;
6083 gen_check_tlb_flush(ctx, true);
6084 #endif /* defined(CONFIG_USER_ONLY) */
6085 }
6086
6087 #endif /* defined(TARGET_PPC64) */
6088
6089 /*** External control ***/
6090 /* Optional: */
6091
6092 /* eciwx */
6093 static void gen_eciwx(DisasContext *ctx)
6094 {
6095 TCGv t0;
6096 /* Should check EAR[E] ! */
6097 gen_set_access_type(ctx, ACCESS_EXT);
6098 t0 = tcg_temp_new();
6099 gen_addr_reg_index(ctx, t0);
6100 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx,
6101 DEF_MEMOP(MO_UL | MO_ALIGN));
6102 tcg_temp_free(t0);
6103 }
6104
6105 /* ecowx */
6106 static void gen_ecowx(DisasContext *ctx)
6107 {
6108 TCGv t0;
6109 /* Should check EAR[E] ! */
6110 gen_set_access_type(ctx, ACCESS_EXT);
6111 t0 = tcg_temp_new();
6112 gen_addr_reg_index(ctx, t0);
6113 tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx,
6114 DEF_MEMOP(MO_UL | MO_ALIGN));
6115 tcg_temp_free(t0);
6116 }
6117
6118 /* PowerPC 601 specific instructions */
6119
6120 /* abs - abs. */
6121 static void gen_abs(DisasContext *ctx)
6122 {
6123 TCGv d = cpu_gpr[rD(ctx->opcode)];
6124 TCGv a = cpu_gpr[rA(ctx->opcode)];
6125
6126 tcg_gen_abs_tl(d, a);
6127 if (unlikely(Rc(ctx->opcode) != 0)) {
6128 gen_set_Rc0(ctx, d);
6129 }
6130 }
6131
6132 /* abso - abso. */
6133 static void gen_abso(DisasContext *ctx)
6134 {
6135 TCGv d = cpu_gpr[rD(ctx->opcode)];
6136 TCGv a = cpu_gpr[rA(ctx->opcode)];
6137
6138 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_ov, a, 0x80000000);
6139 tcg_gen_abs_tl(d, a);
6140 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
6141 if (unlikely(Rc(ctx->opcode) != 0)) {
6142 gen_set_Rc0(ctx, d);
6143 }
6144 }
6145
6146 /* clcs */
6147 static void gen_clcs(DisasContext *ctx)
6148 {
6149 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
6150 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6151 tcg_temp_free_i32(t0);
6152 /* Rc=1 sets CR0 to an undefined state */
6153 }
6154
6155 /* div - div. */
6156 static void gen_div(DisasContext *ctx)
6157 {
6158 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
6159 cpu_gpr[rB(ctx->opcode)]);
6160 if (unlikely(Rc(ctx->opcode) != 0)) {
6161 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
6162 }
6163 }
6164
6165 /* divo - divo. */
6166 static void gen_divo(DisasContext *ctx)
6167 {
6168 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
6169 cpu_gpr[rB(ctx->opcode)]);
6170 if (unlikely(Rc(ctx->opcode) != 0)) {
6171 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
6172 }
6173 }
6174
6175 /* divs - divs. */
6176 static void gen_divs(DisasContext *ctx)
6177 {
6178 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
6179 cpu_gpr[rB(ctx->opcode)]);
6180 if (unlikely(Rc(ctx->opcode) != 0)) {
6181 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
6182 }
6183 }
6184
6185 /* divso - divso. */
6186 static void gen_divso(DisasContext *ctx)
6187 {
6188 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
6189 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6190 if (unlikely(Rc(ctx->opcode) != 0)) {
6191 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
6192 }
6193 }
6194
6195 /* doz - doz. */
6196 static void gen_doz(DisasContext *ctx)
6197 {
6198 TCGLabel *l1 = gen_new_label();
6199 TCGLabel *l2 = gen_new_label();
6200 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)],
6201 cpu_gpr[rA(ctx->opcode)], l1);
6202 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
6203 cpu_gpr[rA(ctx->opcode)]);
6204 tcg_gen_br(l2);
6205 gen_set_label(l1);
6206 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
6207 gen_set_label(l2);
6208 if (unlikely(Rc(ctx->opcode) != 0)) {
6209 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
6210 }
6211 }
6212
6213 /* dozo - dozo. */
6214 static void gen_dozo(DisasContext *ctx)
6215 {
6216 TCGLabel *l1 = gen_new_label();
6217 TCGLabel *l2 = gen_new_label();
6218 TCGv t0 = tcg_temp_new();
6219 TCGv t1 = tcg_temp_new();
6220 TCGv t2 = tcg_temp_new();
6221 /* Start with XER OV disabled, the most likely case */
6222 tcg_gen_movi_tl(cpu_ov, 0);
6223 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)],
6224 cpu_gpr[rA(ctx->opcode)], l1);
6225 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6226 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6227 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
6228 tcg_gen_andc_tl(t1, t1, t2);
6229 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6230 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
6231 tcg_gen_movi_tl(cpu_ov, 1);
6232 tcg_gen_movi_tl(cpu_so, 1);
6233 tcg_gen_br(l2);
6234 gen_set_label(l1);
6235 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
6236 gen_set_label(l2);
6237 tcg_temp_free(t0);
6238 tcg_temp_free(t1);
6239 tcg_temp_free(t2);
6240 if (unlikely(Rc(ctx->opcode) != 0)) {
6241 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
6242 }
6243 }
6244
6245 /* dozi */
6246 static void gen_dozi(DisasContext *ctx)
6247 {
6248 target_long simm = SIMM(ctx->opcode);
6249 TCGLabel *l1 = gen_new_label();
6250 TCGLabel *l2 = gen_new_label();
6251 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
6252 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
6253 tcg_gen_br(l2);
6254 gen_set_label(l1);
6255 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
6256 gen_set_label(l2);
6257 if (unlikely(Rc(ctx->opcode) != 0)) {
6258 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
6259 }
6260 }
6261
6262 /* lscbx - lscbx. */
6263 static void gen_lscbx(DisasContext *ctx)
6264 {
6265 TCGv t0 = tcg_temp_new();
6266 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
6267 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
6268 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
6269
6270 gen_addr_reg_index(ctx, t0);
6271 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
6272 tcg_temp_free_i32(t1);
6273 tcg_temp_free_i32(t2);
6274 tcg_temp_free_i32(t3);
6275 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
6276 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
6277 if (unlikely(Rc(ctx->opcode) != 0)) {
6278 gen_set_Rc0(ctx, t0);
6279 }
6280 tcg_temp_free(t0);
6281 }
6282
6283 /* maskg - maskg. */
6284 static void gen_maskg(DisasContext *ctx)
6285 {
6286 TCGLabel *l1 = gen_new_label();
6287 TCGv t0 = tcg_temp_new();
6288 TCGv t1 = tcg_temp_new();
6289 TCGv t2 = tcg_temp_new();
6290 TCGv t3 = tcg_temp_new();
6291 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
6292 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
6293 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
6294 tcg_gen_addi_tl(t2, t0, 1);
6295 tcg_gen_shr_tl(t2, t3, t2);
6296 tcg_gen_shr_tl(t3, t3, t1);
6297 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
6298 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
6299 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6300 gen_set_label(l1);
6301 tcg_temp_free(t0);
6302 tcg_temp_free(t1);
6303 tcg_temp_free(t2);
6304 tcg_temp_free(t3);
6305 if (unlikely(Rc(ctx->opcode) != 0)) {
6306 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6307 }
6308 }
6309
6310 /* maskir - maskir. */
6311 static void gen_maskir(DisasContext *ctx)
6312 {
6313 TCGv t0 = tcg_temp_new();
6314 TCGv t1 = tcg_temp_new();
6315 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6316 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6317 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
6318 tcg_temp_free(t0);
6319 tcg_temp_free(t1);
6320 if (unlikely(Rc(ctx->opcode) != 0)) {
6321 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6322 }
6323 }
6324
6325 /* mul - mul. */
6326 static void gen_mul(DisasContext *ctx)
6327 {
6328 TCGv_i64 t0 = tcg_temp_new_i64();
6329 TCGv_i64 t1 = tcg_temp_new_i64();
6330 TCGv t2 = tcg_temp_new();
6331 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
6332 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
6333 tcg_gen_mul_i64(t0, t0, t1);
6334 tcg_gen_trunc_i64_tl(t2, t0);
6335 gen_store_spr(SPR_MQ, t2);
6336 tcg_gen_shri_i64(t1, t0, 32);
6337 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
6338 tcg_temp_free_i64(t0);
6339 tcg_temp_free_i64(t1);
6340 tcg_temp_free(t2);
6341 if (unlikely(Rc(ctx->opcode) != 0)) {
6342 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
6343 }
6344 }
6345
6346 /* mulo - mulo. */
6347 static void gen_mulo(DisasContext *ctx)
6348 {
6349 TCGLabel *l1 = gen_new_label();
6350 TCGv_i64 t0 = tcg_temp_new_i64();
6351 TCGv_i64 t1 = tcg_temp_new_i64();
6352 TCGv t2 = tcg_temp_new();
6353 /* Start with XER OV disabled, the most likely case */
6354 tcg_gen_movi_tl(cpu_ov, 0);
6355 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
6356 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
6357 tcg_gen_mul_i64(t0, t0, t1);
6358 tcg_gen_trunc_i64_tl(t2, t0);
6359 gen_store_spr(SPR_MQ, t2);
6360 tcg_gen_shri_i64(t1, t0, 32);
6361 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
6362 tcg_gen_ext32s_i64(t1, t0);
6363 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
6364 tcg_gen_movi_tl(cpu_ov, 1);
6365 tcg_gen_movi_tl(cpu_so, 1);
6366 gen_set_label(l1);
6367 tcg_temp_free_i64(t0);
6368 tcg_temp_free_i64(t1);
6369 tcg_temp_free(t2);
6370 if (unlikely(Rc(ctx->opcode) != 0)) {
6371 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
6372 }
6373 }
6374
6375 /* nabs - nabs. */
6376 static void gen_nabs(DisasContext *ctx)
6377 {
6378 TCGv d = cpu_gpr[rD(ctx->opcode)];
6379 TCGv a = cpu_gpr[rA(ctx->opcode)];
6380
6381 tcg_gen_abs_tl(d, a);
6382 tcg_gen_neg_tl(d, d);
6383 if (unlikely(Rc(ctx->opcode) != 0)) {
6384 gen_set_Rc0(ctx, d);
6385 }
6386 }
6387
6388 /* nabso - nabso. */
6389 static void gen_nabso(DisasContext *ctx)
6390 {
6391 TCGv d = cpu_gpr[rD(ctx->opcode)];
6392 TCGv a = cpu_gpr[rA(ctx->opcode)];
6393
6394 tcg_gen_abs_tl(d, a);
6395 tcg_gen_neg_tl(d, d);
6396 /* nabs never overflows */
6397 tcg_gen_movi_tl(cpu_ov, 0);
6398 if (unlikely(Rc(ctx->opcode) != 0)) {
6399 gen_set_Rc0(ctx, d);
6400 }
6401 }
6402
6403 /* rlmi - rlmi. */
6404 static void gen_rlmi(DisasContext *ctx)
6405 {
6406 uint32_t mb = MB(ctx->opcode);
6407 uint32_t me = ME(ctx->opcode);
6408 TCGv t0 = tcg_temp_new();
6409 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
6410 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
6411 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
6412 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
6413 ~MASK(mb, me));
6414 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
6415 tcg_temp_free(t0);
6416 if (unlikely(Rc(ctx->opcode) != 0)) {
6417 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6418 }
6419 }
6420
6421 /* rrib - rrib. */
6422 static void gen_rrib(DisasContext *ctx)
6423 {
6424 TCGv t0 = tcg_temp_new();
6425 TCGv t1 = tcg_temp_new();
6426 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
6427 tcg_gen_movi_tl(t1, 0x80000000);
6428 tcg_gen_shr_tl(t1, t1, t0);
6429 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
6430 tcg_gen_and_tl(t0, t0, t1);
6431 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
6432 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
6433 tcg_temp_free(t0);
6434 tcg_temp_free(t1);
6435 if (unlikely(Rc(ctx->opcode) != 0)) {
6436 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6437 }
6438 }
6439
6440 /* sle - sle. */
6441 static void gen_sle(DisasContext *ctx)
6442 {
6443 TCGv t0 = tcg_temp_new();
6444 TCGv t1 = tcg_temp_new();
6445 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
6446 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
6447 tcg_gen_subfi_tl(t1, 32, t1);
6448 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
6449 tcg_gen_or_tl(t1, t0, t1);
6450 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
6451 gen_store_spr(SPR_MQ, t1);
6452 tcg_temp_free(t0);
6453 tcg_temp_free(t1);
6454 if (unlikely(Rc(ctx->opcode) != 0)) {
6455 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6456 }
6457 }
6458
6459 /* sleq - sleq. */
6460 static void gen_sleq(DisasContext *ctx)
6461 {
6462 TCGv t0 = tcg_temp_new();
6463 TCGv t1 = tcg_temp_new();
6464 TCGv t2 = tcg_temp_new();
6465 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
6466 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
6467 tcg_gen_shl_tl(t2, t2, t0);
6468 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
6469 gen_load_spr(t1, SPR_MQ);
6470 gen_store_spr(SPR_MQ, t0);
6471 tcg_gen_and_tl(t0, t0, t2);
6472 tcg_gen_andc_tl(t1, t1, t2);
6473 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
6474 tcg_temp_free(t0);
6475 tcg_temp_free(t1);
6476 tcg_temp_free(t2);
6477 if (unlikely(Rc(ctx->opcode) != 0)) {
6478 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6479 }
6480 }
6481
6482 /* sliq - sliq. */
6483 static void gen_sliq(DisasContext *ctx)
6484 {
6485 int sh = SH(ctx->opcode);
6486 TCGv t0 = tcg_temp_new();
6487 TCGv t1 = tcg_temp_new();
6488 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
6489 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
6490 tcg_gen_or_tl(t1, t0, t1);
6491 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
6492 gen_store_spr(SPR_MQ, t1);
6493 tcg_temp_free(t0);
6494 tcg_temp_free(t1);
6495 if (unlikely(Rc(ctx->opcode) != 0)) {
6496 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6497 }
6498 }
6499
6500 /* slliq - slliq. */
6501 static void gen_slliq(DisasContext *ctx)
6502 {
6503 int sh = SH(ctx->opcode);
6504 TCGv t0 = tcg_temp_new();
6505 TCGv t1 = tcg_temp_new();
6506 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
6507 gen_load_spr(t1, SPR_MQ);
6508 gen_store_spr(SPR_MQ, t0);
6509 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
6510 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
6511 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
6512 tcg_temp_free(t0);
6513 tcg_temp_free(t1);
6514 if (unlikely(Rc(ctx->opcode) != 0)) {
6515 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6516 }
6517 }
6518
6519 /* sllq - sllq. */
6520 static void gen_sllq(DisasContext *ctx)
6521 {
6522 TCGLabel *l1 = gen_new_label();
6523 TCGLabel *l2 = gen_new_label();
6524 TCGv t0 = tcg_temp_local_new();
6525 TCGv t1 = tcg_temp_local_new();
6526 TCGv t2 = tcg_temp_local_new();
6527 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
6528 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
6529 tcg_gen_shl_tl(t1, t1, t2);
6530 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
6531 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
6532 gen_load_spr(t0, SPR_MQ);
6533 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
6534 tcg_gen_br(l2);
6535 gen_set_label(l1);
6536 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
6537 gen_load_spr(t2, SPR_MQ);
6538 tcg_gen_andc_tl(t1, t2, t1);
6539 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
6540 gen_set_label(l2);
6541 tcg_temp_free(t0);
6542 tcg_temp_free(t1);
6543 tcg_temp_free(t2);
6544 if (unlikely(Rc(ctx->opcode) != 0)) {
6545 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6546 }
6547 }
6548
6549 /* slq - slq. */
6550 static void gen_slq(DisasContext *ctx)
6551 {
6552 TCGLabel *l1 = gen_new_label();
6553 TCGv t0 = tcg_temp_new();
6554 TCGv t1 = tcg_temp_new();
6555 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
6556 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
6557 tcg_gen_subfi_tl(t1, 32, t1);
6558 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
6559 tcg_gen_or_tl(t1, t0, t1);
6560 gen_store_spr(SPR_MQ, t1);
6561 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
6562 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
6563 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
6564 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
6565 gen_set_label(l1);
6566 tcg_temp_free(t0);
6567 tcg_temp_free(t1);
6568 if (unlikely(Rc(ctx->opcode) != 0)) {
6569 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6570 }
6571 }
6572
6573 /* sraiq - sraiq. */
6574 static void gen_sraiq(DisasContext *ctx)
6575 {
6576 int sh = SH(ctx->opcode);
6577 TCGLabel *l1 = gen_new_label();
6578 TCGv t0 = tcg_temp_new();
6579 TCGv t1 = tcg_temp_new();
6580 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
6581 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
6582 tcg_gen_or_tl(t0, t0, t1);
6583 gen_store_spr(SPR_MQ, t0);
6584 tcg_gen_movi_tl(cpu_ca, 0);
6585 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
6586 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
6587 tcg_gen_movi_tl(cpu_ca, 1);
6588 gen_set_label(l1);
6589 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
6590 tcg_temp_free(t0);
6591 tcg_temp_free(t1);
6592 if (unlikely(Rc(ctx->opcode) != 0)) {
6593 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6594 }
6595 }
6596
6597 /* sraq - sraq. */
6598 static void gen_sraq(DisasContext *ctx)
6599 {
6600 TCGLabel *l1 = gen_new_label();
6601 TCGLabel *l2 = gen_new_label();
6602 TCGv t0 = tcg_temp_new();
6603 TCGv t1 = tcg_temp_local_new();
6604 TCGv t2 = tcg_temp_local_new();
6605 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
6606 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
6607 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
6608 tcg_gen_subfi_tl(t2, 32, t2);
6609 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
6610 tcg_gen_or_tl(t0, t0, t2);
6611 gen_store_spr(SPR_MQ, t0);
6612 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
6613 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
6614 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
6615 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
6616 gen_set_label(l1);
6617 tcg_temp_free(t0);
6618 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
6619 tcg_gen_movi_tl(cpu_ca, 0);
6620 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
6621 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
6622 tcg_gen_movi_tl(cpu_ca, 1);
6623 gen_set_label(l2);
6624 tcg_temp_free(t1);
6625 tcg_temp_free(t2);
6626 if (unlikely(Rc(ctx->opcode) != 0)) {
6627 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6628 }
6629 }
6630
6631 /* sre - sre. */
6632 static void gen_sre(DisasContext *ctx)
6633 {
6634 TCGv t0 = tcg_temp_new();
6635 TCGv t1 = tcg_temp_new();
6636 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
6637 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
6638 tcg_gen_subfi_tl(t1, 32, t1);
6639 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
6640 tcg_gen_or_tl(t1, t0, t1);
6641 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
6642 gen_store_spr(SPR_MQ, t1);
6643 tcg_temp_free(t0);
6644 tcg_temp_free(t1);
6645 if (unlikely(Rc(ctx->opcode) != 0)) {
6646 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6647 }
6648 }
6649
6650 /* srea - srea. */
6651 static void gen_srea(DisasContext *ctx)
6652 {
6653 TCGv t0 = tcg_temp_new();
6654 TCGv t1 = tcg_temp_new();
6655 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
6656 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
6657 gen_store_spr(SPR_MQ, t0);
6658 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
6659 tcg_temp_free(t0);
6660 tcg_temp_free(t1);
6661 if (unlikely(Rc(ctx->opcode) != 0)) {
6662 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6663 }
6664 }
6665
6666 /* sreq */
6667 static void gen_sreq(DisasContext *ctx)
6668 {
6669 TCGv t0 = tcg_temp_new();
6670 TCGv t1 = tcg_temp_new();
6671 TCGv t2 = tcg_temp_new();
6672 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
6673 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
6674 tcg_gen_shr_tl(t1, t1, t0);
6675 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
6676 gen_load_spr(t2, SPR_MQ);
6677 gen_store_spr(SPR_MQ, t0);
6678 tcg_gen_and_tl(t0, t0, t1);
6679 tcg_gen_andc_tl(t2, t2, t1);
6680 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
6681 tcg_temp_free(t0);
6682 tcg_temp_free(t1);
6683 tcg_temp_free(t2);
6684 if (unlikely(Rc(ctx->opcode) != 0)) {
6685 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6686 }
6687 }
6688
6689 /* sriq */
6690 static void gen_sriq(DisasContext *ctx)
6691 {
6692 int sh = SH(ctx->opcode);
6693 TCGv t0 = tcg_temp_new();
6694 TCGv t1 = tcg_temp_new();
6695 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
6696 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
6697 tcg_gen_or_tl(t1, t0, t1);
6698 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
6699 gen_store_spr(SPR_MQ, t1);
6700 tcg_temp_free(t0);
6701 tcg_temp_free(t1);
6702 if (unlikely(Rc(ctx->opcode) != 0)) {
6703 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6704 }
6705 }
6706
6707 /* srliq */
6708 static void gen_srliq(DisasContext *ctx)
6709 {
6710 int sh = SH(ctx->opcode);
6711 TCGv t0 = tcg_temp_new();
6712 TCGv t1 = tcg_temp_new();
6713 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
6714 gen_load_spr(t1, SPR_MQ);
6715 gen_store_spr(SPR_MQ, t0);
6716 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
6717 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
6718 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
6719 tcg_temp_free(t0);
6720 tcg_temp_free(t1);
6721 if (unlikely(Rc(ctx->opcode) != 0)) {
6722 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6723 }
6724 }
6725
6726 /* srlq */
6727 static void gen_srlq(DisasContext *ctx)
6728 {
6729 TCGLabel *l1 = gen_new_label();
6730 TCGLabel *l2 = gen_new_label();
6731 TCGv t0 = tcg_temp_local_new();
6732 TCGv t1 = tcg_temp_local_new();
6733 TCGv t2 = tcg_temp_local_new();
6734 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
6735 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
6736 tcg_gen_shr_tl(t2, t1, t2);
6737 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
6738 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
6739 gen_load_spr(t0, SPR_MQ);
6740 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
6741 tcg_gen_br(l2);
6742 gen_set_label(l1);
6743 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
6744 tcg_gen_and_tl(t0, t0, t2);
6745 gen_load_spr(t1, SPR_MQ);
6746 tcg_gen_andc_tl(t1, t1, t2);
6747 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
6748 gen_set_label(l2);
6749 tcg_temp_free(t0);
6750 tcg_temp_free(t1);
6751 tcg_temp_free(t2);
6752 if (unlikely(Rc(ctx->opcode) != 0)) {
6753 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6754 }
6755 }
6756
6757 /* srq */
6758 static void gen_srq(DisasContext *ctx)
6759 {
6760 TCGLabel *l1 = gen_new_label();
6761 TCGv t0 = tcg_temp_new();
6762 TCGv t1 = tcg_temp_new();
6763 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
6764 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
6765 tcg_gen_subfi_tl(t1, 32, t1);
6766 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
6767 tcg_gen_or_tl(t1, t0, t1);
6768 gen_store_spr(SPR_MQ, t1);
6769 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
6770 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
6771 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
6772 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
6773 gen_set_label(l1);
6774 tcg_temp_free(t0);
6775 tcg_temp_free(t1);
6776 if (unlikely(Rc(ctx->opcode) != 0)) {
6777 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
6778 }
6779 }
6780
6781 /* PowerPC 602 specific instructions */
6782
6783 /* dsa */
6784 static void gen_dsa(DisasContext *ctx)
6785 {
6786 /* XXX: TODO */
6787 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6788 }
6789
6790 /* esa */
6791 static void gen_esa(DisasContext *ctx)
6792 {
6793 /* XXX: TODO */
6794 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6795 }
6796
6797 /* mfrom */
6798 static void gen_mfrom(DisasContext *ctx)
6799 {
6800 #if defined(CONFIG_USER_ONLY)
6801 GEN_PRIV;
6802 #else
6803 CHK_SV;
6804 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6805 #endif /* defined(CONFIG_USER_ONLY) */
6806 }
6807
6808 /* 602 - 603 - G2 TLB management */
6809
6810 /* tlbld */
6811 static void gen_tlbld_6xx(DisasContext *ctx)
6812 {
6813 #if defined(CONFIG_USER_ONLY)
6814 GEN_PRIV;
6815 #else
6816 CHK_SV;
6817 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6818 #endif /* defined(CONFIG_USER_ONLY) */
6819 }
6820
6821 /* tlbli */
6822 static void gen_tlbli_6xx(DisasContext *ctx)
6823 {
6824 #if defined(CONFIG_USER_ONLY)
6825 GEN_PRIV;
6826 #else
6827 CHK_SV;
6828 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6829 #endif /* defined(CONFIG_USER_ONLY) */
6830 }
6831
6832 /* 74xx TLB management */
6833
6834 /* tlbld */
6835 static void gen_tlbld_74xx(DisasContext *ctx)
6836 {
6837 #if defined(CONFIG_USER_ONLY)
6838 GEN_PRIV;
6839 #else
6840 CHK_SV;
6841 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6842 #endif /* defined(CONFIG_USER_ONLY) */
6843 }
6844
6845 /* tlbli */
6846 static void gen_tlbli_74xx(DisasContext *ctx)
6847 {
6848 #if defined(CONFIG_USER_ONLY)
6849 GEN_PRIV;
6850 #else
6851 CHK_SV;
6852 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6853 #endif /* defined(CONFIG_USER_ONLY) */
6854 }
6855
6856 /* POWER instructions not in PowerPC 601 */
6857
6858 /* clf */
6859 static void gen_clf(DisasContext *ctx)
6860 {
6861 /* Cache line flush: implemented as no-op */
6862 }
6863
6864 /* cli */
6865 static void gen_cli(DisasContext *ctx)
6866 {
6867 #if defined(CONFIG_USER_ONLY)
6868 GEN_PRIV;
6869 #else
6870 /* Cache line invalidate: privileged and treated as no-op */
6871 CHK_SV;
6872 #endif /* defined(CONFIG_USER_ONLY) */
6873 }
6874
6875 /* dclst */
6876 static void gen_dclst(DisasContext *ctx)
6877 {
6878 /* Data cache line store: treated as no-op */
6879 }
6880
6881 static void gen_mfsri(DisasContext *ctx)
6882 {
6883 #if defined(CONFIG_USER_ONLY)
6884 GEN_PRIV;
6885 #else
6886 int ra = rA(ctx->opcode);
6887 int rd = rD(ctx->opcode);
6888 TCGv t0;
6889
6890 CHK_SV;
6891 t0 = tcg_temp_new();
6892 gen_addr_reg_index(ctx, t0);
6893 tcg_gen_extract_tl(t0, t0, 28, 4);
6894 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
6895 tcg_temp_free(t0);
6896 if (ra != 0 && ra != rd) {
6897 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
6898 }
6899 #endif /* defined(CONFIG_USER_ONLY) */
6900 }
6901
6902 static void gen_rac(DisasContext *ctx)
6903 {
6904 #if defined(CONFIG_USER_ONLY)
6905 GEN_PRIV;
6906 #else
6907 TCGv t0;
6908
6909 CHK_SV;
6910 t0 = tcg_temp_new();
6911 gen_addr_reg_index(ctx, t0);
6912 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6913 tcg_temp_free(t0);
6914 #endif /* defined(CONFIG_USER_ONLY) */
6915 }
6916
6917 static void gen_rfsvc(DisasContext *ctx)
6918 {
6919 #if defined(CONFIG_USER_ONLY)
6920 GEN_PRIV;
6921 #else
6922 CHK_SV;
6923
6924 gen_helper_rfsvc(cpu_env);
6925 gen_sync_exception(ctx);
6926 #endif /* defined(CONFIG_USER_ONLY) */
6927 }
6928
6929 /* svc is not implemented for now */
6930
6931 /* BookE specific instructions */
6932
6933 /* XXX: not implemented on 440 ? */
6934 static void gen_mfapidi(DisasContext *ctx)
6935 {
6936 /* XXX: TODO */
6937 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6938 }
6939
6940 /* XXX: not implemented on 440 ? */
6941 static void gen_tlbiva(DisasContext *ctx)
6942 {
6943 #if defined(CONFIG_USER_ONLY)
6944 GEN_PRIV;
6945 #else
6946 TCGv t0;
6947
6948 CHK_SV;
6949 t0 = tcg_temp_new();
6950 gen_addr_reg_index(ctx, t0);
6951 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6952 tcg_temp_free(t0);
6953 #endif /* defined(CONFIG_USER_ONLY) */
6954 }
6955
6956 /* All 405 MAC instructions are translated here */
6957 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
6958 int ra, int rb, int rt, int Rc)
6959 {
6960 TCGv t0, t1;
6961
6962 t0 = tcg_temp_local_new();
6963 t1 = tcg_temp_local_new();
6964
6965 switch (opc3 & 0x0D) {
6966 case 0x05:
6967 /* macchw - macchw. - macchwo - macchwo. */
6968 /* macchws - macchws. - macchwso - macchwso. */
6969 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
6970 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
6971 /* mulchw - mulchw. */
6972 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
6973 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
6974 tcg_gen_ext16s_tl(t1, t1);
6975 break;
6976 case 0x04:
6977 /* macchwu - macchwu. - macchwuo - macchwuo. */
6978 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
6979 /* mulchwu - mulchwu. */
6980 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
6981 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
6982 tcg_gen_ext16u_tl(t1, t1);
6983 break;
6984 case 0x01:
6985 /* machhw - machhw. - machhwo - machhwo. */
6986 /* machhws - machhws. - machhwso - machhwso. */
6987 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
6988 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
6989 /* mulhhw - mulhhw. */
6990 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
6991 tcg_gen_ext16s_tl(t0, t0);
6992 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
6993 tcg_gen_ext16s_tl(t1, t1);
6994 break;
6995 case 0x00:
6996 /* machhwu - machhwu. - machhwuo - machhwuo. */
6997 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
6998 /* mulhhwu - mulhhwu. */
6999 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
7000 tcg_gen_ext16u_tl(t0, t0);
7001 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
7002 tcg_gen_ext16u_tl(t1, t1);
7003 break;
7004 case 0x0D:
7005 /* maclhw - maclhw. - maclhwo - maclhwo. */
7006 /* maclhws - maclhws. - maclhwso - maclhwso. */
7007 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
7008 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
7009 /* mullhw - mullhw. */
7010 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
7011 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
7012 break;
7013 case 0x0C:
7014 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
7015 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
7016 /* mullhwu - mullhwu. */
7017 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
7018 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
7019 break;
7020 }
7021 if (opc2 & 0x04) {
7022 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
7023 tcg_gen_mul_tl(t1, t0, t1);
7024 if (opc2 & 0x02) {
7025 /* nmultiply-and-accumulate (0x0E) */
7026 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
7027 } else {
7028 /* multiply-and-accumulate (0x0C) */
7029 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
7030 }
7031
7032 if (opc3 & 0x12) {
7033 /* Check overflow and/or saturate */
7034 TCGLabel *l1 = gen_new_label();
7035
7036 if (opc3 & 0x10) {
7037 /* Start with XER OV disabled, the most likely case */
7038 tcg_gen_movi_tl(cpu_ov, 0);
7039 }
7040 if (opc3 & 0x01) {
7041 /* Signed */
7042 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
7043 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
7044 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
7045 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
7046 if (opc3 & 0x02) {
7047 /* Saturate */
7048 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
7049 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
7050 }
7051 } else {
7052 /* Unsigned */
7053 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
7054 if (opc3 & 0x02) {
7055 /* Saturate */
7056 tcg_gen_movi_tl(t0, UINT32_MAX);
7057 }
7058 }
7059 if (opc3 & 0x10) {
7060 /* Check overflow */
7061 tcg_gen_movi_tl(cpu_ov, 1);
7062 tcg_gen_movi_tl(cpu_so, 1);
7063 }
7064 gen_set_label(l1);
7065 tcg_gen_mov_tl(cpu_gpr[rt], t0);
7066 }
7067 } else {
7068 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
7069 }
7070 tcg_temp_free(t0);
7071 tcg_temp_free(t1);
7072 if (unlikely(Rc) != 0) {
7073 /* Update Rc0 */
7074 gen_set_Rc0(ctx, cpu_gpr[rt]);
7075 }
7076 }
7077
7078 #define GEN_MAC_HANDLER(name, opc2, opc3) \
7079 static void glue(gen_, name)(DisasContext *ctx) \
7080 { \
7081 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
7082 rD(ctx->opcode), Rc(ctx->opcode)); \
7083 }
7084
7085 /* macchw - macchw. */
7086 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
7087 /* macchwo - macchwo. */
7088 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
7089 /* macchws - macchws. */
7090 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
7091 /* macchwso - macchwso. */
7092 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
7093 /* macchwsu - macchwsu. */
7094 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
7095 /* macchwsuo - macchwsuo. */
7096 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
7097 /* macchwu - macchwu. */
7098 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
7099 /* macchwuo - macchwuo. */
7100 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
7101 /* machhw - machhw. */
7102 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
7103 /* machhwo - machhwo. */
7104 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
7105 /* machhws - machhws. */
7106 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
7107 /* machhwso - machhwso. */
7108 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
7109 /* machhwsu - machhwsu. */
7110 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
7111 /* machhwsuo - machhwsuo. */
7112 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
7113 /* machhwu - machhwu. */
7114 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
7115 /* machhwuo - machhwuo. */
7116 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
7117 /* maclhw - maclhw. */
7118 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
7119 /* maclhwo - maclhwo. */
7120 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
7121 /* maclhws - maclhws. */
7122 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
7123 /* maclhwso - maclhwso. */
7124 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
7125 /* maclhwu - maclhwu. */
7126 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
7127 /* maclhwuo - maclhwuo. */
7128 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
7129 /* maclhwsu - maclhwsu. */
7130 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
7131 /* maclhwsuo - maclhwsuo. */
7132 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
7133 /* nmacchw - nmacchw. */
7134 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
7135 /* nmacchwo - nmacchwo. */
7136 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
7137 /* nmacchws - nmacchws. */
7138 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
7139 /* nmacchwso - nmacchwso. */
7140 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
7141 /* nmachhw - nmachhw. */
7142 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
7143 /* nmachhwo - nmachhwo. */
7144 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
7145 /* nmachhws - nmachhws. */
7146 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
7147 /* nmachhwso - nmachhwso. */
7148 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
7149 /* nmaclhw - nmaclhw. */
7150 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
7151 /* nmaclhwo - nmaclhwo. */
7152 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
7153 /* nmaclhws - nmaclhws. */
7154 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
7155 /* nmaclhwso - nmaclhwso. */
7156 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
7157
7158 /* mulchw - mulchw. */
7159 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
7160 /* mulchwu - mulchwu. */
7161 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
7162 /* mulhhw - mulhhw. */
7163 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
7164 /* mulhhwu - mulhhwu. */
7165 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
7166 /* mullhw - mullhw. */
7167 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
7168 /* mullhwu - mullhwu. */
7169 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
7170
7171 /* mfdcr */
7172 static void gen_mfdcr(DisasContext *ctx)
7173 {
7174 #if defined(CONFIG_USER_ONLY)
7175 GEN_PRIV;
7176 #else
7177 TCGv dcrn;
7178
7179 CHK_SV;
7180 dcrn = tcg_const_tl(SPR(ctx->opcode));
7181 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
7182 tcg_temp_free(dcrn);
7183 #endif /* defined(CONFIG_USER_ONLY) */
7184 }
7185
7186 /* mtdcr */
7187 static void gen_mtdcr(DisasContext *ctx)
7188 {
7189 #if defined(CONFIG_USER_ONLY)
7190 GEN_PRIV;
7191 #else
7192 TCGv dcrn;
7193
7194 CHK_SV;
7195 dcrn = tcg_const_tl(SPR(ctx->opcode));
7196 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
7197 tcg_temp_free(dcrn);
7198 #endif /* defined(CONFIG_USER_ONLY) */
7199 }
7200
7201 /* mfdcrx */
7202 /* XXX: not implemented on 440 ? */
7203 static void gen_mfdcrx(DisasContext *ctx)
7204 {
7205 #if defined(CONFIG_USER_ONLY)
7206 GEN_PRIV;
7207 #else
7208 CHK_SV;
7209 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
7210 cpu_gpr[rA(ctx->opcode)]);
7211 /* Note: Rc update flag set leads to undefined state of Rc0 */
7212 #endif /* defined(CONFIG_USER_ONLY) */
7213 }
7214
7215 /* mtdcrx */
7216 /* XXX: not implemented on 440 ? */
7217 static void gen_mtdcrx(DisasContext *ctx)
7218 {
7219 #if defined(CONFIG_USER_ONLY)
7220 GEN_PRIV;
7221 #else
7222 CHK_SV;
7223 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
7224 cpu_gpr[rS(ctx->opcode)]);
7225 /* Note: Rc update flag set leads to undefined state of Rc0 */
7226 #endif /* defined(CONFIG_USER_ONLY) */
7227 }
7228
7229 /* mfdcrux (PPC 460) : user-mode access to DCR */
7230 static void gen_mfdcrux(DisasContext *ctx)
7231 {
7232 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
7233 cpu_gpr[rA(ctx->opcode)]);
7234 /* Note: Rc update flag set leads to undefined state of Rc0 */
7235 }
7236
7237 /* mtdcrux (PPC 460) : user-mode access to DCR */
7238 static void gen_mtdcrux(DisasContext *ctx)
7239 {
7240 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
7241 cpu_gpr[rS(ctx->opcode)]);
7242 /* Note: Rc update flag set leads to undefined state of Rc0 */
7243 }
7244
7245 /* dccci */
7246 static void gen_dccci(DisasContext *ctx)
7247 {
7248 CHK_SV;
7249 /* interpreted as no-op */
7250 }
7251
7252 /* dcread */
7253 static void gen_dcread(DisasContext *ctx)
7254 {
7255 #if defined(CONFIG_USER_ONLY)
7256 GEN_PRIV;
7257 #else
7258 TCGv EA, val;
7259
7260 CHK_SV;
7261 gen_set_access_type(ctx, ACCESS_CACHE);
7262 EA = tcg_temp_new();
7263 gen_addr_reg_index(ctx, EA);
7264 val = tcg_temp_new();
7265 gen_qemu_ld32u(ctx, val, EA);
7266 tcg_temp_free(val);
7267 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
7268 tcg_temp_free(EA);
7269 #endif /* defined(CONFIG_USER_ONLY) */
7270 }
7271
7272 /* icbt */
7273 static void gen_icbt_40x(DisasContext *ctx)
7274 {
7275 /*
7276 * interpreted as no-op
7277 * XXX: specification say this is treated as a load by the MMU but
7278 * does not generate any exception
7279 */
7280 }
7281
7282 /* iccci */
7283 static void gen_iccci(DisasContext *ctx)
7284 {
7285 CHK_SV;
7286 /* interpreted as no-op */
7287 }
7288
7289 /* icread */
7290 static void gen_icread(DisasContext *ctx)
7291 {
7292 CHK_SV;
7293 /* interpreted as no-op */
7294 }
7295
7296 /* rfci (supervisor only) */
7297 static void gen_rfci_40x(DisasContext *ctx)
7298 {
7299 #if defined(CONFIG_USER_ONLY)
7300 GEN_PRIV;
7301 #else
7302 CHK_SV;
7303 /* Restore CPU state */
7304 gen_helper_40x_rfci(cpu_env);
7305 gen_sync_exception(ctx);
7306 #endif /* defined(CONFIG_USER_ONLY) */
7307 }
7308
7309 static void gen_rfci(DisasContext *ctx)
7310 {
7311 #if defined(CONFIG_USER_ONLY)
7312 GEN_PRIV;
7313 #else
7314 CHK_SV;
7315 /* Restore CPU state */
7316 gen_helper_rfci(cpu_env);
7317 gen_sync_exception(ctx);
7318 #endif /* defined(CONFIG_USER_ONLY) */
7319 }
7320
7321 /* BookE specific */
7322
7323 /* XXX: not implemented on 440 ? */
7324 static void gen_rfdi(DisasContext *ctx)
7325 {
7326 #if defined(CONFIG_USER_ONLY)
7327 GEN_PRIV;
7328 #else
7329 CHK_SV;
7330 /* Restore CPU state */
7331 gen_helper_rfdi(cpu_env);
7332 gen_sync_exception(ctx);
7333 #endif /* defined(CONFIG_USER_ONLY) */
7334 }
7335
7336 /* XXX: not implemented on 440 ? */
7337 static void gen_rfmci(DisasContext *ctx)
7338 {
7339 #if defined(CONFIG_USER_ONLY)
7340 GEN_PRIV;
7341 #else
7342 CHK_SV;
7343 /* Restore CPU state */
7344 gen_helper_rfmci(cpu_env);
7345 gen_sync_exception(ctx);
7346 #endif /* defined(CONFIG_USER_ONLY) */
7347 }
7348
7349 /* TLB management - PowerPC 405 implementation */
7350
7351 /* tlbre */
7352 static void gen_tlbre_40x(DisasContext *ctx)
7353 {
7354 #if defined(CONFIG_USER_ONLY)
7355 GEN_PRIV;
7356 #else
7357 CHK_SV;
7358 switch (rB(ctx->opcode)) {
7359 case 0:
7360 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
7361 cpu_gpr[rA(ctx->opcode)]);
7362 break;
7363 case 1:
7364 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
7365 cpu_gpr[rA(ctx->opcode)]);
7366 break;
7367 default:
7368 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
7369 break;
7370 }
7371 #endif /* defined(CONFIG_USER_ONLY) */
7372 }
7373
7374 /* tlbsx - tlbsx. */
7375 static void gen_tlbsx_40x(DisasContext *ctx)
7376 {
7377 #if defined(CONFIG_USER_ONLY)
7378 GEN_PRIV;
7379 #else
7380 TCGv t0;
7381
7382 CHK_SV;
7383 t0 = tcg_temp_new();
7384 gen_addr_reg_index(ctx, t0);
7385 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
7386 tcg_temp_free(t0);
7387 if (Rc(ctx->opcode)) {
7388 TCGLabel *l1 = gen_new_label();
7389 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
7390 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
7391 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
7392 gen_set_label(l1);
7393 }
7394 #endif /* defined(CONFIG_USER_ONLY) */
7395 }
7396
7397 /* tlbwe */
7398 static void gen_tlbwe_40x(DisasContext *ctx)
7399 {
7400 #if defined(CONFIG_USER_ONLY)
7401 GEN_PRIV;
7402 #else
7403 CHK_SV;
7404
7405 switch (rB(ctx->opcode)) {
7406 case 0:
7407 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
7408 cpu_gpr[rS(ctx->opcode)]);
7409 break;
7410 case 1:
7411 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
7412 cpu_gpr[rS(ctx->opcode)]);
7413 break;
7414 default:
7415 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
7416 break;
7417 }
7418 #endif /* defined(CONFIG_USER_ONLY) */
7419 }
7420
7421 /* TLB management - PowerPC 440 implementation */
7422
7423 /* tlbre */
7424 static void gen_tlbre_440(DisasContext *ctx)
7425 {
7426 #if defined(CONFIG_USER_ONLY)
7427 GEN_PRIV;
7428 #else
7429 CHK_SV;
7430
7431 switch (rB(ctx->opcode)) {
7432 case 0:
7433 case 1:
7434 case 2:
7435 {
7436 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
7437 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
7438 t0, cpu_gpr[rA(ctx->opcode)]);
7439 tcg_temp_free_i32(t0);
7440 }
7441 break;
7442 default:
7443 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
7444 break;
7445 }
7446 #endif /* defined(CONFIG_USER_ONLY) */
7447 }
7448
7449 /* tlbsx - tlbsx. */
7450 static void gen_tlbsx_440(DisasContext *ctx)
7451 {
7452 #if defined(CONFIG_USER_ONLY)
7453 GEN_PRIV;
7454 #else
7455 TCGv t0;
7456
7457 CHK_SV;
7458 t0 = tcg_temp_new();
7459 gen_addr_reg_index(ctx, t0);
7460 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
7461 tcg_temp_free(t0);
7462 if (Rc(ctx->opcode)) {
7463 TCGLabel *l1 = gen_new_label();
7464 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
7465 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
7466 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
7467 gen_set_label(l1);
7468 }
7469 #endif /* defined(CONFIG_USER_ONLY) */
7470 }
7471
7472 /* tlbwe */
7473 static void gen_tlbwe_440(DisasContext *ctx)
7474 {
7475 #if defined(CONFIG_USER_ONLY)
7476 GEN_PRIV;
7477 #else
7478 CHK_SV;
7479 switch (rB(ctx->opcode)) {
7480 case 0:
7481 case 1:
7482 case 2:
7483 {
7484 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
7485 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
7486 cpu_gpr[rS(ctx->opcode)]);
7487 tcg_temp_free_i32(t0);
7488 }
7489 break;
7490 default:
7491 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
7492 break;
7493 }
7494 #endif /* defined(CONFIG_USER_ONLY) */
7495 }
7496
7497 /* TLB management - PowerPC BookE 2.06 implementation */
7498
7499 /* tlbre */
7500 static void gen_tlbre_booke206(DisasContext *ctx)
7501 {
7502 #if defined(CONFIG_USER_ONLY)
7503 GEN_PRIV;
7504 #else
7505 CHK_SV;
7506 gen_helper_booke206_tlbre(cpu_env);
7507 #endif /* defined(CONFIG_USER_ONLY) */
7508 }
7509
7510 /* tlbsx - tlbsx. */
7511 static void gen_tlbsx_booke206(DisasContext *ctx)
7512 {
7513 #if defined(CONFIG_USER_ONLY)
7514 GEN_PRIV;
7515 #else
7516 TCGv t0;
7517
7518 CHK_SV;
7519 if (rA(ctx->opcode)) {
7520 t0 = tcg_temp_new();
7521 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
7522 } else {
7523 t0 = tcg_const_tl(0);
7524 }
7525
7526 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
7527 gen_helper_booke206_tlbsx(cpu_env, t0);
7528 tcg_temp_free(t0);
7529 #endif /* defined(CONFIG_USER_ONLY) */
7530 }
7531
7532 /* tlbwe */
7533 static void gen_tlbwe_booke206(DisasContext *ctx)
7534 {
7535 #if defined(CONFIG_USER_ONLY)
7536 GEN_PRIV;
7537 #else
7538 CHK_SV;
7539 gen_helper_booke206_tlbwe(cpu_env);
7540 #endif /* defined(CONFIG_USER_ONLY) */
7541 }
7542
7543 static void gen_tlbivax_booke206(DisasContext *ctx)
7544 {
7545 #if defined(CONFIG_USER_ONLY)
7546 GEN_PRIV;
7547 #else
7548 TCGv t0;
7549
7550 CHK_SV;
7551 t0 = tcg_temp_new();
7552 gen_addr_reg_index(ctx, t0);
7553 gen_helper_booke206_tlbivax(cpu_env, t0);
7554 tcg_temp_free(t0);
7555 #endif /* defined(CONFIG_USER_ONLY) */
7556 }
7557
7558 static void gen_tlbilx_booke206(DisasContext *ctx)
7559 {
7560 #if defined(CONFIG_USER_ONLY)
7561 GEN_PRIV;
7562 #else
7563 TCGv t0;
7564
7565 CHK_SV;
7566 t0 = tcg_temp_new();
7567 gen_addr_reg_index(ctx, t0);
7568
7569 switch ((ctx->opcode >> 21) & 0x3) {
7570 case 0:
7571 gen_helper_booke206_tlbilx0(cpu_env, t0);
7572 break;
7573 case 1:
7574 gen_helper_booke206_tlbilx1(cpu_env, t0);
7575 break;
7576 case 3:
7577 gen_helper_booke206_tlbilx3(cpu_env, t0);
7578 break;
7579 default:
7580 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
7581 break;
7582 }
7583
7584 tcg_temp_free(t0);
7585 #endif /* defined(CONFIG_USER_ONLY) */
7586 }
7587
7588
7589 /* wrtee */
7590 static void gen_wrtee(DisasContext *ctx)
7591 {
7592 #if defined(CONFIG_USER_ONLY)
7593 GEN_PRIV;
7594 #else
7595 TCGv t0;
7596
7597 CHK_SV;
7598 t0 = tcg_temp_new();
7599 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
7600 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
7601 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
7602 tcg_temp_free(t0);
7603 /*
7604 * Stop translation to have a chance to raise an exception if we
7605 * just set msr_ee to 1
7606 */
7607 gen_stop_exception(ctx);
7608 #endif /* defined(CONFIG_USER_ONLY) */
7609 }
7610
7611 /* wrteei */
7612 static void gen_wrteei(DisasContext *ctx)
7613 {
7614 #if defined(CONFIG_USER_ONLY)
7615 GEN_PRIV;
7616 #else
7617 CHK_SV;
7618 if (ctx->opcode & 0x00008000) {
7619 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
7620 /* Stop translation to have a chance to raise an exception */
7621 gen_stop_exception(ctx);
7622 } else {
7623 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
7624 }
7625 #endif /* defined(CONFIG_USER_ONLY) */
7626 }
7627
7628 /* PowerPC 440 specific instructions */
7629
7630 /* dlmzb */
7631 static void gen_dlmzb(DisasContext *ctx)
7632 {
7633 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
7634 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
7635 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
7636 tcg_temp_free_i32(t0);
7637 }
7638
7639 /* mbar replaces eieio on 440 */
7640 static void gen_mbar(DisasContext *ctx)
7641 {
7642 /* interpreted as no-op */
7643 }
7644
7645 /* msync replaces sync on 440 */
7646 static void gen_msync_4xx(DisasContext *ctx)
7647 {
7648 /* Only e500 seems to treat reserved bits as invalid */
7649 if ((ctx->insns_flags2 & PPC2_BOOKE206) &&
7650 (ctx->opcode & 0x03FFF801)) {
7651 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
7652 }
7653 /* otherwise interpreted as no-op */
7654 }
7655
7656 /* icbt */
7657 static void gen_icbt_440(DisasContext *ctx)
7658 {
7659 /*
7660 * interpreted as no-op
7661 * XXX: specification say this is treated as a load by the MMU but
7662 * does not generate any exception
7663 */
7664 }
7665
7666 /* Embedded.Processor Control */
7667
7668 static void gen_msgclr(DisasContext *ctx)
7669 {
7670 #if defined(CONFIG_USER_ONLY)
7671 GEN_PRIV;
7672 #else
7673 CHK_HV;
7674 if (is_book3s_arch2x(ctx)) {
7675 gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
7676 } else {
7677 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
7678 }
7679 #endif /* defined(CONFIG_USER_ONLY) */
7680 }
7681
7682 static void gen_msgsnd(DisasContext *ctx)
7683 {
7684 #if defined(CONFIG_USER_ONLY)
7685 GEN_PRIV;
7686 #else
7687 CHK_HV;
7688 if (is_book3s_arch2x(ctx)) {
7689 gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]);
7690 } else {
7691 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
7692 }
7693 #endif /* defined(CONFIG_USER_ONLY) */
7694 }
7695
7696 #if defined(TARGET_PPC64)
7697 static void gen_msgclrp(DisasContext *ctx)
7698 {
7699 #if defined(CONFIG_USER_ONLY)
7700 GEN_PRIV;
7701 #else
7702 CHK_SV;
7703 gen_helper_book3s_msgclrp(cpu_env, cpu_gpr[rB(ctx->opcode)]);
7704 #endif /* defined(CONFIG_USER_ONLY) */
7705 }
7706
7707 static void gen_msgsndp(DisasContext *ctx)
7708 {
7709 #if defined(CONFIG_USER_ONLY)
7710 GEN_PRIV;
7711 #else
7712 CHK_SV;
7713 gen_helper_book3s_msgsndp(cpu_env, cpu_gpr[rB(ctx->opcode)]);
7714 #endif /* defined(CONFIG_USER_ONLY) */
7715 }
7716 #endif
7717
7718 static void gen_msgsync(DisasContext *ctx)
7719 {
7720 #if defined(CONFIG_USER_ONLY)
7721 GEN_PRIV;
7722 #else
7723 CHK_HV;
7724 #endif /* defined(CONFIG_USER_ONLY) */
7725 /* interpreted as no-op */
7726 }
7727
7728 #if defined(TARGET_PPC64)
7729 static void gen_maddld(DisasContext *ctx)
7730 {
7731 TCGv_i64 t1 = tcg_temp_new_i64();
7732
7733 tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7734 tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]);
7735 tcg_temp_free_i64(t1);
7736 }
7737
7738 /* maddhd maddhdu */
7739 static void gen_maddhd_maddhdu(DisasContext *ctx)
7740 {
7741 TCGv_i64 lo = tcg_temp_new_i64();
7742 TCGv_i64 hi = tcg_temp_new_i64();
7743 TCGv_i64 t1 = tcg_temp_new_i64();
7744
7745 if (Rc(ctx->opcode)) {
7746 tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
7747 cpu_gpr[rB(ctx->opcode)]);
7748 tcg_gen_movi_i64(t1, 0);
7749 } else {
7750 tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
7751 cpu_gpr[rB(ctx->opcode)]);
7752 tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63);
7753 }
7754 tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi,
7755 cpu_gpr[rC(ctx->opcode)], t1);
7756 tcg_temp_free_i64(lo);
7757 tcg_temp_free_i64(hi);
7758 tcg_temp_free_i64(t1);
7759 }
7760 #endif /* defined(TARGET_PPC64) */
7761
7762 static void gen_tbegin(DisasContext *ctx)
7763 {
7764 if (unlikely(!ctx->tm_enabled)) {
7765 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
7766 return;
7767 }
7768 gen_helper_tbegin(cpu_env);
7769 }
7770
7771 #define GEN_TM_NOOP(name) \
7772 static inline void gen_##name(DisasContext *ctx) \
7773 { \
7774 if (unlikely(!ctx->tm_enabled)) { \
7775 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
7776 return; \
7777 } \
7778 /* \
7779 * Because tbegin always fails in QEMU, these user \
7780 * space instructions all have a simple implementation: \
7781 * \
7782 * CR[0] = 0b0 || MSR[TS] || 0b0 \
7783 * = 0b0 || 0b00 || 0b0 \
7784 */ \
7785 tcg_gen_movi_i32(cpu_crf[0], 0); \
7786 }
7787
7788 GEN_TM_NOOP(tend);
7789 GEN_TM_NOOP(tabort);
7790 GEN_TM_NOOP(tabortwc);
7791 GEN_TM_NOOP(tabortwci);
7792 GEN_TM_NOOP(tabortdc);
7793 GEN_TM_NOOP(tabortdci);
7794 GEN_TM_NOOP(tsr);
7795
7796 static inline void gen_cp_abort(DisasContext *ctx)
7797 {
7798 /* Do Nothing */
7799 }
7800
7801 #define GEN_CP_PASTE_NOOP(name) \
7802 static inline void gen_##name(DisasContext *ctx) \
7803 { \
7804 /* \
7805 * Generate invalid exception until we have an \
7806 * implementation of the copy paste facility \
7807 */ \
7808 gen_invalid(ctx); \
7809 }
7810
7811 GEN_CP_PASTE_NOOP(copy)
7812 GEN_CP_PASTE_NOOP(paste)
7813
7814 static void gen_tcheck(DisasContext *ctx)
7815 {
7816 if (unlikely(!ctx->tm_enabled)) {
7817 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
7818 return;
7819 }
7820 /*
7821 * Because tbegin always fails, the tcheck implementation is
7822 * simple:
7823 *
7824 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
7825 * = 0b1 || 0b00 || 0b0
7826 */
7827 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
7828 }
7829
7830 #if defined(CONFIG_USER_ONLY)
7831 #define GEN_TM_PRIV_NOOP(name) \
7832 static inline void gen_##name(DisasContext *ctx) \
7833 { \
7834 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
7835 }
7836
7837 #else
7838
7839 #define GEN_TM_PRIV_NOOP(name) \
7840 static inline void gen_##name(DisasContext *ctx) \
7841 { \
7842 CHK_SV; \
7843 if (unlikely(!ctx->tm_enabled)) { \
7844 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
7845 return; \
7846 } \
7847 /* \
7848 * Because tbegin always fails, the implementation is \
7849 * simple: \
7850 * \
7851 * CR[0] = 0b0 || MSR[TS] || 0b0 \
7852 * = 0b0 || 0b00 | 0b0 \
7853 */ \
7854 tcg_gen_movi_i32(cpu_crf[0], 0); \
7855 }
7856
7857 #endif
7858
7859 GEN_TM_PRIV_NOOP(treclaim);
7860 GEN_TM_PRIV_NOOP(trechkpt);
7861
7862 static inline void get_fpr(TCGv_i64 dst, int regno)
7863 {
7864 tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno));
7865 }
7866
7867 static inline void set_fpr(int regno, TCGv_i64 src)
7868 {
7869 tcg_gen_st_i64(src, cpu_env, fpr_offset(regno));
7870 }
7871
7872 static inline void get_avr64(TCGv_i64 dst, int regno, bool high)
7873 {
7874 tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high));
7875 }
7876
7877 static inline void set_avr64(int regno, TCGv_i64 src, bool high)
7878 {
7879 tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high));
7880 }
7881
7882 #include "translate/fp-impl.c.inc"
7883
7884 #include "translate/vmx-impl.c.inc"
7885
7886 #include "translate/vsx-impl.c.inc"
7887
7888 #include "translate/dfp-impl.c.inc"
7889
7890 #include "translate/spe-impl.c.inc"
7891
7892 /* Handles lfdp, lxsd, lxssp */
7893 static void gen_dform39(DisasContext *ctx)
7894 {
7895 switch (ctx->opcode & 0x3) {
7896 case 0: /* lfdp */
7897 if (ctx->insns_flags2 & PPC2_ISA205) {
7898 return gen_lfdp(ctx);
7899 }
7900 break;
7901 case 2: /* lxsd */
7902 if (ctx->insns_flags2 & PPC2_ISA300) {
7903 return gen_lxsd(ctx);
7904 }
7905 break;
7906 case 3: /* lxssp */
7907 if (ctx->insns_flags2 & PPC2_ISA300) {
7908 return gen_lxssp(ctx);
7909 }
7910 break;
7911 }
7912 return gen_invalid(ctx);
7913 }
7914
7915 /* handles stfdp, lxv, stxsd, stxssp lxvx */
7916 static void gen_dform3D(DisasContext *ctx)
7917 {
7918 if ((ctx->opcode & 3) == 1) { /* DQ-FORM */
7919 switch (ctx->opcode & 0x7) {
7920 case 1: /* lxv */
7921 if (ctx->insns_flags2 & PPC2_ISA300) {
7922 return gen_lxv(ctx);
7923 }
7924 break;
7925 case 5: /* stxv */
7926 if (ctx->insns_flags2 & PPC2_ISA300) {
7927 return gen_stxv(ctx);
7928 }
7929 break;
7930 }
7931 } else { /* DS-FORM */
7932 switch (ctx->opcode & 0x3) {
7933 case 0: /* stfdp */
7934 if (ctx->insns_flags2 & PPC2_ISA205) {
7935 return gen_stfdp(ctx);
7936 }
7937 break;
7938 case 2: /* stxsd */
7939 if (ctx->insns_flags2 & PPC2_ISA300) {
7940 return gen_stxsd(ctx);
7941 }
7942 break;
7943 case 3: /* stxssp */
7944 if (ctx->insns_flags2 & PPC2_ISA300) {
7945 return gen_stxssp(ctx);
7946 }
7947 break;
7948 }
7949 }
7950 return gen_invalid(ctx);
7951 }
7952
7953 #if defined(TARGET_PPC64)
7954 /* brd */
7955 static void gen_brd(DisasContext *ctx)
7956 {
7957 tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
7958 }
7959
7960 /* brw */
7961 static void gen_brw(DisasContext *ctx)
7962 {
7963 tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
7964 tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32);
7965
7966 }
7967
7968 /* brh */
7969 static void gen_brh(DisasContext *ctx)
7970 {
7971 TCGv_i64 t0 = tcg_temp_new_i64();
7972 TCGv_i64 t1 = tcg_temp_new_i64();
7973 TCGv_i64 t2 = tcg_temp_new_i64();
7974
7975 tcg_gen_movi_i64(t0, 0x00ff00ff00ff00ffull);
7976 tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8);
7977 tcg_gen_and_i64(t2, t1, t0);
7978 tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], t0);
7979 tcg_gen_shli_i64(t1, t1, 8);
7980 tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2);
7981
7982 tcg_temp_free_i64(t0);
7983 tcg_temp_free_i64(t1);
7984 tcg_temp_free_i64(t2);
7985 }
7986 #endif
7987
7988 static opcode_t opcodes[] = {
7989 #if defined(TARGET_PPC64)
7990 GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310),
7991 GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310),
7992 GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310),
7993 #endif
7994 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
7995 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
7996 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
7997 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER),
7998 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
7999 #if defined(TARGET_PPC64)
8000 GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300),
8001 #endif
8002 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
8003 GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
8004 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
8005 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8006 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8007 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8008 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8009 GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
8010 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
8011 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
8012 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
8013 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
8014 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8015 #if defined(TARGET_PPC64)
8016 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
8017 #endif
8018 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
8019 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
8020 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8021 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8022 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8023 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
8024 GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300),
8025 GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300),
8026 GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
8027 GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300),
8028 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
8029 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
8030 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8031 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8032 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8033 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8034 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
8035 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
8036 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
8037 #if defined(TARGET_PPC64)
8038 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
8039 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
8040 GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300),
8041 GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300),
8042 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
8043 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
8044 #endif
8045 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8046 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8047 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8048 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
8049 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
8050 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
8051 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
8052 #if defined(TARGET_PPC64)
8053 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
8054 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
8055 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
8056 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
8057 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
8058 GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000,
8059 PPC_NONE, PPC2_ISA300),
8060 GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000,
8061 PPC_NONE, PPC2_ISA300),
8062 #endif
8063 #if defined(TARGET_PPC64)
8064 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
8065 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
8066 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
8067 #endif
8068 /* handles lfdp, lxsd, lxssp */
8069 GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
8070 /* handles stfdp, lxv, stxsd, stxssp, stxv */
8071 GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
8072 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8073 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8074 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
8075 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
8076 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
8077 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
8078 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO),
8079 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
8080 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
8081 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
8082 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
8083 GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300),
8084 GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300),
8085 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
8086 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
8087 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
8088 #if defined(TARGET_PPC64)
8089 GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300),
8090 GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300),
8091 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
8092 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
8093 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
8094 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
8095 #endif
8096 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
8097 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
8098 GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300),
8099 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8100 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8101 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
8102 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
8103 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207),
8104 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
8105 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
8106 #if defined(TARGET_PPC64)
8107 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
8108 #if !defined(CONFIG_USER_ONLY)
8109 /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */
8110 GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300),
8111 GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300),
8112 GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300),
8113 #endif
8114 GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300),
8115 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
8116 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
8117 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
8118 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
8119 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
8120 #endif
8121 /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */
8122 GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW),
8123 GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW),
8124 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
8125 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8126 #if defined(TARGET_PPC64)
8127 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
8128 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
8129 #endif
8130 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
8131 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
8132 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
8133 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
8134 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
8135 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
8136 #if defined(TARGET_PPC64)
8137 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
8138 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300),
8139 GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300),
8140 #endif
8141 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC),
8142 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
8143 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
8144 GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206),
8145 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
8146 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
8147 GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206),
8148 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
8149 GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206),
8150 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
8151 GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206),
8152 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
8153 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
8154 GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206),
8155 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
8156 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC),
8157 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
8158 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
8159 GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206),
8160 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
8161 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
8162 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
8163 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
8164 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
8165 #if defined(TARGET_PPC64)
8166 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
8167 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
8168 PPC_SEGMENT_64B),
8169 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
8170 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
8171 PPC_SEGMENT_64B),
8172 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
8173 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
8174 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
8175 GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B),
8176 #endif
8177 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
8178 /*
8179 * XXX Those instructions will need to be handled differently for
8180 * different ISA versions
8181 */
8182 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE),
8183 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE),
8184 GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300),
8185 GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300),
8186 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
8187 #if defined(TARGET_PPC64)
8188 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
8189 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
8190 GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300),
8191 GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
8192 #endif
8193 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
8194 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
8195 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
8196 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
8197 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
8198 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
8199 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
8200 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
8201 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
8202 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
8203 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
8204 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8205 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
8206 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
8207 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
8208 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
8209 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
8210 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
8211 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
8212 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8213 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
8214 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
8215 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
8216 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
8217 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
8218 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
8219 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
8220 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
8221 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
8222 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
8223 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
8224 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
8225 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
8226 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
8227 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
8228 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
8229 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
8230 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
8231 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
8232 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
8233 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
8234 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
8235 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
8236 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
8237 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
8238 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
8239 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
8240 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
8241 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
8242 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8243 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8244 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
8245 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
8246 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8247 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8248 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
8249 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
8250 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
8251 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
8252 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
8253 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
8254 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
8255 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
8256 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
8257 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
8258 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
8259 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
8260 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
8261 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
8262 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
8263 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
8264 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
8265 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
8266 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
8267 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
8268 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
8269 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
8270 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
8271 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
8272 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
8273 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
8274 PPC_NONE, PPC2_BOOKE206),
8275 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
8276 PPC_NONE, PPC2_BOOKE206),
8277 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
8278 PPC_NONE, PPC2_BOOKE206),
8279 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
8280 PPC_NONE, PPC2_BOOKE206),
8281 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
8282 PPC_NONE, PPC2_BOOKE206),
8283 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
8284 PPC_NONE, PPC2_PRCNTL),
8285 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
8286 PPC_NONE, PPC2_PRCNTL),
8287 GEN_HANDLER2_E(msgsync, "msgsync", 0x1F, 0x16, 0x1B, 0x00000000,
8288 PPC_NONE, PPC2_PRCNTL),
8289 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
8290 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
8291 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
8292 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
8293 PPC_BOOKE, PPC2_BOOKE206),
8294 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE),
8295 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
8296 PPC_BOOKE, PPC2_BOOKE206),
8297 GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001,
8298 PPC_440_SPEC),
8299 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
8300 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
8301 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
8302 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
8303 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
8304 #if defined(TARGET_PPC64)
8305 GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE,
8306 PPC2_ISA300),
8307 GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
8308 GEN_HANDLER2_E(msgsndp, "msgsndp", 0x1F, 0x0E, 0x04, 0x03ff0001,
8309 PPC_NONE, PPC2_ISA207S),
8310 GEN_HANDLER2_E(msgclrp, "msgclrp", 0x1F, 0x0E, 0x05, 0x03ff0001,
8311 PPC_NONE, PPC2_ISA207S),
8312 #endif
8313
8314 #undef GEN_INT_ARITH_ADD
8315 #undef GEN_INT_ARITH_ADD_CONST
8316 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
8317 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
8318 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
8319 add_ca, compute_ca, compute_ov) \
8320 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
8321 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
8322 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
8323 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
8324 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
8325 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
8326 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
8327 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
8328 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
8329 GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300),
8330 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
8331 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
8332
8333 #undef GEN_INT_ARITH_DIVW
8334 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
8335 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
8336 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
8337 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
8338 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
8339 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
8340 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
8341 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
8342 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
8343 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
8344 GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
8345 GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
8346
8347 #if defined(TARGET_PPC64)
8348 #undef GEN_INT_ARITH_DIVD
8349 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
8350 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8351 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
8352 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
8353 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
8354 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
8355
8356 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
8357 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
8358 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
8359 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
8360 GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
8361 GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
8362
8363 #undef GEN_INT_ARITH_MUL_HELPER
8364 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
8365 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8366 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
8367 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
8368 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
8369 #endif
8370
8371 #undef GEN_INT_ARITH_SUBF
8372 #undef GEN_INT_ARITH_SUBF_CONST
8373 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
8374 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
8375 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
8376 add_ca, compute_ca, compute_ov) \
8377 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
8378 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
8379 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
8380 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
8381 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
8382 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
8383 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
8384 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
8385 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
8386 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
8387 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
8388
8389 #undef GEN_LOGICAL1
8390 #undef GEN_LOGICAL2
8391 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
8392 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
8393 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
8394 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
8395 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
8396 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
8397 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
8398 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
8399 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
8400 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
8401 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
8402 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
8403 #if defined(TARGET_PPC64)
8404 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
8405 #endif
8406
8407 #if defined(TARGET_PPC64)
8408 #undef GEN_PPC64_R2
8409 #undef GEN_PPC64_R4
8410 #define GEN_PPC64_R2(name, opc1, opc2) \
8411 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8412 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8413 PPC_64B)
8414 #define GEN_PPC64_R4(name, opc1, opc2) \
8415 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8416 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
8417 PPC_64B), \
8418 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8419 PPC_64B), \
8420 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
8421 PPC_64B)
8422 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
8423 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
8424 GEN_PPC64_R4(rldic, 0x1E, 0x04),
8425 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
8426 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
8427 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
8428 #endif
8429
8430 #undef GEN_LD
8431 #undef GEN_LDU
8432 #undef GEN_LDUX
8433 #undef GEN_LDX_E
8434 #undef GEN_LDS
8435 #define GEN_LD(name, ldop, opc, type) \
8436 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8437 #define GEN_LDU(name, ldop, opc, type) \
8438 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8439 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
8440 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8441 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
8442 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
8443 #define GEN_LDS(name, ldop, op, type) \
8444 GEN_LD(name, ldop, op | 0x20, type) \
8445 GEN_LDU(name, ldop, op | 0x21, type) \
8446 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
8447 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
8448
8449 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
8450 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
8451 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
8452 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
8453 #if defined(TARGET_PPC64)
8454 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
8455 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
8456 GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B)
8457 GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B)
8458 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE)
8459
8460 /* HV/P7 and later only */
8461 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
8462 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST)
8463 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
8464 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
8465 #endif
8466 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
8467 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
8468
8469 /* External PID based load */
8470 #undef GEN_LDEPX
8471 #define GEN_LDEPX(name, ldop, opc2, opc3) \
8472 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \
8473 0x00000001, PPC_NONE, PPC2_BOOKE206),
8474
8475 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02)
8476 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08)
8477 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00)
8478 #if defined(TARGET_PPC64)
8479 GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00)
8480 #endif
8481
8482 #undef GEN_ST
8483 #undef GEN_STU
8484 #undef GEN_STUX
8485 #undef GEN_STX_E
8486 #undef GEN_STS
8487 #define GEN_ST(name, stop, opc, type) \
8488 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8489 #define GEN_STU(name, stop, opc, type) \
8490 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
8491 #define GEN_STUX(name, stop, opc2, opc3, type) \
8492 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8493 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
8494 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2),
8495 #define GEN_STS(name, stop, op, type) \
8496 GEN_ST(name, stop, op | 0x20, type) \
8497 GEN_STU(name, stop, op | 0x21, type) \
8498 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
8499 GEN_STX(name, stop, 0x17, op | 0x00, type)
8500
8501 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
8502 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
8503 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
8504 #if defined(TARGET_PPC64)
8505 GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B)
8506 GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B)
8507 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE)
8508 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
8509 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
8510 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
8511 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
8512 #endif
8513 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
8514 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
8515
8516 #undef GEN_STEPX
8517 #define GEN_STEPX(name, ldop, opc2, opc3) \
8518 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \
8519 0x00000001, PPC_NONE, PPC2_BOOKE206),
8520
8521 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06)
8522 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C)
8523 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04)
8524 #if defined(TARGET_PPC64)
8525 GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1D, 0x04)
8526 #endif
8527
8528 #undef GEN_CRLOGIC
8529 #define GEN_CRLOGIC(name, tcg_op, opc) \
8530 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
8531 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
8532 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
8533 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
8534 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
8535 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
8536 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
8537 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
8538 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
8539
8540 #undef GEN_MAC_HANDLER
8541 #define GEN_MAC_HANDLER(name, opc2, opc3) \
8542 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
8543 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
8544 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
8545 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
8546 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
8547 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
8548 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
8549 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
8550 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
8551 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
8552 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
8553 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
8554 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
8555 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
8556 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
8557 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
8558 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
8559 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
8560 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
8561 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
8562 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
8563 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
8564 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
8565 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
8566 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
8567 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
8568 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
8569 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
8570 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
8571 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
8572 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
8573 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
8574 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
8575 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
8576 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
8577 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
8578 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
8579 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
8580 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
8581 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
8582 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
8583 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
8584 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
8585
8586 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
8587 PPC_NONE, PPC2_TM),
8588 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
8589 PPC_NONE, PPC2_TM),
8590 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
8591 PPC_NONE, PPC2_TM),
8592 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
8593 PPC_NONE, PPC2_TM),
8594 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
8595 PPC_NONE, PPC2_TM),
8596 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
8597 PPC_NONE, PPC2_TM),
8598 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
8599 PPC_NONE, PPC2_TM),
8600 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
8601 PPC_NONE, PPC2_TM),
8602 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
8603 PPC_NONE, PPC2_TM),
8604 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
8605 PPC_NONE, PPC2_TM),
8606 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
8607 PPC_NONE, PPC2_TM),
8608
8609 #include "translate/fp-ops.c.inc"
8610
8611 #include "translate/vmx-ops.c.inc"
8612
8613 #include "translate/vsx-ops.c.inc"
8614
8615 #include "translate/dfp-ops.c.inc"
8616
8617 #include "translate/spe-ops.c.inc"
8618 };
8619
8620 /*****************************************************************************/
8621 /* Opcode types */
8622 enum {
8623 PPC_DIRECT = 0, /* Opcode routine */
8624 PPC_INDIRECT = 1, /* Indirect opcode table */
8625 };
8626
8627 #define PPC_OPCODE_MASK 0x3
8628
8629 static inline int is_indirect_opcode(void *handler)
8630 {
8631 return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT;
8632 }
8633
8634 static inline opc_handler_t **ind_table(void *handler)
8635 {
8636 return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK);
8637 }
8638
8639 /* Instruction table creation */
8640 /* Opcodes tables creation */
8641 static void fill_new_table(opc_handler_t **table, int len)
8642 {
8643 int i;
8644
8645 for (i = 0; i < len; i++) {
8646 table[i] = &invalid_handler;
8647 }
8648 }
8649
8650 static int create_new_table(opc_handler_t **table, unsigned char idx)
8651 {
8652 opc_handler_t **tmp;
8653
8654 tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN);
8655 fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN);
8656 table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT);
8657
8658 return 0;
8659 }
8660
8661 static int insert_in_table(opc_handler_t **table, unsigned char idx,
8662 opc_handler_t *handler)
8663 {
8664 if (table[idx] != &invalid_handler) {
8665 return -1;
8666 }
8667 table[idx] = handler;
8668
8669 return 0;
8670 }
8671
8672 static int register_direct_insn(opc_handler_t **ppc_opcodes,
8673 unsigned char idx, opc_handler_t *handler)
8674 {
8675 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
8676 printf("*** ERROR: opcode %02x already assigned in main "
8677 "opcode table\n", idx);
8678 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
8679 printf(" Registered handler '%s' - new handler '%s'\n",
8680 ppc_opcodes[idx]->oname, handler->oname);
8681 #endif
8682 return -1;
8683 }
8684
8685 return 0;
8686 }
8687
8688 static int register_ind_in_table(opc_handler_t **table,
8689 unsigned char idx1, unsigned char idx2,
8690 opc_handler_t *handler)
8691 {
8692 if (table[idx1] == &invalid_handler) {
8693 if (create_new_table(table, idx1) < 0) {
8694 printf("*** ERROR: unable to create indirect table "
8695 "idx=%02x\n", idx1);
8696 return -1;
8697 }
8698 } else {
8699 if (!is_indirect_opcode(table[idx1])) {
8700 printf("*** ERROR: idx %02x already assigned to a direct "
8701 "opcode\n", idx1);
8702 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
8703 printf(" Registered handler '%s' - new handler '%s'\n",
8704 ind_table(table[idx1])[idx2]->oname, handler->oname);
8705 #endif
8706 return -1;
8707 }
8708 }
8709 if (handler != NULL &&
8710 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
8711 printf("*** ERROR: opcode %02x already assigned in "
8712 "opcode table %02x\n", idx2, idx1);
8713 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
8714 printf(" Registered handler '%s' - new handler '%s'\n",
8715 ind_table(table[idx1])[idx2]->oname, handler->oname);
8716 #endif
8717 return -1;
8718 }
8719
8720 return 0;
8721 }
8722
8723 static int register_ind_insn(opc_handler_t **ppc_opcodes,
8724 unsigned char idx1, unsigned char idx2,
8725 opc_handler_t *handler)
8726 {
8727 return register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
8728 }
8729
8730 static int register_dblind_insn(opc_handler_t **ppc_opcodes,
8731 unsigned char idx1, unsigned char idx2,
8732 unsigned char idx3, opc_handler_t *handler)
8733 {
8734 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
8735 printf("*** ERROR: unable to join indirect table idx "
8736 "[%02x-%02x]\n", idx1, idx2);
8737 return -1;
8738 }
8739 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
8740 handler) < 0) {
8741 printf("*** ERROR: unable to insert opcode "
8742 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
8743 return -1;
8744 }
8745
8746 return 0;
8747 }
8748
8749 static int register_trplind_insn(opc_handler_t **ppc_opcodes,
8750 unsigned char idx1, unsigned char idx2,
8751 unsigned char idx3, unsigned char idx4,
8752 opc_handler_t *handler)
8753 {
8754 opc_handler_t **table;
8755
8756 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
8757 printf("*** ERROR: unable to join indirect table idx "
8758 "[%02x-%02x]\n", idx1, idx2);
8759 return -1;
8760 }
8761 table = ind_table(ppc_opcodes[idx1]);
8762 if (register_ind_in_table(table, idx2, idx3, NULL) < 0) {
8763 printf("*** ERROR: unable to join 2nd-level indirect table idx "
8764 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
8765 return -1;
8766 }
8767 table = ind_table(table[idx2]);
8768 if (register_ind_in_table(table, idx3, idx4, handler) < 0) {
8769 printf("*** ERROR: unable to insert opcode "
8770 "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4);
8771 return -1;
8772 }
8773 return 0;
8774 }
8775 static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn)
8776 {
8777 if (insn->opc2 != 0xFF) {
8778 if (insn->opc3 != 0xFF) {
8779 if (insn->opc4 != 0xFF) {
8780 if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2,
8781 insn->opc3, insn->opc4,
8782 &insn->handler) < 0) {
8783 return -1;
8784 }
8785 } else {
8786 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
8787 insn->opc3, &insn->handler) < 0) {
8788 return -1;
8789 }
8790 }
8791 } else {
8792 if (register_ind_insn(ppc_opcodes, insn->opc1,
8793 insn->opc2, &insn->handler) < 0) {
8794 return -1;
8795 }
8796 }
8797 } else {
8798 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) {
8799 return -1;
8800 }
8801 }
8802
8803 return 0;
8804 }
8805
8806 static int test_opcode_table(opc_handler_t **table, int len)
8807 {
8808 int i, count, tmp;
8809
8810 for (i = 0, count = 0; i < len; i++) {
8811 /* Consistency fixup */
8812 if (table[i] == NULL) {
8813 table[i] = &invalid_handler;
8814 }
8815 if (table[i] != &invalid_handler) {
8816 if (is_indirect_opcode(table[i])) {
8817 tmp = test_opcode_table(ind_table(table[i]),
8818 PPC_CPU_INDIRECT_OPCODES_LEN);
8819 if (tmp == 0) {
8820 free(table[i]);
8821 table[i] = &invalid_handler;
8822 } else {
8823 count++;
8824 }
8825 } else {
8826 count++;
8827 }
8828 }
8829 }
8830
8831 return count;
8832 }
8833
8834 static void fix_opcode_tables(opc_handler_t **ppc_opcodes)
8835 {
8836 if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) {
8837 printf("*** WARNING: no opcode defined !\n");
8838 }
8839 }
8840
8841 /*****************************************************************************/
8842 void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp)
8843 {
8844 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8845 opcode_t *opc;
8846
8847 fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN);
8848 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
8849 if (((opc->handler.type & pcc->insns_flags) != 0) ||
8850 ((opc->handler.type2 & pcc->insns_flags2) != 0)) {
8851 if (register_insn(cpu->opcodes, opc) < 0) {
8852 error_setg(errp, "ERROR initializing PowerPC instruction "
8853 "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2,
8854 opc->opc3);
8855 return;
8856 }
8857 }
8858 }
8859 fix_opcode_tables(cpu->opcodes);
8860 fflush(stdout);
8861 fflush(stderr);
8862 }
8863
8864 void destroy_ppc_opcodes(PowerPCCPU *cpu)
8865 {
8866 opc_handler_t **table, **table_2;
8867 int i, j, k;
8868
8869 for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) {
8870 if (cpu->opcodes[i] == &invalid_handler) {
8871 continue;
8872 }
8873 if (is_indirect_opcode(cpu->opcodes[i])) {
8874 table = ind_table(cpu->opcodes[i]);
8875 for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) {
8876 if (table[j] == &invalid_handler) {
8877 continue;
8878 }
8879 if (is_indirect_opcode(table[j])) {
8880 table_2 = ind_table(table[j]);
8881 for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) {
8882 if (table_2[k] != &invalid_handler &&
8883 is_indirect_opcode(table_2[k])) {
8884 g_free((opc_handler_t *)((uintptr_t)table_2[k] &
8885 ~PPC_INDIRECT));
8886 }
8887 }
8888 g_free((opc_handler_t *)((uintptr_t)table[j] &
8889 ~PPC_INDIRECT));
8890 }
8891 }
8892 g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] &
8893 ~PPC_INDIRECT));
8894 }
8895 }
8896 }
8897
8898 #if defined(PPC_DUMP_CPU)
8899 static void dump_ppc_insns(CPUPPCState *env)
8900 {
8901 opc_handler_t **table, *handler;
8902 const char *p, *q;
8903 uint8_t opc1, opc2, opc3, opc4;
8904
8905 printf("Instructions set:\n");
8906 /* opc1 is 6 bits long */
8907 for (opc1 = 0x00; opc1 < PPC_CPU_OPCODES_LEN; opc1++) {
8908 table = env->opcodes;
8909 handler = table[opc1];
8910 if (is_indirect_opcode(handler)) {
8911 /* opc2 is 5 bits long */
8912 for (opc2 = 0; opc2 < PPC_CPU_INDIRECT_OPCODES_LEN; opc2++) {
8913 table = env->opcodes;
8914 handler = env->opcodes[opc1];
8915 table = ind_table(handler);
8916 handler = table[opc2];
8917 if (is_indirect_opcode(handler)) {
8918 table = ind_table(handler);
8919 /* opc3 is 5 bits long */
8920 for (opc3 = 0; opc3 < PPC_CPU_INDIRECT_OPCODES_LEN;
8921 opc3++) {
8922 handler = table[opc3];
8923 if (is_indirect_opcode(handler)) {
8924 table = ind_table(handler);
8925 /* opc4 is 5 bits long */
8926 for (opc4 = 0; opc4 < PPC_CPU_INDIRECT_OPCODES_LEN;
8927 opc4++) {
8928 handler = table[opc4];
8929 if (handler->handler != &gen_invalid) {
8930 printf("INSN: %02x %02x %02x %02x -- "
8931 "(%02d %04d %02d) : %s\n",
8932 opc1, opc2, opc3, opc4,
8933 opc1, (opc3 << 5) | opc2, opc4,
8934 handler->oname);
8935 }
8936 }
8937 } else {
8938 if (handler->handler != &gen_invalid) {
8939 /* Special hack to properly dump SPE insns */
8940 p = strchr(handler->oname, '_');
8941 if (p == NULL) {
8942 printf("INSN: %02x %02x %02x (%02d %04d) : "
8943 "%s\n",
8944 opc1, opc2, opc3, opc1,
8945 (opc3 << 5) | opc2,
8946 handler->oname);
8947 } else {
8948 q = "speundef";
8949 if ((p - handler->oname) != strlen(q)
8950 || (memcmp(handler->oname, q, strlen(q))
8951 != 0)) {
8952 /* First instruction */
8953 printf("INSN: %02x %02x %02x"
8954 "(%02d %04d) : %.*s\n",
8955 opc1, opc2 << 1, opc3, opc1,
8956 (opc3 << 6) | (opc2 << 1),
8957 (int)(p - handler->oname),
8958 handler->oname);
8959 }
8960 if (strcmp(p + 1, q) != 0) {
8961 /* Second instruction */
8962 printf("INSN: %02x %02x %02x "
8963 "(%02d %04d) : %s\n", opc1,
8964 (opc2 << 1) | 1, opc3, opc1,
8965 (opc3 << 6) | (opc2 << 1) | 1,
8966 p + 1);
8967 }
8968 }
8969 }
8970 }
8971 }
8972 } else {
8973 if (handler->handler != &gen_invalid) {
8974 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
8975 opc1, opc2, opc1, opc2, handler->oname);
8976 }
8977 }
8978 }
8979 } else {
8980 if (handler->handler != &gen_invalid) {
8981 printf("INSN: %02x -- -- (%02d ----) : %s\n",
8982 opc1, opc1, handler->oname);
8983 }
8984 }
8985 }
8986 }
8987 #endif
8988 int ppc_fixup_cpu(PowerPCCPU *cpu)
8989 {
8990 CPUPPCState *env = &cpu->env;
8991
8992 /*
8993 * TCG doesn't (yet) emulate some groups of instructions that are
8994 * implemented on some otherwise supported CPUs (e.g. VSX and
8995 * decimal floating point instructions on POWER7). We remove
8996 * unsupported instruction groups from the cpu state's instruction
8997 * masks and hope the guest can cope. For at least the pseries
8998 * machine, the unavailability of these instructions can be
8999 * advertised to the guest via the device tree.
9000 */
9001 if ((env->insns_flags & ~PPC_TCG_INSNS)
9002 || (env->insns_flags2 & ~PPC_TCG_INSNS2)) {
9003 warn_report("Disabling some instructions which are not "
9004 "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")",
9005 env->insns_flags & ~PPC_TCG_INSNS,
9006 env->insns_flags2 & ~PPC_TCG_INSNS2);
9007 }
9008 env->insns_flags &= PPC_TCG_INSNS;
9009 env->insns_flags2 &= PPC_TCG_INSNS2;
9010 return 0;
9011 }
9012
9013
9014 void ppc_cpu_dump_statistics(CPUState *cs, int flags)
9015 {
9016 #if defined(DO_PPC_STATISTICS)
9017 PowerPCCPU *cpu = POWERPC_CPU(cs);
9018 opc_handler_t **t1, **t2, **t3, *handler;
9019 int op1, op2, op3;
9020
9021 t1 = cpu->env.opcodes;
9022 for (op1 = 0; op1 < 64; op1++) {
9023 handler = t1[op1];
9024 if (is_indirect_opcode(handler)) {
9025 t2 = ind_table(handler);
9026 for (op2 = 0; op2 < 32; op2++) {
9027 handler = t2[op2];
9028 if (is_indirect_opcode(handler)) {
9029 t3 = ind_table(handler);
9030 for (op3 = 0; op3 < 32; op3++) {
9031 handler = t3[op3];
9032 if (handler->count == 0) {
9033 continue;
9034 }
9035 qemu_printf("%02x %02x %02x (%02x %04d) %16s: "
9036 "%016" PRIx64 " %" PRId64 "\n",
9037 op1, op2, op3, op1, (op3 << 5) | op2,
9038 handler->oname,
9039 handler->count, handler->count);
9040 }
9041 } else {
9042 if (handler->count == 0) {
9043 continue;
9044 }
9045 qemu_printf("%02x %02x (%02x %04d) %16s: "
9046 "%016" PRIx64 " %" PRId64 "\n",
9047 op1, op2, op1, op2, handler->oname,
9048 handler->count, handler->count);
9049 }
9050 }
9051 } else {
9052 if (handler->count == 0) {
9053 continue;
9054 }
9055 qemu_printf("%02x (%02x ) %16s: %016" PRIx64
9056 " %" PRId64 "\n",
9057 op1, op1, handler->oname,
9058 handler->count, handler->count);
9059 }
9060 }
9061 #endif
9062 }
9063
9064 static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
9065 {
9066 DisasContext *ctx = container_of(dcbase, DisasContext, base);
9067 CPUPPCState *env = cs->env_ptr;
9068 uint32_t hflags = ctx->base.tb->flags;
9069 int bound;
9070
9071 ctx->exception = POWERPC_EXCP_NONE;
9072 ctx->spr_cb = env->spr_cb;
9073 ctx->pr = (hflags >> HFLAGS_PR) & 1;
9074 ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7;
9075 ctx->dr = (hflags >> HFLAGS_DR) & 1;
9076 ctx->hv = (hflags >> HFLAGS_HV) & 1;
9077 ctx->insns_flags = env->insns_flags;
9078 ctx->insns_flags2 = env->insns_flags2;
9079 ctx->access_type = -1;
9080 ctx->need_access_type = !mmu_is_64bit(env->mmu_model);
9081 ctx->le_mode = (hflags >> HFLAGS_LE) & 1;
9082 ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE;
9083 ctx->flags = env->flags;
9084 #if defined(TARGET_PPC64)
9085 ctx->sf_mode = (hflags >> HFLAGS_64) & 1;
9086 ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
9087 #endif
9088 ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B
9089 || env->mmu_model == POWERPC_MMU_601
9090 || env->mmu_model & POWERPC_MMU_64;
9091
9092 ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1;
9093 ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1;
9094 ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1;
9095 ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1;
9096 ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1;
9097 ctx->gtse = (hflags >> HFLAGS_GTSE) & 1;
9098
9099 ctx->singlestep_enabled = 0;
9100 if ((hflags >> HFLAGS_SE) & 1) {
9101 ctx->singlestep_enabled |= CPU_SINGLE_STEP;
9102 }
9103 if ((hflags >> HFLAGS_BE) & 1) {
9104 ctx->singlestep_enabled |= CPU_BRANCH_STEP;
9105 }
9106 if (unlikely(ctx->base.singlestep_enabled)) {
9107 ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP;
9108 }
9109
9110 bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;
9111 ctx->base.max_insns = MIN(ctx->base.max_insns, bound);
9112 }
9113
9114 static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs)
9115 {
9116 }
9117
9118 static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
9119 {
9120 tcg_gen_insn_start(dcbase->pc_next);
9121 }
9122
9123 static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs,
9124 const CPUBreakpoint *bp)
9125 {
9126 DisasContext *ctx = container_of(dcbase, DisasContext, base);
9127
9128 gen_debug_exception(ctx);
9129 dcbase->is_jmp = DISAS_NORETURN;
9130 /*
9131 * The address covered by the breakpoint must be included in
9132 * [tb->pc, tb->pc + tb->size) in order to for it to be properly
9133 * cleared -- thus we increment the PC here so that the logic
9134 * setting tb->size below does the right thing.
9135 */
9136 ctx->base.pc_next += 4;
9137 return true;
9138 }
9139
9140 static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
9141 {
9142 DisasContext *ctx = container_of(dcbase, DisasContext, base);
9143 PowerPCCPU *cpu = POWERPC_CPU(cs);
9144 CPUPPCState *env = cs->env_ptr;
9145 opc_handler_t **table, *handler;
9146
9147 LOG_DISAS("----------------\n");
9148 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
9149 ctx->base.pc_next, ctx->mem_idx, (int)msr_ir);
9150
9151 ctx->opcode = translator_ldl_swap(env, ctx->base.pc_next,
9152 need_byteswap(ctx));
9153
9154 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n",
9155 ctx->opcode, opc1(ctx->opcode), opc2(ctx->opcode),
9156 opc3(ctx->opcode), opc4(ctx->opcode),
9157 ctx->le_mode ? "little" : "big");
9158 ctx->base.pc_next += 4;
9159 table = cpu->opcodes;
9160 handler = table[opc1(ctx->opcode)];
9161 if (is_indirect_opcode(handler)) {
9162 table = ind_table(handler);
9163 handler = table[opc2(ctx->opcode)];
9164 if (is_indirect_opcode(handler)) {
9165 table = ind_table(handler);
9166 handler = table[opc3(ctx->opcode)];
9167 if (is_indirect_opcode(handler)) {
9168 table = ind_table(handler);
9169 handler = table[opc4(ctx->opcode)];
9170 }
9171 }
9172 }
9173 /* Is opcode *REALLY* valid ? */
9174 if (unlikely(handler->handler == &gen_invalid)) {
9175 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
9176 "%02x - %02x - %02x - %02x (%08x) "
9177 TARGET_FMT_lx " %d\n",
9178 opc1(ctx->opcode), opc2(ctx->opcode),
9179 opc3(ctx->opcode), opc4(ctx->opcode),
9180 ctx->opcode, ctx->base.pc_next - 4, (int)msr_ir);
9181 } else {
9182 uint32_t inval;
9183
9184 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE)
9185 && Rc(ctx->opcode))) {
9186 inval = handler->inval2;
9187 } else {
9188 inval = handler->inval1;
9189 }
9190
9191 if (unlikely((ctx->opcode & inval) != 0)) {
9192 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
9193 "%02x - %02x - %02x - %02x (%08x) "
9194 TARGET_FMT_lx "\n", ctx->opcode & inval,
9195 opc1(ctx->opcode), opc2(ctx->opcode),
9196 opc3(ctx->opcode), opc4(ctx->opcode),
9197 ctx->opcode, ctx->base.pc_next - 4);
9198 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
9199 ctx->base.is_jmp = DISAS_NORETURN;
9200 return;
9201 }
9202 }
9203 (*(handler->handler))(ctx);
9204 #if defined(DO_PPC_STATISTICS)
9205 handler->count++;
9206 #endif
9207 /* Check trace mode exceptions */
9208 if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP &&
9209 (ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) &&
9210 ctx->exception != POWERPC_SYSCALL &&
9211 ctx->exception != POWERPC_EXCP_TRAP &&
9212 ctx->exception != POWERPC_EXCP_BRANCH)) {
9213 uint32_t excp = gen_prep_dbgex(ctx);
9214 gen_exception_nip(ctx, excp, ctx->base.pc_next);
9215 }
9216
9217 if (tcg_check_temp_count()) {
9218 qemu_log("Opcode %02x %02x %02x %02x (%08x) leaked "
9219 "temporaries\n", opc1(ctx->opcode), opc2(ctx->opcode),
9220 opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode);
9221 }
9222
9223 ctx->base.is_jmp = ctx->exception == POWERPC_EXCP_NONE ?
9224 DISAS_NEXT : DISAS_NORETURN;
9225 }
9226
9227 static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
9228 {
9229 DisasContext *ctx = container_of(dcbase, DisasContext, base);
9230
9231 if (ctx->exception == POWERPC_EXCP_NONE) {
9232 gen_goto_tb(ctx, 0, ctx->base.pc_next);
9233 } else if (ctx->exception != POWERPC_EXCP_BRANCH) {
9234 if (unlikely(ctx->base.singlestep_enabled)) {
9235 gen_debug_exception(ctx);
9236 }
9237 /* Generate the return instruction */
9238 tcg_gen_exit_tb(NULL, 0);
9239 }
9240 }
9241
9242 static void ppc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs)
9243 {
9244 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
9245 log_target_disas(cs, dcbase->pc_first, dcbase->tb->size);
9246 }
9247
9248 static const TranslatorOps ppc_tr_ops = {
9249 .init_disas_context = ppc_tr_init_disas_context,
9250 .tb_start = ppc_tr_tb_start,
9251 .insn_start = ppc_tr_insn_start,
9252 .breakpoint_check = ppc_tr_breakpoint_check,
9253 .translate_insn = ppc_tr_translate_insn,
9254 .tb_stop = ppc_tr_tb_stop,
9255 .disas_log = ppc_tr_disas_log,
9256 };
9257
9258 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
9259 {
9260 DisasContext ctx;
9261
9262 translator_loop(&ppc_tr_ops, &ctx.base, cs, tb, max_insns);
9263 }
9264
9265 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
9266 target_ulong *data)
9267 {
9268 env->nip = data[0];
9269 }
QEmu