hw/arm/mps2.c

   1 /*
   2  * ARM V2M MPS2 board emulation.
   3  *
   4  * Copyright (c) 2017 Linaro Limited
   5  * Written by Peter Maydell
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License version 2 or
   9  *  (at your option) any later version.
  10  */
  11
  12 /* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger
  13  * FPGA but is otherwise the same as the 2). Since the CPU itself
  14  * and most of the devices are in the FPGA, the details of the board
  15  * as seen by the guest depend significantly on the FPGA image.
  16  * We model the following FPGA images:
  17  *  "mps2-an385" -- Cortex-M3 as documented in ARM Application Note AN385
  18  *  "mps2-an511" -- Cortex-M3 'DesignStart' as documented in AN511
  19  *
  20  * Links to the TRM for the board itself and to the various Application
  21  * Notes which document the FPGA images can be found here:
  22  *   https://developer.arm.com/products/system-design/development-boards/cortex-m-prototyping-system
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qapi/error.h"
  27 #include "qemu/error-report.h"
  28 #include "hw/arm/arm.h"
  29 #include "hw/arm/armv7m.h"
  30 #include "hw/or-irq.h"
  31 #include "hw/boards.h"
  32 #include "exec/address-spaces.h"
  33 #include "sysemu/sysemu.h"
  34 #include "hw/misc/unimp.h"
  35 #include "hw/char/cmsdk-apb-uart.h"
  36 #include "hw/timer/cmsdk-apb-timer.h"
  37
  38 typedef enum MPS2FPGAType {
  39     FPGA_AN385,
  40     FPGA_AN511,
  41 } MPS2FPGAType;
  42
  43 typedef struct {
  44     MachineClass parent;
  45     MPS2FPGAType fpga_type;
  46     const char *cpu_model;
  47 } MPS2MachineClass;
  48
  49 typedef struct {
  50     MachineState parent;
  51
  52     ARMv7MState armv7m;
  53     MemoryRegion psram;
  54     MemoryRegion ssram1;
  55     MemoryRegion ssram1_m;
  56     MemoryRegion ssram23;
  57     MemoryRegion ssram23_m;
  58     MemoryRegion blockram;
  59     MemoryRegion blockram_m1;
  60     MemoryRegion blockram_m2;
  61     MemoryRegion blockram_m3;
  62     MemoryRegion sram;
  63 } MPS2MachineState;
  64
  65 #define TYPE_MPS2_MACHINE "mps2"
  66 #define TYPE_MPS2_AN385_MACHINE MACHINE_TYPE_NAME("mps2-an385")
  67 #define TYPE_MPS2_AN511_MACHINE MACHINE_TYPE_NAME("mps2-an511")
  68
  69 #define MPS2_MACHINE(obj)                                       \
  70     OBJECT_CHECK(MPS2MachineState, obj, TYPE_MPS2_MACHINE)
  71 #define MPS2_MACHINE_GET_CLASS(obj) \
  72     OBJECT_GET_CLASS(MPS2MachineClass, obj, TYPE_MPS2_MACHINE)
  73 #define MPS2_MACHINE_CLASS(klass) \
  74     OBJECT_CLASS_CHECK(MPS2MachineClass, klass, TYPE_MPS2_MACHINE)
  75
  76 /* Main SYSCLK frequency in Hz */
  77 #define SYSCLK_FRQ 25000000
  78
  79 /* Initialize the auxiliary RAM region @mr and map it into
  80  * the memory map at @base.
  81  */
  82 static void make_ram(MemoryRegion *mr, const char *name,
  83                      hwaddr base, hwaddr size)
  84 {
  85     memory_region_init_ram(mr, NULL, name, size, &error_fatal);
  86     memory_region_add_subregion(get_system_memory(), base, mr);
  87 }
  88
  89 /* Create an alias of an entire original MemoryRegion @orig
  90  * located at @base in the memory map.
  91  */
  92 static void make_ram_alias(MemoryRegion *mr, const char *name,
  93                            MemoryRegion *orig, hwaddr base)
  94 {
  95     memory_region_init_alias(mr, NULL, name, orig, 0,
  96                              memory_region_size(orig));
  97     memory_region_add_subregion(get_system_memory(), base, mr);
  98 }
  99
 100 static void mps2_common_init(MachineState *machine)
 101 {
 102     MPS2MachineState *mms = MPS2_MACHINE(machine);
 103     MPS2MachineClass *mmc = MPS2_MACHINE_GET_CLASS(machine);
 104     MemoryRegion *system_memory = get_system_memory();
 105     DeviceState *armv7m;
 106
 107     if (!machine->cpu_model) {
 108         machine->cpu_model = mmc->cpu_model;
 109     }
 110
 111     if (strcmp(machine->cpu_model, mmc->cpu_model) != 0) {
 112         error_report("This board can only be used with CPU %s", mmc->cpu_model);
 113         exit(1);
 114     }
 115
 116     /* The FPGA images have an odd combination of different RAMs,
 117      * because in hardware they are different implementations and
 118      * connected to different buses, giving varying performance/size
 119      * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily
 120      * call the 16MB our "system memory", as it's the largest lump.
 121      *
 122      * Common to both boards:
 123      *  0x21000000..0x21ffffff : PSRAM (16MB)
 124      * AN385 only:
 125      *  0x00000000 .. 0x003fffff : ZBT SSRAM1
 126      *  0x00400000 .. 0x007fffff : mirror of ZBT SSRAM1
 127      *  0x20000000 .. 0x203fffff : ZBT SSRAM 2&3
 128      *  0x20400000 .. 0x207fffff : mirror of ZBT SSRAM 2&3
 129      *  0x01000000 .. 0x01003fff : block RAM (16K)
 130      *  0x01004000 .. 0x01007fff : mirror of above
 131      *  0x01008000 .. 0x0100bfff : mirror of above
 132      *  0x0100c000 .. 0x0100ffff : mirror of above
 133      * AN511 only:
 134      *  0x00000000 .. 0x0003ffff : FPGA block RAM
 135      *  0x00400000 .. 0x007fffff : ZBT SSRAM1
 136      *  0x20000000 .. 0x2001ffff : SRAM
 137      *  0x20400000 .. 0x207fffff : ZBT SSRAM 2&3
 138      *
 139      * The AN385 has a feature where the lowest 16K can be mapped
 140      * either to the bottom of the ZBT SSRAM1 or to the block RAM.
 141      * This is of no use for QEMU so we don't implement it (as if
 142      * zbt_boot_ctrl is always zero).
 143      */
 144     memory_region_allocate_system_memory(&mms->psram,
 145                                          NULL, "mps.ram", 0x1000000);
 146     memory_region_add_subregion(system_memory, 0x21000000, &mms->psram);
 147
 148     switch (mmc->fpga_type) {
 149     case FPGA_AN385:
 150         make_ram(&mms->ssram1, "mps.ssram1", 0x0, 0x400000);
 151         make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", &mms->ssram1, 0x400000);
 152         make_ram(&mms->ssram23, "mps.ssram23", 0x20000000, 0x400000);
 153         make_ram_alias(&mms->ssram23_m, "mps.ssram23_m",
 154                        &mms->ssram23, 0x20400000);
 155         make_ram(&mms->blockram, "mps.blockram", 0x01000000, 0x4000);
 156         make_ram_alias(&mms->blockram_m1, "mps.blockram_m1",
 157                        &mms->blockram, 0x01004000);
 158         make_ram_alias(&mms->blockram_m2, "mps.blockram_m2",
 159                        &mms->blockram, 0x01008000);
 160         make_ram_alias(&mms->blockram_m3, "mps.blockram_m3",
 161                        &mms->blockram, 0x0100c000);
 162         break;
 163     case FPGA_AN511:
 164         make_ram(&mms->blockram, "mps.blockram", 0x0, 0x40000);
 165         make_ram(&mms->ssram1, "mps.ssram1", 0x00400000, 0x00800000);
 166         make_ram(&mms->sram, "mps.sram", 0x20000000, 0x20000);
 167         make_ram(&mms->ssram23, "mps.ssram23", 0x20400000, 0x400000);
 168         break;
 169     default:
 170         g_assert_not_reached();
 171     }
 172
 173     object_initialize(&mms->armv7m, sizeof(mms->armv7m), TYPE_ARMV7M);
 174     armv7m = DEVICE(&mms->armv7m);
 175     qdev_set_parent_bus(armv7m, sysbus_get_default());
 176     switch (mmc->fpga_type) {
 177     case FPGA_AN385:
 178         qdev_prop_set_uint32(armv7m, "num-irq", 32);
 179         break;
 180     case FPGA_AN511:
 181         qdev_prop_set_uint32(armv7m, "num-irq", 64);
 182         break;
 183     default:
 184         g_assert_not_reached();
 185     }
 186     qdev_prop_set_string(armv7m, "cpu-model", machine->cpu_model);
 187     object_property_set_link(OBJECT(&mms->armv7m), OBJECT(system_memory),
 188                              "memory", &error_abort);
 189     object_property_set_bool(OBJECT(&mms->armv7m), true, "realized",
 190                              &error_fatal);
 191
 192     create_unimplemented_device("zbtsmram mirror", 0x00400000, 0x00400000);
 193     create_unimplemented_device("RESERVED 1", 0x00800000, 0x00800000);
 194     create_unimplemented_device("Block RAM", 0x01000000, 0x00010000);
 195     create_unimplemented_device("RESERVED 2", 0x01010000, 0x1EFF0000);
 196     create_unimplemented_device("RESERVED 3", 0x20800000, 0x00800000);
 197     create_unimplemented_device("PSRAM", 0x21000000, 0x01000000);
 198     /* These three ranges all cover multiple devices; we may implement
 199      * some of them below (in which case the real device takes precedence
 200      * over the unimplemented-region mapping).
 201      */
 202     create_unimplemented_device("CMSDK APB peripheral region @0x40000000",
 203                                 0x40000000, 0x00010000);
 204     create_unimplemented_device("CMSDK peripheral region @0x40010000",
 205                                 0x40010000, 0x00010000);
 206     create_unimplemented_device("Extra peripheral region @0x40020000",
 207                                 0x40020000, 0x00010000);
 208     create_unimplemented_device("RESERVED 4", 0x40030000, 0x001D0000);
 209     create_unimplemented_device("Ethernet", 0x40200000, 0x00100000);
 210     create_unimplemented_device("VGA", 0x41000000, 0x0200000);
 211
 212     switch (mmc->fpga_type) {
 213     case FPGA_AN385:
 214     {
 215         /* The overflow IRQs for UARTs 0, 1 and 2 are ORed together.
 216          * Overflow for UARTs 4 and 5 doesn't trigger any interrupt.
 217          */
 218         Object *orgate;
 219         DeviceState *orgate_dev;
 220         int i;
 221
 222         orgate = object_new(TYPE_OR_IRQ);
 223         object_property_set_int(orgate, 6, "num-lines", &error_fatal);
 224         object_property_set_bool(orgate, true, "realized", &error_fatal);
 225         orgate_dev = DEVICE(orgate);
 226         qdev_connect_gpio_out(orgate_dev, 0, qdev_get_gpio_in(armv7m, 12));
 227
 228         for (i = 0; i < 5; i++) {
 229             static const hwaddr uartbase[] = {0x40004000, 0x40005000,
 230                                               0x40006000, 0x40007000,
 231                                               0x40009000};
 232             Chardev *uartchr = i < MAX_SERIAL_PORTS ? serial_hds[i] : NULL;
 233             /* RX irq number; TX irq is always one greater */
 234             static const int uartirq[] = {0, 2, 4, 18, 20};
 235             qemu_irq txovrint = NULL, rxovrint = NULL;
 236
 237             if (i < 3) {
 238                 txovrint = qdev_get_gpio_in(orgate_dev, i * 2);
 239                 rxovrint = qdev_get_gpio_in(orgate_dev, i * 2 + 1);
 240             }
 241
 242             cmsdk_apb_uart_create(uartbase[i],
 243                                   qdev_get_gpio_in(armv7m, uartirq[i] + 1),
 244                                   qdev_get_gpio_in(armv7m, uartirq[i]),
 245                                   txovrint, rxovrint,
 246                                   NULL,
 247                                   uartchr, SYSCLK_FRQ);
 248         }
 249         break;
 250     }
 251     case FPGA_AN511:
 252     {
 253         /* The overflow IRQs for all UARTs are ORed together.
 254          * Tx and Rx IRQs for each UART are ORed together.
 255          */
 256         Object *orgate;
 257         DeviceState *orgate_dev;
 258         int i;
 259
 260         orgate = object_new(TYPE_OR_IRQ);
 261         object_property_set_int(orgate, 10, "num-lines", &error_fatal);
 262         object_property_set_bool(orgate, true, "realized", &error_fatal);
 263         orgate_dev = DEVICE(orgate);
 264         qdev_connect_gpio_out(orgate_dev, 0, qdev_get_gpio_in(armv7m, 12));
 265
 266         for (i = 0; i < 5; i++) {
 267             /* system irq numbers for the combined tx/rx for each UART */
 268             static const int uart_txrx_irqno[] = {0, 2, 45, 46, 56};
 269             static const hwaddr uartbase[] = {0x40004000, 0x40005000,
 270                                               0x4002c000, 0x4002d000,
 271                                               0x4002e000};
 272             Chardev *uartchr = i < MAX_SERIAL_PORTS ? serial_hds[i] : NULL;
 273             Object *txrx_orgate;
 274             DeviceState *txrx_orgate_dev;
 275
 276             txrx_orgate = object_new(TYPE_OR_IRQ);
 277             object_property_set_int(txrx_orgate, 2, "num-lines", &error_fatal);
 278             object_property_set_bool(txrx_orgate, true, "realized",
 279                                      &error_fatal);
 280             txrx_orgate_dev = DEVICE(txrx_orgate);
 281             qdev_connect_gpio_out(txrx_orgate_dev, 0,
 282                                   qdev_get_gpio_in(armv7m, uart_txrx_irqno[i]));
 283             cmsdk_apb_uart_create(uartbase[i],
 284                                   qdev_get_gpio_in(txrx_orgate_dev, 0),
 285                                   qdev_get_gpio_in(txrx_orgate_dev, 1),
 286                                   qdev_get_gpio_in(orgate_dev, 0),
 287                                   qdev_get_gpio_in(orgate_dev, 1),
 288                                   NULL,
 289                                   uartchr, SYSCLK_FRQ);
 290         }
 291         break;
 292     }
 293     default:
 294         g_assert_not_reached();
 295     }
 296
 297     cmsdk_apb_timer_create(0x40000000, qdev_get_gpio_in(armv7m, 8), SYSCLK_FRQ);
 298     cmsdk_apb_timer_create(0x40001000, qdev_get_gpio_in(armv7m, 9), SYSCLK_FRQ);
 299
 300     system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ;
 301
 302     armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
 303                        0x400000);
 304 }
 305
 306 static void mps2_class_init(ObjectClass *oc, void *data)
 307 {
 308     MachineClass *mc = MACHINE_CLASS(oc);
 309
 310     mc->init = mps2_common_init;
 311     mc->max_cpus = 1;
 312 }
 313
 314 static void mps2_an385_class_init(ObjectClass *oc, void *data)
 315 {
 316     MachineClass *mc = MACHINE_CLASS(oc);
 317     MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc);
 318
 319     mc->desc = "ARM MPS2 with AN385 FPGA image for Cortex-M3";
 320     mmc->fpga_type = FPGA_AN385;
 321     mmc->cpu_model = "cortex-m3";
 322 }
 323
 324 static void mps2_an511_class_init(ObjectClass *oc, void *data)
 325 {
 326     MachineClass *mc = MACHINE_CLASS(oc);
 327     MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc);
 328
 329     mc->desc = "ARM MPS2 with AN511 DesignStart FPGA image for Cortex-M3";
 330     mmc->fpga_type = FPGA_AN511;
 331     mmc->cpu_model = "cortex-m3";
 332 }
 333
 334 static const TypeInfo mps2_info = {
 335     .name = TYPE_MPS2_MACHINE,
 336     .parent = TYPE_MACHINE,
 337     .abstract = true,
 338     .instance_size = sizeof(MPS2MachineState),
 339     .class_size = sizeof(MPS2MachineClass),
 340     .class_init = mps2_class_init,
 341 };
 342
 343 static const TypeInfo mps2_an385_info = {
 344     .name = TYPE_MPS2_AN385_MACHINE,
 345     .parent = TYPE_MPS2_MACHINE,
 346     .class_init = mps2_an385_class_init,
 347 };
 348
 349 static const TypeInfo mps2_an511_info = {
 350     .name = TYPE_MPS2_AN511_MACHINE,
 351     .parent = TYPE_MPS2_MACHINE,
 352     .class_init = mps2_an511_class_init,
 353 };
 354
 355 static void mps2_machine_init(void)
 356 {
 357     type_register_static(&mps2_info);
 358     type_register_static(&mps2_an385_info);
 359     type_register_static(&mps2_an511_info);
 360 }
 361
 362 type_init(mps2_machine_init);