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x86: pci: acpi: reorder Device's _ADR and _SUN fields
[qemu.git] / hw / i386 / acpi-build.c
blob6342467af41a790c97896af940e783d62cc82558
1 /* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include "qemu/osdep.h"
24 #include "qapi/error.h"
25 #include "qapi/qmp/qnum.h"
26 #include "acpi-build.h"
27 #include "acpi-common.h"
28 #include "qemu/bitmap.h"
29 #include "qemu/error-report.h"
30 #include "hw/pci/pci.h"
31 #include "hw/cxl/cxl.h"
32 #include "hw/core/cpu.h"
33 #include "target/i386/cpu.h"
34 #include "hw/timer/hpet.h"
35 #include "hw/acpi/acpi-defs.h"
36 #include "hw/acpi/acpi.h"
37 #include "hw/acpi/cpu.h"
38 #include "hw/nvram/fw_cfg.h"
39 #include "hw/acpi/bios-linker-loader.h"
40 #include "hw/acpi/acpi_aml_interface.h"
41 #include "hw/input/i8042.h"
42 #include "hw/acpi/memory_hotplug.h"
43 #include "sysemu/tpm.h"
44 #include "hw/acpi/tpm.h"
45 #include "hw/acpi/vmgenid.h"
46 #include "hw/acpi/erst.h"
47 #include "hw/acpi/piix4.h"
48 #include "sysemu/tpm_backend.h"
49 #include "hw/rtc/mc146818rtc_regs.h"
50 #include "migration/vmstate.h"
51 #include "hw/mem/memory-device.h"
52 #include "hw/mem/nvdimm.h"
53 #include "sysemu/numa.h"
54 #include "sysemu/reset.h"
55 #include "hw/hyperv/vmbus-bridge.h"
56
57 /* Supported chipsets: */
58 #include "hw/southbridge/piix.h"
59 #include "hw/acpi/pcihp.h"
60 #include "hw/i386/fw_cfg.h"
61 #include "hw/i386/ich9.h"
62 #include "hw/pci/pci_bus.h"
63 #include "hw/pci-host/q35.h"
64 #include "hw/i386/x86-iommu.h"
65
66 #include "hw/acpi/aml-build.h"
67 #include "hw/acpi/utils.h"
68 #include "hw/acpi/pci.h"
69 #include "hw/acpi/cxl.h"
70
71 #include "qom/qom-qobject.h"
72 #include "hw/i386/amd_iommu.h"
73 #include "hw/i386/intel_iommu.h"
74 #include "hw/virtio/virtio-iommu.h"
75
76 #include "hw/acpi/hmat.h"
77 #include "hw/acpi/viot.h"
78 #include "hw/acpi/cxl.h"
79
80 #include CONFIG_DEVICES
81
82 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
83 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
84 * a little bit, there should be plenty of free space since the DSDT
85 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
86 */
87 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
88 #define ACPI_BUILD_ALIGN_SIZE 0x1000
89
90 #define ACPI_BUILD_TABLE_SIZE 0x20000
91
92 /* #define DEBUG_ACPI_BUILD */
93 #ifdef DEBUG_ACPI_BUILD
94 #define ACPI_BUILD_DPRINTF(fmt, ...) \
95 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
96 #else
97 #define ACPI_BUILD_DPRINTF(fmt, ...)
98 #endif
99
100 typedef struct AcpiPmInfo {
101 bool s3_disabled;
102 bool s4_disabled;
103 bool pcihp_bridge_en;
104 bool smi_on_cpuhp;
105 bool smi_on_cpu_unplug;
106 bool pcihp_root_en;
107 uint8_t s4_val;
108 AcpiFadtData fadt;
109 uint16_t cpu_hp_io_base;
110 uint16_t pcihp_io_base;
111 uint16_t pcihp_io_len;
112 } AcpiPmInfo;
113
114 typedef struct AcpiMiscInfo {
115 bool is_piix4;
116 bool has_hpet;
117 #ifdef CONFIG_TPM
118 TPMVersion tpm_version;
119 #endif
120 const unsigned char *dsdt_code;
121 unsigned dsdt_size;
122 } AcpiMiscInfo;
123
124 typedef struct AcpiBuildPciBusHotplugState {
125 GArray *device_table;
126 GArray *notify_table;
127 struct AcpiBuildPciBusHotplugState *parent;
128 bool pcihp_bridge_en;
129 } AcpiBuildPciBusHotplugState;
130
131 typedef struct FwCfgTPMConfig {
132 uint32_t tpmppi_address;
133 uint8_t tpm_version;
134 uint8_t tpmppi_version;
135 } QEMU_PACKED FwCfgTPMConfig;
136
137 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg);
138
139 const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio = {
140 .space_id = AML_AS_SYSTEM_IO,
141 .address = NVDIMM_ACPI_IO_BASE,
142 .bit_width = NVDIMM_ACPI_IO_LEN << 3
143 };
144
145 static void init_common_fadt_data(MachineState *ms, Object *o,
146 AcpiFadtData *data)
147 {
148 X86MachineState *x86ms = X86_MACHINE(ms);
149 /*
150 * "ICH9-LPC" or "PIIX4_PM" has "smm-compat" property to keep the old
151 * behavior for compatibility irrelevant to smm_enabled, which doesn't
152 * comforms to ACPI spec.
153 */
154 bool smm_enabled = object_property_get_bool(o, "smm-compat", NULL) ?
155 true : x86_machine_is_smm_enabled(x86ms);
156 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL);
157 AmlAddressSpace as = AML_AS_SYSTEM_IO;
158 AcpiFadtData fadt = {
159 .rev = 3,
160 .flags =
161 (1 << ACPI_FADT_F_WBINVD) |
162 (1 << ACPI_FADT_F_PROC_C1) |
163 (1 << ACPI_FADT_F_SLP_BUTTON) |
164 (1 << ACPI_FADT_F_RTC_S4) |
165 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) |
166 /* APIC destination mode ("Flat Logical") has an upper limit of 8
167 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be
168 * used
169 */
170 ((ms->smp.max_cpus > 8) ?
171 (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0),
172 .int_model = 1 /* Multiple APIC */,
173 .rtc_century = RTC_CENTURY,
174 .plvl2_lat = 0xfff /* C2 state not supported */,
175 .plvl3_lat = 0xfff /* C3 state not supported */,
176 .smi_cmd = smm_enabled ? ACPI_PORT_SMI_CMD : 0,
177 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL),
178 .acpi_enable_cmd =
179 smm_enabled ?
180 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL) :
181 0,
182 .acpi_disable_cmd =
183 smm_enabled ?
184 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL) :
185 0,
186 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io },
187 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8,
188 .address = io + 0x04 },
189 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 },
190 .gpe0_blk = { .space_id = as, .bit_width =
191 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8,
192 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL)
193 },
194 };
195
196 /*
197 * ACPI v2, Table 5-10 - Fixed ACPI Description Table Boot Architecture
198 * Flags, bit offset 1 - 8042.
199 */
200 fadt.iapc_boot_arch = iapc_boot_arch_8042();
201
202 *data = fadt;
203 }
204
205 static Object *object_resolve_type_unambiguous(const char *typename)
206 {
207 bool ambig;
208 Object *o = object_resolve_path_type("", typename, &ambig);
209
210 if (ambig || !o) {
211 return NULL;
212 }
213 return o;
214 }
215
216 static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm)
217 {
218 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM);
219 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE);
220 Object *obj = piix ? piix : lpc;
221 QObject *o;
222 pm->cpu_hp_io_base = 0;
223 pm->pcihp_io_base = 0;
224 pm->pcihp_io_len = 0;
225 pm->smi_on_cpuhp = false;
226 pm->smi_on_cpu_unplug = false;
227
228 assert(obj);
229 init_common_fadt_data(machine, obj, &pm->fadt);
230 if (piix) {
231 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */
232 pm->fadt.rev = 1;
233 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
234 }
235 if (lpc) {
236 uint64_t smi_features = object_property_get_uint(lpc,
237 ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, NULL);
238 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO,
239 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT };
240 pm->fadt.reset_reg = r;
241 pm->fadt.reset_val = 0xf;
242 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP;
243 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
244 pm->smi_on_cpuhp =
245 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT));
246 pm->smi_on_cpu_unplug =
247 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT));
248 }
249 pm->pcihp_io_base =
250 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
251 pm->pcihp_io_len =
252 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
253
254 /* The above need not be conditional on machine type because the reset port
255 * happens to be the same on PIIX (pc) and ICH9 (q35). */
256 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != PIIX_RCR_IOPORT);
257
258 /* Fill in optional s3/s4 related properties */
259 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
260 if (o) {
261 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o));
262 } else {
263 pm->s3_disabled = false;
264 }
265 qobject_unref(o);
266 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
267 if (o) {
268 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o));
269 } else {
270 pm->s4_disabled = false;
271 }
272 qobject_unref(o);
273 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
274 if (o) {
275 pm->s4_val = qnum_get_uint(qobject_to(QNum, o));
276 } else {
277 pm->s4_val = false;
278 }
279 qobject_unref(o);
280
281 pm->pcihp_bridge_en =
282 object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCIHP_BRIDGE,
283 NULL);
284 pm->pcihp_root_en =
285 object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCI_ROOTHP,
286 NULL);
287 }
288
289 static void acpi_get_misc_info(AcpiMiscInfo *info)
290 {
291 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM);
292 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE);
293 assert(!!piix != !!lpc);
294
295 if (piix) {
296 info->is_piix4 = true;
297 }
298 if (lpc) {
299 info->is_piix4 = false;
300 }
301
302 info->has_hpet = hpet_find();
303 #ifdef CONFIG_TPM
304 info->tpm_version = tpm_get_version(tpm_find());
305 #endif
306 }
307
308 /*
309 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
310 * On i386 arch we only have two pci hosts, so we can look only for them.
311 */
312 Object *acpi_get_i386_pci_host(void)
313 {
314 PCIHostState *host;
315
316 host = PCI_HOST_BRIDGE(object_resolve_path("/machine/i440fx", NULL));
317 if (!host) {
318 host = PCI_HOST_BRIDGE(object_resolve_path("/machine/q35", NULL));
319 }
320
321 return OBJECT(host);
322 }
323
324 static void acpi_get_pci_holes(Range *hole, Range *hole64)
325 {
326 Object *pci_host;
327
328 pci_host = acpi_get_i386_pci_host();
329
330 if (!pci_host) {
331 return;
332 }
333
334 range_set_bounds1(hole,
335 object_property_get_uint(pci_host,
336 PCI_HOST_PROP_PCI_HOLE_START,
337 NULL),
338 object_property_get_uint(pci_host,
339 PCI_HOST_PROP_PCI_HOLE_END,
340 NULL));
341 range_set_bounds1(hole64,
342 object_property_get_uint(pci_host,
343 PCI_HOST_PROP_PCI_HOLE64_START,
344 NULL),
345 object_property_get_uint(pci_host,
346 PCI_HOST_PROP_PCI_HOLE64_END,
347 NULL));
348 }
349
350 static void acpi_align_size(GArray *blob, unsigned align)
351 {
352 /* Align size to multiple of given size. This reduces the chance
353 * we need to change size in the future (breaking cross version migration).
354 */
355 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
356 }
357
358 /*
359 * ACPI spec 1.0b,
360 * 5.2.6 Firmware ACPI Control Structure
361 */
362 static void
363 build_facs(GArray *table_data)
364 {
365 const char *sig = "FACS";
366 const uint8_t reserved[40] = {};
367
368 g_array_append_vals(table_data, sig, 4); /* Signature */
369 build_append_int_noprefix(table_data, 64, 4); /* Length */
370 build_append_int_noprefix(table_data, 0, 4); /* Hardware Signature */
371 build_append_int_noprefix(table_data, 0, 4); /* Firmware Waking Vector */
372 build_append_int_noprefix(table_data, 0, 4); /* Global Lock */
373 build_append_int_noprefix(table_data, 0, 4); /* Flags */
374 g_array_append_vals(table_data, reserved, 40); /* Reserved */
375 }
376
377 Aml *aml_pci_device_dsm(void)
378 {
379 Aml *method;
380
381 method = aml_method("_DSM", 4, AML_SERIALIZED);
382 {
383 Aml *params = aml_local(0);
384 Aml *pkg = aml_package(2);
385 aml_append(pkg, aml_name("BSEL"));
386 aml_append(pkg, aml_name("ASUN"));
387 aml_append(method, aml_store(pkg, params));
388 aml_append(method,
389 aml_return(aml_call5("PDSM", aml_arg(0), aml_arg(1),
390 aml_arg(2), aml_arg(3), params))
391 );
392 }
393 return method;
394 }
395
396 static void build_append_pcihp_notify_entry(Aml *method, int slot)
397 {
398 Aml *if_ctx;
399 int32_t devfn = PCI_DEVFN(slot, 0);
400
401 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
402 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
403 aml_append(method, if_ctx);
404 }
405
406 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
407 bool pcihp_bridge_en)
408 {
409 Aml *dev, *notify_method = NULL, *method;
410 QObject *bsel;
411 PCIBus *sec;
412 int devfn;
413
414 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
415 if (bsel) {
416 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
417
418 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
419 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
420 }
421
422 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
423 DeviceClass *dc;
424 PCIDeviceClass *pc;
425 PCIDevice *pdev = bus->devices[devfn];
426 int slot = PCI_SLOT(devfn);
427 int func = PCI_FUNC(devfn);
428 /* ACPI spec: 1.0b: Table 6-2 _ADR Object Bus Types, PCI type */
429 int adr = slot << 16 | func;
430 bool hotplug_enabled_dev;
431 bool bridge_in_acpi;
432 bool cold_plugged_bridge;
433
434 if (!pdev) {
435 /*
436 * add hotplug slots for non present devices.
437 * hotplug is supported only for non-multifunction device
438 * so generate device description only for function 0
439 */
440 if (bsel && !func) {
441 if (pci_bus_is_express(bus) && slot > 0) {
442 break;
443 }
444 dev = aml_device("S%.02X", devfn);
445 aml_append(dev, aml_name_decl("_ADR", aml_int(adr)));
446 aml_append(dev, aml_name_decl("ASUN", aml_int(slot)));
447 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
448 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
449 aml_append(method,
450 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
451 );
452 aml_append(dev, method);
453
454 aml_append(dev, aml_pci_device_dsm());
455
456 aml_append(parent_scope, dev);
457
458 build_append_pcihp_notify_entry(notify_method, slot);
459 }
460 continue;
461 }
462
463 pc = PCI_DEVICE_GET_CLASS(pdev);
464 dc = DEVICE_GET_CLASS(pdev);
465
466 /*
467 * Cold plugged bridges aren't themselves hot-pluggable.
468 * Hotplugged bridges *are* hot-pluggable.
469 */
470 cold_plugged_bridge = pc->is_bridge && !DEVICE(pdev)->hotplugged;
471 bridge_in_acpi = cold_plugged_bridge && pcihp_bridge_en;
472
473 hotplug_enabled_dev = bsel && dc->hotpluggable && !cold_plugged_bridge;
474
475 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) {
476 continue;
477 }
478
479 /*
480 * allow describing coldplugged bridges in ACPI even if they are not
481 * on function 0, as they are not unpluggable, for all other devices
482 * generate description only for function 0 per slot
483 */
484 if (func && !bridge_in_acpi) {
485 continue;
486 }
487
488 /* start to compose PCI device descriptor */
489 dev = aml_device("S%.02X", devfn);
490 aml_append(dev, aml_name_decl("_ADR", aml_int(adr)));
491
492 if (bsel) {
493 /*
494 * Can't declare _SUN here for every device as it changes 'slot'
495 * enumeration order in linux kernel, so use another variable for it
496 */
497 aml_append(dev, aml_name_decl("ASUN", aml_int(slot)));
498 aml_append(dev, aml_pci_device_dsm());
499 }
500
501 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) {
502 /* add VGA specific AML methods */
503 int s3d;
504
505 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) {
506 s3d = 3;
507 } else {
508 s3d = 0;
509 }
510
511 method = aml_method("_S1D", 0, AML_NOTSERIALIZED);
512 aml_append(method, aml_return(aml_int(0)));
513 aml_append(dev, method);
514
515 method = aml_method("_S2D", 0, AML_NOTSERIALIZED);
516 aml_append(method, aml_return(aml_int(0)));
517 aml_append(dev, method);
518
519 method = aml_method("_S3D", 0, AML_NOTSERIALIZED);
520 aml_append(method, aml_return(aml_int(s3d)));
521 aml_append(dev, method);
522 } else if (hotplug_enabled_dev) {
523 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
524 /* add _EJ0 to make slot hotpluggable */
525 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
526 aml_append(method,
527 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
528 );
529 aml_append(dev, method);
530
531 if (bsel) {
532 build_append_pcihp_notify_entry(notify_method, slot);
533 }
534 } else if (bridge_in_acpi) {
535 /*
536 * device is coldplugged bridge,
537 * add child device descriptions into its scope
538 */
539 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
540
541 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en);
542 }
543 /* device descriptor has been composed, add it into parent context */
544 aml_append(parent_scope, dev);
545 }
546
547 if (bsel) {
548 aml_append(parent_scope, notify_method);
549 }
550
551 /* Append PCNT method to notify about events on local and child buses.
552 * Add this method for root bus only when hotplug is enabled since DSDT
553 * expects it.
554 */
555 if (bsel || pcihp_bridge_en) {
556 method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
557
558 /* If bus supports hotplug select it and notify about local events */
559 if (bsel) {
560 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
561
562 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
563 aml_append(method, aml_call2("DVNT", aml_name("PCIU"),
564 aml_int(1))); /* Device Check */
565 aml_append(method, aml_call2("DVNT", aml_name("PCID"),
566 aml_int(3))); /* Eject Request */
567 }
568
569 /* Notify about child bus events in any case */
570 if (pcihp_bridge_en) {
571 QLIST_FOREACH(sec, &bus->child, sibling) {
572 if (pci_bus_is_root(sec)) {
573 continue;
574 }
575
576 aml_append(method, aml_name("^S%.02X.PCNT",
577 sec->parent_dev->devfn));
578 }
579 }
580
581 aml_append(parent_scope, method);
582 }
583 qobject_unref(bsel);
584 }
585
586 static Aml *aml_pci_pdsm(void)
587 {
588 Aml *method, *UUID, *ifctx, *ifctx1;
589 Aml *ret = aml_local(0);
590 Aml *caps = aml_local(1);
591 Aml *acpi_index = aml_local(2);
592 Aml *zero = aml_int(0);
593 Aml *one = aml_int(1);
594 Aml *func = aml_arg(2);
595 Aml *rev = aml_arg(1);
596 Aml *params = aml_arg(4);
597 Aml *bnum = aml_derefof(aml_index(params, aml_int(0)));
598 Aml *sunum = aml_derefof(aml_index(params, aml_int(1)));
599
600 method = aml_method("PDSM", 5, AML_SERIALIZED);
601
602 /* get supported functions */
603 ifctx = aml_if(aml_equal(func, zero));
604 {
605 uint8_t byte_list[1] = { 0 }; /* nothing supported yet */
606 aml_append(ifctx, aml_store(aml_buffer(1, byte_list), ret));
607 aml_append(ifctx, aml_store(zero, caps));
608
609 /*
610 * PCI Firmware Specification 3.1
611 * 4.6. _DSM Definitions for PCI
612 */
613 UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D");
614 ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(0), UUID)));
615 {
616 /* call is for unsupported UUID, bail out */
617 aml_append(ifctx1, aml_return(ret));
618 }
619 aml_append(ifctx, ifctx1);
620
621 ifctx1 = aml_if(aml_lless(rev, aml_int(2)));
622 {
623 /* call is for unsupported REV, bail out */
624 aml_append(ifctx1, aml_return(ret));
625 }
626 aml_append(ifctx, ifctx1);
627
628 aml_append(ifctx,
629 aml_store(aml_call2("AIDX", bnum, sunum), acpi_index));
630 /*
631 * advertise function 7 if device has acpi-index
632 * acpi_index values:
633 * 0: not present (default value)
634 * FFFFFFFF: not supported (old QEMU without PIDX reg)
635 * other: device's acpi-index
636 */
637 ifctx1 = aml_if(aml_lnot(
638 aml_or(aml_equal(acpi_index, zero),
639 aml_equal(acpi_index, aml_int(0xFFFFFFFF)), NULL)
640 ));
641 {
642 /* have supported functions */
643 aml_append(ifctx1, aml_or(caps, one, caps));
644 /* support for function 7 */
645 aml_append(ifctx1,
646 aml_or(caps, aml_shiftleft(one, aml_int(7)), caps));
647 }
648 aml_append(ifctx, ifctx1);
649
650 aml_append(ifctx, aml_store(caps, aml_index(ret, zero)));
651 aml_append(ifctx, aml_return(ret));
652 }
653 aml_append(method, ifctx);
654
655 /* handle specific functions requests */
656 /*
657 * PCI Firmware Specification 3.1
658 * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under
659 * Operating Systems
660 */
661 ifctx = aml_if(aml_equal(func, aml_int(7)));
662 {
663 Aml *pkg = aml_package(2);
664
665 aml_append(pkg, zero);
666 /*
667 * optional, if not impl. should return null string
668 */
669 aml_append(pkg, aml_string("%s", ""));
670 aml_append(ifctx, aml_store(pkg, ret));
671
672 aml_append(ifctx, aml_store(aml_call2("AIDX", bnum, sunum), acpi_index));
673 /*
674 * update acpi-index to actual value
675 */
676 aml_append(ifctx, aml_store(acpi_index, aml_index(ret, zero)));
677 aml_append(ifctx, aml_return(ret));
678 }
679
680 aml_append(method, ifctx);
681 return method;
682 }
683
684 /**
685 * build_prt_entry:
686 * @link_name: link name for PCI route entry
687 *
688 * build AML package containing a PCI route entry for @link_name
689 */
690 static Aml *build_prt_entry(const char *link_name)
691 {
692 Aml *a_zero = aml_int(0);
693 Aml *pkg = aml_package(4);
694 aml_append(pkg, a_zero);
695 aml_append(pkg, a_zero);
696 aml_append(pkg, aml_name("%s", link_name));
697 aml_append(pkg, a_zero);
698 return pkg;
699 }
700
701 /*
702 * initialize_route - Initialize the interrupt routing rule
703 * through a specific LINK:
704 * if (lnk_idx == idx)
705 * route using link 'link_name'
706 */
707 static Aml *initialize_route(Aml *route, const char *link_name,
708 Aml *lnk_idx, int idx)
709 {
710 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx)));
711 Aml *pkg = build_prt_entry(link_name);
712
713 aml_append(if_ctx, aml_store(pkg, route));
714
715 return if_ctx;
716 }
717
718 /*
719 * build_prt - Define interrupt rounting rules
720 *
721 * Returns an array of 128 routes, one for each device,
722 * based on device location.
723 * The main goal is to equaly distribute the interrupts
724 * over the 4 existing ACPI links (works only for i440fx).
725 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
726 *
727 */
728 static Aml *build_prt(bool is_pci0_prt)
729 {
730 Aml *method, *while_ctx, *pin, *res;
731
732 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
733 res = aml_local(0);
734 pin = aml_local(1);
735 aml_append(method, aml_store(aml_package(128), res));
736 aml_append(method, aml_store(aml_int(0), pin));
737
738 /* while (pin < 128) */
739 while_ctx = aml_while(aml_lless(pin, aml_int(128)));
740 {
741 Aml *slot = aml_local(2);
742 Aml *lnk_idx = aml_local(3);
743 Aml *route = aml_local(4);
744
745 /* slot = pin >> 2 */
746 aml_append(while_ctx,
747 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot));
748 /* lnk_idx = (slot + pin) & 3 */
749 aml_append(while_ctx,
750 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL),
751 lnk_idx));
752
753 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
754 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0));
755 if (is_pci0_prt) {
756 Aml *if_device_1, *if_pin_4, *else_pin_4;
757
758 /* device 1 is the power-management device, needs SCI */
759 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1)));
760 {
761 if_pin_4 = aml_if(aml_equal(pin, aml_int(4)));
762 {
763 aml_append(if_pin_4,
764 aml_store(build_prt_entry("LNKS"), route));
765 }
766 aml_append(if_device_1, if_pin_4);
767 else_pin_4 = aml_else();
768 {
769 aml_append(else_pin_4,
770 aml_store(build_prt_entry("LNKA"), route));
771 }
772 aml_append(if_device_1, else_pin_4);
773 }
774 aml_append(while_ctx, if_device_1);
775 } else {
776 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1));
777 }
778 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2));
779 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3));
780
781 /* route[0] = 0x[slot]FFFF */
782 aml_append(while_ctx,
783 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF),
784 NULL),
785 aml_index(route, aml_int(0))));
786 /* route[1] = pin & 3 */
787 aml_append(while_ctx,
788 aml_store(aml_and(pin, aml_int(3), NULL),
789 aml_index(route, aml_int(1))));
790 /* res[pin] = route */
791 aml_append(while_ctx, aml_store(route, aml_index(res, pin)));
792 /* pin++ */
793 aml_append(while_ctx, aml_increment(pin));
794 }
795 aml_append(method, while_ctx);
796 /* return res*/
797 aml_append(method, aml_return(res));
798
799 return method;
800 }
801
802 static void build_hpet_aml(Aml *table)
803 {
804 Aml *crs;
805 Aml *field;
806 Aml *method;
807 Aml *if_ctx;
808 Aml *scope = aml_scope("_SB");
809 Aml *dev = aml_device("HPET");
810 Aml *zero = aml_int(0);
811 Aml *id = aml_local(0);
812 Aml *period = aml_local(1);
813
814 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103")));
815 aml_append(dev, aml_name_decl("_UID", zero));
816
817 aml_append(dev,
818 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE),
819 HPET_LEN));
820 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE);
821 aml_append(field, aml_named_field("VEND", 32));
822 aml_append(field, aml_named_field("PRD", 32));
823 aml_append(dev, field);
824
825 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
826 aml_append(method, aml_store(aml_name("VEND"), id));
827 aml_append(method, aml_store(aml_name("PRD"), period));
828 aml_append(method, aml_shiftright(id, aml_int(16), id));
829 if_ctx = aml_if(aml_lor(aml_equal(id, zero),
830 aml_equal(id, aml_int(0xffff))));
831 {
832 aml_append(if_ctx, aml_return(zero));
833 }
834 aml_append(method, if_ctx);
835
836 if_ctx = aml_if(aml_lor(aml_equal(period, zero),
837 aml_lgreater(period, aml_int(100000000))));
838 {
839 aml_append(if_ctx, aml_return(zero));
840 }
841 aml_append(method, if_ctx);
842
843 aml_append(method, aml_return(aml_int(0x0F)));
844 aml_append(dev, method);
845
846 crs = aml_resource_template();
847 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY));
848 aml_append(dev, aml_name_decl("_CRS", crs));
849
850 aml_append(scope, dev);
851 aml_append(table, scope);
852 }
853
854 static Aml *build_vmbus_device_aml(VMBusBridge *vmbus_bridge)
855 {
856 Aml *dev;
857 Aml *method;
858 Aml *crs;
859
860 dev = aml_device("VMBS");
861 aml_append(dev, aml_name_decl("STA", aml_int(0xF)));
862 aml_append(dev, aml_name_decl("_HID", aml_string("VMBus")));
863 aml_append(dev, aml_name_decl("_UID", aml_int(0x0)));
864 aml_append(dev, aml_name_decl("_DDN", aml_string("VMBUS")));
865
866 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
867 aml_append(method, aml_store(aml_and(aml_name("STA"), aml_int(0xD), NULL),
868 aml_name("STA")));
869 aml_append(dev, method);
870
871 method = aml_method("_PS0", 0, AML_NOTSERIALIZED);
872 aml_append(method, aml_store(aml_or(aml_name("STA"), aml_int(0xF), NULL),
873 aml_name("STA")));
874 aml_append(dev, method);
875
876 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
877 aml_append(method, aml_return(aml_name("STA")));
878 aml_append(dev, method);
879
880 aml_append(dev, aml_name_decl("_PS3", aml_int(0x0)));
881
882 crs = aml_resource_template();
883 aml_append(crs, aml_irq_no_flags(vmbus_bridge->irq));
884 aml_append(dev, aml_name_decl("_CRS", crs));
885
886 return dev;
887 }
888
889 static void build_dbg_aml(Aml *table)
890 {
891 Aml *field;
892 Aml *method;
893 Aml *while_ctx;
894 Aml *scope = aml_scope("\\");
895 Aml *buf = aml_local(0);
896 Aml *len = aml_local(1);
897 Aml *idx = aml_local(2);
898
899 aml_append(scope,
900 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01));
901 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
902 aml_append(field, aml_named_field("DBGB", 8));
903 aml_append(scope, field);
904
905 method = aml_method("DBUG", 1, AML_NOTSERIALIZED);
906
907 aml_append(method, aml_to_hexstring(aml_arg(0), buf));
908 aml_append(method, aml_to_buffer(buf, buf));
909 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len));
910 aml_append(method, aml_store(aml_int(0), idx));
911
912 while_ctx = aml_while(aml_lless(idx, len));
913 aml_append(while_ctx,
914 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB")));
915 aml_append(while_ctx, aml_increment(idx));
916 aml_append(method, while_ctx);
917
918 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB")));
919 aml_append(scope, method);
920
921 aml_append(table, scope);
922 }
923
924 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
925 {
926 Aml *dev;
927 Aml *crs;
928 Aml *method;
929 uint32_t irqs[] = {5, 10, 11};
930
931 dev = aml_device("%s", name);
932 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
933 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
934
935 crs = aml_resource_template();
936 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
937 AML_SHARED, irqs, ARRAY_SIZE(irqs)));
938 aml_append(dev, aml_name_decl("_PRS", crs));
939
940 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
941 aml_append(method, aml_return(aml_call1("IQST", reg)));
942 aml_append(dev, method);
943
944 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
945 aml_append(method, aml_or(reg, aml_int(0x80), reg));
946 aml_append(dev, method);
947
948 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
949 aml_append(method, aml_return(aml_call1("IQCR", reg)));
950 aml_append(dev, method);
951
952 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
953 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
954 aml_append(method, aml_store(aml_name("PRRI"), reg));
955 aml_append(dev, method);
956
957 return dev;
958 }
959
960 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
961 {
962 Aml *dev;
963 Aml *crs;
964 Aml *method;
965 uint32_t irqs;
966
967 dev = aml_device("%s", name);
968 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
969 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
970
971 crs = aml_resource_template();
972 irqs = gsi;
973 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
974 AML_SHARED, &irqs, 1));
975 aml_append(dev, aml_name_decl("_PRS", crs));
976
977 aml_append(dev, aml_name_decl("_CRS", crs));
978
979 /*
980 * _DIS can be no-op because the interrupt cannot be disabled.
981 */
982 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
983 aml_append(dev, method);
984
985 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
986 aml_append(dev, method);
987
988 return dev;
989 }
990
991 /* _CRS method - get current settings */
992 static Aml *build_iqcr_method(bool is_piix4)
993 {
994 Aml *if_ctx;
995 uint32_t irqs;
996 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED);
997 Aml *crs = aml_resource_template();
998
999 irqs = 0;
1000 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1001 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
1002 aml_append(method, aml_name_decl("PRR0", crs));
1003
1004 aml_append(method,
1005 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
1006
1007 if (is_piix4) {
1008 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
1009 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI")));
1010 aml_append(method, if_ctx);
1011 } else {
1012 aml_append(method,
1013 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL),
1014 aml_name("PRRI")));
1015 }
1016
1017 aml_append(method, aml_return(aml_name("PRR0")));
1018 return method;
1019 }
1020
1021 /* _STA method - get status */
1022 static Aml *build_irq_status_method(void)
1023 {
1024 Aml *if_ctx;
1025 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED);
1026
1027 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL));
1028 aml_append(if_ctx, aml_return(aml_int(0x09)));
1029 aml_append(method, if_ctx);
1030 aml_append(method, aml_return(aml_int(0x0B)));
1031 return method;
1032 }
1033
1034 static void build_piix4_pci0_int(Aml *table)
1035 {
1036 Aml *dev;
1037 Aml *crs;
1038 Aml *field;
1039 Aml *method;
1040 uint32_t irqs;
1041 Aml *sb_scope = aml_scope("_SB");
1042 Aml *pci0_scope = aml_scope("PCI0");
1043
1044 aml_append(pci0_scope, build_prt(true));
1045 aml_append(sb_scope, pci0_scope);
1046
1047 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1048 aml_append(field, aml_named_field("PRQ0", 8));
1049 aml_append(field, aml_named_field("PRQ1", 8));
1050 aml_append(field, aml_named_field("PRQ2", 8));
1051 aml_append(field, aml_named_field("PRQ3", 8));
1052 aml_append(sb_scope, field);
1053
1054 aml_append(sb_scope, build_irq_status_method());
1055 aml_append(sb_scope, build_iqcr_method(true));
1056
1057 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
1058 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1059 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1060 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1061
1062 dev = aml_device("LNKS");
1063 {
1064 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1065 aml_append(dev, aml_name_decl("_UID", aml_int(4)));
1066
1067 crs = aml_resource_template();
1068 irqs = 9;
1069 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1070 AML_ACTIVE_HIGH, AML_SHARED,
1071 &irqs, 1));
1072 aml_append(dev, aml_name_decl("_PRS", crs));
1073
1074 /* The SCI cannot be disabled and is always attached to GSI 9,
1075 * so these are no-ops. We only need this link to override the
1076 * polarity to active high and match the content of the MADT.
1077 */
1078 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1079 aml_append(method, aml_return(aml_int(0x0b)));
1080 aml_append(dev, method);
1081
1082 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1083 aml_append(dev, method);
1084
1085 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1086 aml_append(method, aml_return(aml_name("_PRS")));
1087 aml_append(dev, method);
1088
1089 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1090 aml_append(dev, method);
1091 }
1092 aml_append(sb_scope, dev);
1093
1094 aml_append(table, sb_scope);
1095 }
1096
1097 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name)
1098 {
1099 int i;
1100 int head;
1101 Aml *pkg;
1102 char base = name[3] < 'E' ? 'A' : 'E';
1103 char *s = g_strdup(name);
1104 Aml *a_nr = aml_int((nr << 16) | 0xffff);
1105
1106 assert(strlen(s) == 4);
1107
1108 head = name[3] - base;
1109 for (i = 0; i < 4; i++) {
1110 if (head + i > 3) {
1111 head = i * -1;
1112 }
1113 s[3] = base + head + i;
1114 pkg = aml_package(4);
1115 aml_append(pkg, a_nr);
1116 aml_append(pkg, aml_int(i));
1117 aml_append(pkg, aml_name("%s", s));
1118 aml_append(pkg, aml_int(0));
1119 aml_append(ctx, pkg);
1120 }
1121 g_free(s);
1122 }
1123
1124 static Aml *build_q35_routing_table(const char *str)
1125 {
1126 int i;
1127 Aml *pkg;
1128 char *name = g_strdup_printf("%s ", str);
1129
1130 pkg = aml_package(128);
1131 for (i = 0; i < 0x18; i++) {
1132 name[3] = 'E' + (i & 0x3);
1133 append_q35_prt_entry(pkg, i, name);
1134 }
1135
1136 name[3] = 'E';
1137 append_q35_prt_entry(pkg, 0x18, name);
1138
1139 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
1140 for (i = 0x0019; i < 0x1e; i++) {
1141 name[3] = 'A';
1142 append_q35_prt_entry(pkg, i, name);
1143 }
1144
1145 /* PCIe->PCI bridge. use PIRQ[E-H] */
1146 name[3] = 'E';
1147 append_q35_prt_entry(pkg, 0x1e, name);
1148 name[3] = 'A';
1149 append_q35_prt_entry(pkg, 0x1f, name);
1150
1151 g_free(name);
1152 return pkg;
1153 }
1154
1155 static void build_q35_pci0_int(Aml *table)
1156 {
1157 Aml *field;
1158 Aml *method;
1159 Aml *sb_scope = aml_scope("_SB");
1160 Aml *pci0_scope = aml_scope("PCI0");
1161
1162 /* Zero => PIC mode, One => APIC Mode */
1163 aml_append(table, aml_name_decl("PICF", aml_int(0)));
1164 method = aml_method("_PIC", 1, AML_NOTSERIALIZED);
1165 {
1166 aml_append(method, aml_store(aml_arg(0), aml_name("PICF")));
1167 }
1168 aml_append(table, method);
1169
1170 aml_append(pci0_scope,
1171 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
1172 aml_append(pci0_scope,
1173 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1174
1175 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
1176 {
1177 Aml *if_ctx;
1178 Aml *else_ctx;
1179
1180 /* PCI IRQ routing table, example from ACPI 2.0a specification,
1181 section 6.2.8.1 */
1182 /* Note: we provide the same info as the PCI routing
1183 table of the Bochs BIOS */
1184 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1185 aml_append(if_ctx, aml_return(aml_name("PRTP")));
1186 aml_append(method, if_ctx);
1187 else_ctx = aml_else();
1188 aml_append(else_ctx, aml_return(aml_name("PRTA")));
1189 aml_append(method, else_ctx);
1190 }
1191 aml_append(pci0_scope, method);
1192 aml_append(sb_scope, pci0_scope);
1193
1194 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1195 aml_append(field, aml_named_field("PRQA", 8));
1196 aml_append(field, aml_named_field("PRQB", 8));
1197 aml_append(field, aml_named_field("PRQC", 8));
1198 aml_append(field, aml_named_field("PRQD", 8));
1199 aml_append(field, aml_reserved_field(0x20));
1200 aml_append(field, aml_named_field("PRQE", 8));
1201 aml_append(field, aml_named_field("PRQF", 8));
1202 aml_append(field, aml_named_field("PRQG", 8));
1203 aml_append(field, aml_named_field("PRQH", 8));
1204 aml_append(sb_scope, field);
1205
1206 aml_append(sb_scope, build_irq_status_method());
1207 aml_append(sb_scope, build_iqcr_method(false));
1208
1209 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA")));
1210 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB")));
1211 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC")));
1212 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD")));
1213 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE")));
1214 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF")));
1215 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG")));
1216 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH")));
1217
1218 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10));
1219 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11));
1220 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12));
1221 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13));
1222 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14));
1223 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15));
1224 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16));
1225 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17));
1226
1227 aml_append(table, sb_scope);
1228 }
1229
1230 static Aml *build_q35_dram_controller(const AcpiMcfgInfo *mcfg)
1231 {
1232 Aml *dev;
1233 Aml *resource_template;
1234
1235 /* DRAM controller */
1236 dev = aml_device("DRAC");
1237 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C01")));
1238
1239 resource_template = aml_resource_template();
1240 if (mcfg->base + mcfg->size - 1 >= (1ULL << 32)) {
1241 aml_append(resource_template,
1242 aml_qword_memory(AML_POS_DECODE,
1243 AML_MIN_FIXED,
1244 AML_MAX_FIXED,
1245 AML_NON_CACHEABLE,
1246 AML_READ_WRITE,
1247 0x0000000000000000,
1248 mcfg->base,
1249 mcfg->base + mcfg->size - 1,
1250 0x0000000000000000,
1251 mcfg->size));
1252 } else {
1253 aml_append(resource_template,
1254 aml_dword_memory(AML_POS_DECODE,
1255 AML_MIN_FIXED,
1256 AML_MAX_FIXED,
1257 AML_NON_CACHEABLE,
1258 AML_READ_WRITE,
1259 0x0000000000000000,
1260 mcfg->base,
1261 mcfg->base + mcfg->size - 1,
1262 0x0000000000000000,
1263 mcfg->size));
1264 }
1265 aml_append(dev, aml_name_decl("_CRS", resource_template));
1266
1267 return dev;
1268 }
1269
1270 static void build_q35_isa_bridge(Aml *table)
1271 {
1272 Aml *dev;
1273 Aml *scope;
1274 Object *obj;
1275 bool ambiguous;
1276
1277 /*
1278 * temporarily fish out isa bridge, build_q35_isa_bridge() will be dropped
1279 * once PCI is converted to AcpiDevAmlIf and would be ble to generate
1280 * AML for bridge itself
1281 */
1282 obj = object_resolve_path_type("", TYPE_ICH9_LPC_DEVICE, &ambiguous);
1283 assert(obj && !ambiguous);
1284
1285 scope = aml_scope("_SB.PCI0");
1286 dev = aml_device("ISA");
1287 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000)));
1288
1289 call_dev_aml_func(DEVICE(obj), dev);
1290 aml_append(scope, dev);
1291 aml_append(table, scope);
1292 }
1293
1294 static void build_piix4_isa_bridge(Aml *table)
1295 {
1296 Aml *dev;
1297 Aml *scope;
1298 Object *obj;
1299 bool ambiguous;
1300
1301 /*
1302 * temporarily fish out isa bridge, build_piix4_isa_bridge() will be dropped
1303 * once PCI is converted to AcpiDevAmlIf and would be ble to generate
1304 * AML for bridge itself
1305 */
1306 obj = object_resolve_path_type("", TYPE_PIIX3_PCI_DEVICE, &ambiguous);
1307 assert(obj && !ambiguous);
1308
1309 scope = aml_scope("_SB.PCI0");
1310 dev = aml_device("ISA");
1311 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000)));
1312
1313 call_dev_aml_func(DEVICE(obj), dev);
1314 aml_append(scope, dev);
1315 aml_append(table, scope);
1316 }
1317
1318 static void build_x86_acpi_pci_hotplug(Aml *table, uint64_t pcihp_addr)
1319 {
1320 Aml *scope;
1321 Aml *field;
1322 Aml *method;
1323
1324 scope = aml_scope("_SB.PCI0");
1325
1326 aml_append(scope,
1327 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(pcihp_addr), 0x08));
1328 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1329 aml_append(field, aml_named_field("PCIU", 32));
1330 aml_append(field, aml_named_field("PCID", 32));
1331 aml_append(scope, field);
1332
1333 aml_append(scope,
1334 aml_operation_region("SEJ", AML_SYSTEM_IO,
1335 aml_int(pcihp_addr + ACPI_PCIHP_SEJ_BASE), 0x04));
1336 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1337 aml_append(field, aml_named_field("B0EJ", 32));
1338 aml_append(scope, field);
1339
1340 aml_append(scope,
1341 aml_operation_region("BNMR", AML_SYSTEM_IO,
1342 aml_int(pcihp_addr + ACPI_PCIHP_BNMR_BASE), 0x08));
1343 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1344 aml_append(field, aml_named_field("BNUM", 32));
1345 aml_append(field, aml_named_field("PIDX", 32));
1346 aml_append(scope, field);
1347
1348 aml_append(scope, aml_mutex("BLCK", 0));
1349
1350 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED);
1351 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1352 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1353 aml_append(method,
1354 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1355 aml_append(method, aml_release(aml_name("BLCK")));
1356 aml_append(method, aml_return(aml_int(0)));
1357 aml_append(scope, method);
1358
1359 method = aml_method("AIDX", 2, AML_NOTSERIALIZED);
1360 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1361 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1362 aml_append(method,
1363 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("PIDX")));
1364 aml_append(method, aml_store(aml_name("PIDX"), aml_local(0)));
1365 aml_append(method, aml_release(aml_name("BLCK")));
1366 aml_append(method, aml_return(aml_local(0)));
1367 aml_append(scope, method);
1368
1369 aml_append(scope, aml_pci_pdsm());
1370
1371 aml_append(table, scope);
1372 }
1373
1374 static Aml *build_q35_osc_method(bool enable_native_pcie_hotplug)
1375 {
1376 Aml *if_ctx;
1377 Aml *if_ctx2;
1378 Aml *else_ctx;
1379 Aml *method;
1380 Aml *a_cwd1 = aml_name("CDW1");
1381 Aml *a_ctrl = aml_local(0);
1382
1383 method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
1384 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1385
1386 if_ctx = aml_if(aml_equal(
1387 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1388 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1389 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1390
1391 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl));
1392
1393 /*
1394 * Always allow native PME, AER (no dependencies)
1395 * Allow SHPC (PCI bridges can have SHPC controller)
1396 * Disable PCIe Native Hot-plug if ACPI PCI Hot-plug is enabled.
1397 */
1398 aml_append(if_ctx, aml_and(a_ctrl,
1399 aml_int(0x1E | (enable_native_pcie_hotplug ? 0x1 : 0x0)), a_ctrl));
1400
1401 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1402 /* Unknown revision */
1403 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1));
1404 aml_append(if_ctx, if_ctx2);
1405
1406 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
1407 /* Capabilities bits were masked */
1408 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1));
1409 aml_append(if_ctx, if_ctx2);
1410
1411 /* Update DWORD3 in the buffer */
1412 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3")));
1413 aml_append(method, if_ctx);
1414
1415 else_ctx = aml_else();
1416 /* Unrecognized UUID */
1417 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1));
1418 aml_append(method, else_ctx);
1419
1420 aml_append(method, aml_return(aml_arg(3)));
1421 return method;
1422 }
1423
1424 static void build_smb0(Aml *table, int devnr, int func)
1425 {
1426 Aml *scope = aml_scope("_SB.PCI0");
1427 Aml *dev = aml_device("SMB0");
1428 bool ambiguous;
1429 Object *obj;
1430 /*
1431 * temporarily fish out device hosting SMBUS, build_smb0 will be gone once
1432 * PCI enumeration will be switched to call_dev_aml_func()
1433 */
1434 obj = object_resolve_path_type("", TYPE_ICH9_SMB_DEVICE, &ambiguous);
1435 assert(obj && !ambiguous);
1436
1437 aml_append(dev, aml_name_decl("_ADR", aml_int(devnr << 16 | func)));
1438 call_dev_aml_func(DEVICE(obj), dev);
1439 aml_append(scope, dev);
1440 aml_append(table, scope);
1441 }
1442
1443 static void build_acpi0017(Aml *table)
1444 {
1445 Aml *dev, *scope, *method;
1446
1447 scope = aml_scope("_SB");
1448 dev = aml_device("CXLM");
1449 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0017")));
1450
1451 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1452 aml_append(method, aml_return(aml_int(0x01)));
1453 aml_append(dev, method);
1454
1455 aml_append(scope, dev);
1456 aml_append(table, scope);
1457 }
1458
1459 static void
1460 build_dsdt(GArray *table_data, BIOSLinker *linker,
1461 AcpiPmInfo *pm, AcpiMiscInfo *misc,
1462 Range *pci_hole, Range *pci_hole64, MachineState *machine)
1463 {
1464 CrsRangeEntry *entry;
1465 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs;
1466 CrsRangeSet crs_range_set;
1467 PCMachineState *pcms = PC_MACHINE(machine);
1468 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine);
1469 X86MachineState *x86ms = X86_MACHINE(machine);
1470 AcpiMcfgInfo mcfg;
1471 bool mcfg_valid = !!acpi_get_mcfg(&mcfg);
1472 uint32_t nr_mem = machine->ram_slots;
1473 int root_bus_limit = 0xFF;
1474 PCIBus *bus = NULL;
1475 #ifdef CONFIG_TPM
1476 TPMIf *tpm = tpm_find();
1477 #endif
1478 bool cxl_present = false;
1479 int i;
1480 VMBusBridge *vmbus_bridge = vmbus_bridge_find();
1481 AcpiTable table = { .sig = "DSDT", .rev = 1, .oem_id = x86ms->oem_id,
1482 .oem_table_id = x86ms->oem_table_id };
1483
1484 acpi_table_begin(&table, table_data);
1485 dsdt = init_aml_allocator();
1486
1487 build_dbg_aml(dsdt);
1488 if (misc->is_piix4) {
1489 sb_scope = aml_scope("_SB");
1490 dev = aml_device("PCI0");
1491 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1492 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1493 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid)));
1494 aml_append(sb_scope, dev);
1495 aml_append(dsdt, sb_scope);
1496
1497 build_piix4_isa_bridge(dsdt);
1498 if (pm->pcihp_bridge_en || pm->pcihp_root_en) {
1499 build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base);
1500 }
1501 build_piix4_pci0_int(dsdt);
1502 } else {
1503 sb_scope = aml_scope("_SB");
1504 dev = aml_device("PCI0");
1505 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1506 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1507 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1508 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid)));
1509 aml_append(dev, build_q35_osc_method(!pm->pcihp_bridge_en));
1510 aml_append(sb_scope, dev);
1511 if (mcfg_valid) {
1512 aml_append(sb_scope, build_q35_dram_controller(&mcfg));
1513 }
1514
1515 if (pm->smi_on_cpuhp) {
1516 /* reserve SMI block resources, IO ports 0xB2, 0xB3 */
1517 dev = aml_device("PCI0.SMI0");
1518 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06")));
1519 aml_append(dev, aml_name_decl("_UID", aml_string("SMI resources")));
1520 crs = aml_resource_template();
1521 aml_append(crs,
1522 aml_io(
1523 AML_DECODE16,
1524 ACPI_PORT_SMI_CMD,
1525 ACPI_PORT_SMI_CMD,
1526 1,
1527 2)
1528 );
1529 aml_append(dev, aml_name_decl("_CRS", crs));
1530 aml_append(dev, aml_operation_region("SMIR", AML_SYSTEM_IO,
1531 aml_int(ACPI_PORT_SMI_CMD), 2));
1532 field = aml_field("SMIR", AML_BYTE_ACC, AML_NOLOCK,
1533 AML_WRITE_AS_ZEROS);
1534 aml_append(field, aml_named_field("SMIC", 8));
1535 aml_append(field, aml_reserved_field(8));
1536 aml_append(dev, field);
1537 aml_append(sb_scope, dev);
1538 }
1539
1540 aml_append(dsdt, sb_scope);
1541
1542 build_q35_isa_bridge(dsdt);
1543 if (pm->pcihp_bridge_en) {
1544 build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base);
1545 }
1546 build_q35_pci0_int(dsdt);
1547 if (pcms->smbus) {
1548 build_smb0(dsdt, ICH9_SMB_DEV, ICH9_SMB_FUNC);
1549 }
1550 }
1551
1552 if (misc->has_hpet) {
1553 build_hpet_aml(dsdt);
1554 }
1555
1556 if (vmbus_bridge) {
1557 sb_scope = aml_scope("_SB");
1558 aml_append(sb_scope, build_vmbus_device_aml(vmbus_bridge));
1559 aml_append(dsdt, sb_scope);
1560 }
1561
1562 if (pcmc->legacy_cpu_hotplug) {
1563 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base);
1564 } else {
1565 CPUHotplugFeatures opts = {
1566 .acpi_1_compatible = true, .has_legacy_cphp = true,
1567 .smi_path = pm->smi_on_cpuhp ? "\\_SB.PCI0.SMI0.SMIC" : NULL,
1568 .fw_unplugs_cpu = pm->smi_on_cpu_unplug,
1569 };
1570 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base,
1571 "\\_SB.PCI0", "\\_GPE._E02");
1572 }
1573
1574 if (pcms->memhp_io_base && nr_mem) {
1575 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0",
1576 "\\_GPE._E03", AML_SYSTEM_IO,
1577 pcms->memhp_io_base);
1578 }
1579
1580 scope = aml_scope("_GPE");
1581 {
1582 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
1583
1584 if (pm->pcihp_bridge_en || pm->pcihp_root_en) {
1585 method = aml_method("_E01", 0, AML_NOTSERIALIZED);
1586 aml_append(method,
1587 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
1588 aml_append(method, aml_call0("\\_SB.PCI0.PCNT"));
1589 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK")));
1590 aml_append(scope, method);
1591 }
1592
1593 if (machine->nvdimms_state->is_enabled) {
1594 method = aml_method("_E04", 0, AML_NOTSERIALIZED);
1595 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"),
1596 aml_int(0x80)));
1597 aml_append(scope, method);
1598 }
1599 }
1600 aml_append(dsdt, scope);
1601
1602 crs_range_set_init(&crs_range_set);
1603 bus = PC_MACHINE(machine)->bus;
1604 if (bus) {
1605 QLIST_FOREACH(bus, &bus->child, sibling) {
1606 uint8_t bus_num = pci_bus_num(bus);
1607 uint8_t numa_node = pci_bus_numa_node(bus);
1608
1609 /* look only for expander root buses */
1610 if (!pci_bus_is_root(bus)) {
1611 continue;
1612 }
1613
1614 if (bus_num < root_bus_limit) {
1615 root_bus_limit = bus_num - 1;
1616 }
1617
1618 scope = aml_scope("\\_SB");
1619
1620 if (pci_bus_is_cxl(bus)) {
1621 dev = aml_device("CL%.02X", bus_num);
1622 } else {
1623 dev = aml_device("PC%.02X", bus_num);
1624 }
1625 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
1626 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
1627 if (pci_bus_is_cxl(bus)) {
1628 struct Aml *pkg = aml_package(2);
1629
1630 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0016")));
1631 aml_append(pkg, aml_eisaid("PNP0A08"));
1632 aml_append(pkg, aml_eisaid("PNP0A03"));
1633 aml_append(dev, aml_name_decl("_CID", pkg));
1634 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1635 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
1636 build_cxl_osc_method(dev);
1637 } else if (pci_bus_is_express(bus)) {
1638 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1639 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1640
1641 /* Expander bridges do not have ACPI PCI Hot-plug enabled */
1642 aml_append(dev, build_q35_osc_method(true));
1643 } else {
1644 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1645 }
1646
1647 if (numa_node != NUMA_NODE_UNASSIGNED) {
1648 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
1649 }
1650
1651 aml_append(dev, build_prt(false));
1652 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set,
1653 0, 0, 0, 0);
1654 aml_append(dev, aml_name_decl("_CRS", crs));
1655 aml_append(scope, dev);
1656 aml_append(dsdt, scope);
1657
1658 /* Handle the ranges for the PXB expanders */
1659 if (pci_bus_is_cxl(bus)) {
1660 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr;
1661 uint64_t base = mr->addr;
1662
1663 cxl_present = true;
1664 crs_range_insert(crs_range_set.mem_ranges, base,
1665 base + memory_region_size(mr) - 1);
1666 }
1667 }
1668 }
1669
1670 if (cxl_present) {
1671 build_acpi0017(dsdt);
1672 }
1673
1674 /*
1675 * At this point crs_range_set has all the ranges used by pci
1676 * busses *other* than PCI0. These ranges will be excluded from
1677 * the PCI0._CRS. Add mmconfig to the set so it will be excluded
1678 * too.
1679 */
1680 if (mcfg_valid) {
1681 crs_range_insert(crs_range_set.mem_ranges,
1682 mcfg.base, mcfg.base + mcfg.size - 1);
1683 }
1684
1685 scope = aml_scope("\\_SB.PCI0");
1686 /* build PCI0._CRS */
1687 crs = aml_resource_template();
1688 aml_append(crs,
1689 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
1690 0x0000, 0x0, root_bus_limit,
1691 0x0000, root_bus_limit + 1));
1692 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
1693
1694 aml_append(crs,
1695 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1696 AML_POS_DECODE, AML_ENTIRE_RANGE,
1697 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
1698
1699 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF);
1700 for (i = 0; i < crs_range_set.io_ranges->len; i++) {
1701 entry = g_ptr_array_index(crs_range_set.io_ranges, i);
1702 aml_append(crs,
1703 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1704 AML_POS_DECODE, AML_ENTIRE_RANGE,
1705 0x0000, entry->base, entry->limit,
1706 0x0000, entry->limit - entry->base + 1));
1707 }
1708
1709 aml_append(crs,
1710 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1711 AML_CACHEABLE, AML_READ_WRITE,
1712 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
1713
1714 crs_replace_with_free_ranges(crs_range_set.mem_ranges,
1715 range_lob(pci_hole),
1716 range_upb(pci_hole));
1717 for (i = 0; i < crs_range_set.mem_ranges->len; i++) {
1718 entry = g_ptr_array_index(crs_range_set.mem_ranges, i);
1719 aml_append(crs,
1720 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1721 AML_NON_CACHEABLE, AML_READ_WRITE,
1722 0, entry->base, entry->limit,
1723 0, entry->limit - entry->base + 1));
1724 }
1725
1726 if (!range_is_empty(pci_hole64)) {
1727 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges,
1728 range_lob(pci_hole64),
1729 range_upb(pci_hole64));
1730 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) {
1731 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i);
1732 aml_append(crs,
1733 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
1734 AML_MAX_FIXED,
1735 AML_CACHEABLE, AML_READ_WRITE,
1736 0, entry->base, entry->limit,
1737 0, entry->limit - entry->base + 1));
1738 }
1739 }
1740
1741 #ifdef CONFIG_TPM
1742 if (TPM_IS_TIS_ISA(tpm_find())) {
1743 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
1744 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
1745 }
1746 #endif
1747 aml_append(scope, aml_name_decl("_CRS", crs));
1748
1749 /* reserve GPE0 block resources */
1750 dev = aml_device("GPE0");
1751 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1752 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
1753 /* device present, functioning, decoding, not shown in UI */
1754 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1755 crs = aml_resource_template();
1756 aml_append(crs,
1757 aml_io(
1758 AML_DECODE16,
1759 pm->fadt.gpe0_blk.address,
1760 pm->fadt.gpe0_blk.address,
1761 1,
1762 pm->fadt.gpe0_blk.bit_width / 8)
1763 );
1764 aml_append(dev, aml_name_decl("_CRS", crs));
1765 aml_append(scope, dev);
1766
1767 crs_range_set_free(&crs_range_set);
1768
1769 /* reserve PCIHP resources */
1770 if (pm->pcihp_io_len && (pm->pcihp_bridge_en || pm->pcihp_root_en)) {
1771 dev = aml_device("PHPR");
1772 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1773 aml_append(dev,
1774 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
1775 /* device present, functioning, decoding, not shown in UI */
1776 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1777 crs = aml_resource_template();
1778 aml_append(crs,
1779 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
1780 pm->pcihp_io_len)
1781 );
1782 aml_append(dev, aml_name_decl("_CRS", crs));
1783 aml_append(scope, dev);
1784 }
1785 aml_append(dsdt, scope);
1786
1787 /* create S3_ / S4_ / S5_ packages if necessary */
1788 scope = aml_scope("\\");
1789 if (!pm->s3_disabled) {
1790 pkg = aml_package(4);
1791 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
1792 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1793 aml_append(pkg, aml_int(0)); /* reserved */
1794 aml_append(pkg, aml_int(0)); /* reserved */
1795 aml_append(scope, aml_name_decl("_S3", pkg));
1796 }
1797
1798 if (!pm->s4_disabled) {
1799 pkg = aml_package(4);
1800 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
1801 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1802 aml_append(pkg, aml_int(pm->s4_val));
1803 aml_append(pkg, aml_int(0)); /* reserved */
1804 aml_append(pkg, aml_int(0)); /* reserved */
1805 aml_append(scope, aml_name_decl("_S4", pkg));
1806 }
1807
1808 pkg = aml_package(4);
1809 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
1810 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
1811 aml_append(pkg, aml_int(0)); /* reserved */
1812 aml_append(pkg, aml_int(0)); /* reserved */
1813 aml_append(scope, aml_name_decl("_S5", pkg));
1814 aml_append(dsdt, scope);
1815
1816 /* create fw_cfg node, unconditionally */
1817 {
1818 scope = aml_scope("\\_SB.PCI0");
1819 fw_cfg_add_acpi_dsdt(scope, x86ms->fw_cfg);
1820 aml_append(dsdt, scope);
1821 }
1822
1823 sb_scope = aml_scope("\\_SB");
1824 {
1825 Object *pci_host = acpi_get_i386_pci_host();
1826
1827 if (pci_host) {
1828 PCIBus *bus = PCI_HOST_BRIDGE(pci_host)->bus;
1829 Aml *scope = aml_scope("PCI0");
1830 /* Scan all PCI buses. Generate tables to support hotplug. */
1831 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en);
1832 aml_append(sb_scope, scope);
1833 }
1834 }
1835
1836 #ifdef CONFIG_TPM
1837 if (TPM_IS_CRB(tpm)) {
1838 dev = aml_device("TPM");
1839 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101")));
1840 aml_append(dev, aml_name_decl("_STR",
1841 aml_string("TPM 2.0 Device")));
1842 crs = aml_resource_template();
1843 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE,
1844 TPM_CRB_ADDR_SIZE, AML_READ_WRITE));
1845 aml_append(dev, aml_name_decl("_CRS", crs));
1846
1847 aml_append(dev, aml_name_decl("_STA", aml_int(0xf)));
1848 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
1849
1850 tpm_build_ppi_acpi(tpm, dev);
1851
1852 aml_append(sb_scope, dev);
1853 }
1854 #endif
1855
1856 if (pcms->sgx_epc.size != 0) {
1857 uint64_t epc_base = pcms->sgx_epc.base;
1858 uint64_t epc_size = pcms->sgx_epc.size;
1859
1860 dev = aml_device("EPC");
1861 aml_append(dev, aml_name_decl("_HID", aml_eisaid("INT0E0C")));
1862 aml_append(dev, aml_name_decl("_STR",
1863 aml_unicode("Enclave Page Cache 1.0")));
1864 crs = aml_resource_template();
1865 aml_append(crs,
1866 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
1867 AML_MAX_FIXED, AML_NON_CACHEABLE,
1868 AML_READ_WRITE, 0, epc_base,
1869 epc_base + epc_size - 1, 0, epc_size));
1870 aml_append(dev, aml_name_decl("_CRS", crs));
1871
1872 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1873 aml_append(method, aml_return(aml_int(0x0f)));
1874 aml_append(dev, method);
1875
1876 aml_append(sb_scope, dev);
1877 }
1878 aml_append(dsdt, sb_scope);
1879
1880 /* copy AML table into ACPI tables blob and patch header there */
1881 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
1882 acpi_table_end(linker, &table);
1883 free_aml_allocator();
1884 }
1885
1886 /*
1887 * IA-PC HPET (High Precision Event Timers) Specification (Revision: 1.0a)
1888 * 3.2.4The ACPI 2.0 HPET Description Table (HPET)
1889 */
1890 static void
1891 build_hpet(GArray *table_data, BIOSLinker *linker, const char *oem_id,
1892 const char *oem_table_id)
1893 {
1894 AcpiTable table = { .sig = "HPET", .rev = 1,
1895 .oem_id = oem_id, .oem_table_id = oem_table_id };
1896
1897 acpi_table_begin(&table, table_data);
1898 /* Note timer_block_id value must be kept in sync with value advertised by
1899 * emulated hpet
1900 */
1901 /* Event Timer Block ID */
1902 build_append_int_noprefix(table_data, 0x8086a201, 4);
1903 /* BASE_ADDRESS */
1904 build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 0, 0, 0, HPET_BASE);
1905 /* HPET Number */
1906 build_append_int_noprefix(table_data, 0, 1);
1907 /* Main Counter Minimum Clock_tick in Periodic Mode */
1908 build_append_int_noprefix(table_data, 0, 2);
1909 /* Page Protection And OEM Attribute */
1910 build_append_int_noprefix(table_data, 0, 1);
1911 acpi_table_end(linker, &table);
1912 }
1913
1914 #ifdef CONFIG_TPM
1915 /*
1916 * TCPA Description Table
1917 *
1918 * Following Level 00, Rev 00.37 of specs:
1919 * http://www.trustedcomputinggroup.org/resources/tcg_acpi_specification
1920 * 7.1.2 ACPI Table Layout
1921 */
1922 static void
1923 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog,
1924 const char *oem_id, const char *oem_table_id)
1925 {
1926 unsigned log_addr_offset;
1927 AcpiTable table = { .sig = "TCPA", .rev = 2,
1928 .oem_id = oem_id, .oem_table_id = oem_table_id };
1929
1930 acpi_table_begin(&table, table_data);
1931 /* Platform Class */
1932 build_append_int_noprefix(table_data, TPM_TCPA_ACPI_CLASS_CLIENT, 2);
1933 /* Log Area Minimum Length (LAML) */
1934 build_append_int_noprefix(table_data, TPM_LOG_AREA_MINIMUM_SIZE, 4);
1935 /* Log Area Start Address (LASA) */
1936 log_addr_offset = table_data->len;
1937 build_append_int_noprefix(table_data, 0, 8);
1938
1939 /* allocate/reserve space for TPM log area */
1940 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE);
1941 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1,
1942 false /* high memory */);
1943 /* log area start address to be filled by Guest linker */
1944 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
1945 log_addr_offset, 8, ACPI_BUILD_TPMLOG_FILE, 0);
1946
1947 acpi_table_end(linker, &table);
1948 }
1949 #endif
1950
1951 #define HOLE_640K_START (640 * KiB)
1952 #define HOLE_640K_END (1 * MiB)
1953
1954 /*
1955 * ACPI spec, Revision 3.0
1956 * 5.2.15 System Resource Affinity Table (SRAT)
1957 */
1958 static void
1959 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
1960 {
1961 int i;
1962 int numa_mem_start, slots;
1963 uint64_t mem_len, mem_base, next_base;
1964 MachineClass *mc = MACHINE_GET_CLASS(machine);
1965 X86MachineState *x86ms = X86_MACHINE(machine);
1966 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine);
1967 PCMachineState *pcms = PC_MACHINE(machine);
1968 int nb_numa_nodes = machine->numa_state->num_nodes;
1969 NodeInfo *numa_info = machine->numa_state->nodes;
1970 ram_addr_t hotpluggable_address_space_size =
1971 object_property_get_int(OBJECT(pcms), PC_MACHINE_DEVMEM_REGION_SIZE,
1972 NULL);
1973 AcpiTable table = { .sig = "SRAT", .rev = 1, .oem_id = x86ms->oem_id,
1974 .oem_table_id = x86ms->oem_table_id };
1975
1976 acpi_table_begin(&table, table_data);
1977 build_append_int_noprefix(table_data, 1, 4); /* Reserved */
1978 build_append_int_noprefix(table_data, 0, 8); /* Reserved */
1979
1980 for (i = 0; i < apic_ids->len; i++) {
1981 int node_id = apic_ids->cpus[i].props.node_id;
1982 uint32_t apic_id = apic_ids->cpus[i].arch_id;
1983
1984 if (apic_id < 255) {
1985 /* 5.2.15.1 Processor Local APIC/SAPIC Affinity Structure */
1986 build_append_int_noprefix(table_data, 0, 1); /* Type */
1987 build_append_int_noprefix(table_data, 16, 1); /* Length */
1988 /* Proximity Domain [7:0] */
1989 build_append_int_noprefix(table_data, node_id, 1);
1990 build_append_int_noprefix(table_data, apic_id, 1); /* APIC ID */
1991 /* Flags, Table 5-36 */
1992 build_append_int_noprefix(table_data, 1, 4);
1993 build_append_int_noprefix(table_data, 0, 1); /* Local SAPIC EID */
1994 /* Proximity Domain [31:8] */
1995 build_append_int_noprefix(table_data, 0, 3);
1996 build_append_int_noprefix(table_data, 0, 4); /* Reserved */
1997 } else {
1998 /*
1999 * ACPI spec, Revision 4.0
2000 * 5.2.16.3 Processor Local x2APIC Affinity Structure
2001 */
2002 build_append_int_noprefix(table_data, 2, 1); /* Type */
2003 build_append_int_noprefix(table_data, 24, 1); /* Length */
2004 build_append_int_noprefix(table_data, 0, 2); /* Reserved */
2005 /* Proximity Domain */
2006 build_append_int_noprefix(table_data, node_id, 4);
2007 build_append_int_noprefix(table_data, apic_id, 4); /* X2APIC ID */
2008 /* Flags, Table 5-39 */
2009 build_append_int_noprefix(table_data, 1 /* Enabled */, 4);
2010 build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */
2011 build_append_int_noprefix(table_data, 0, 4); /* Reserved */
2012 }
2013 }
2014
2015 /* the memory map is a bit tricky, it contains at least one hole
2016 * from 640k-1M and possibly another one from 3.5G-4G.
2017 */
2018 next_base = 0;
2019 numa_mem_start = table_data->len;
2020
2021 for (i = 1; i < nb_numa_nodes + 1; ++i) {
2022 mem_base = next_base;
2023 mem_len = numa_info[i - 1].node_mem;
2024 next_base = mem_base + mem_len;
2025
2026 /* Cut out the 640K hole */
2027 if (mem_base <= HOLE_640K_START &&
2028 next_base > HOLE_640K_START) {
2029 mem_len -= next_base - HOLE_640K_START;
2030 if (mem_len > 0) {
2031 build_srat_memory(table_data, mem_base, mem_len, i - 1,
2032 MEM_AFFINITY_ENABLED);
2033 }
2034
2035 /* Check for the rare case: 640K < RAM < 1M */
2036 if (next_base <= HOLE_640K_END) {
2037 next_base = HOLE_640K_END;
2038 continue;
2039 }
2040 mem_base = HOLE_640K_END;
2041 mem_len = next_base - HOLE_640K_END;
2042 }
2043
2044 /* Cut out the ACPI_PCI hole */
2045 if (mem_base <= x86ms->below_4g_mem_size &&
2046 next_base > x86ms->below_4g_mem_size) {
2047 mem_len -= next_base - x86ms->below_4g_mem_size;
2048 if (mem_len > 0) {
2049 build_srat_memory(table_data, mem_base, mem_len, i - 1,
2050 MEM_AFFINITY_ENABLED);
2051 }
2052 mem_base = x86ms->above_4g_mem_start;
2053 mem_len = next_base - x86ms->below_4g_mem_size;
2054 next_base = mem_base + mem_len;
2055 }
2056
2057 if (mem_len > 0) {
2058 build_srat_memory(table_data, mem_base, mem_len, i - 1,
2059 MEM_AFFINITY_ENABLED);
2060 }
2061 }
2062
2063 if (machine->nvdimms_state->is_enabled) {
2064 nvdimm_build_srat(table_data);
2065 }
2066
2067 sgx_epc_build_srat(table_data);
2068
2069 /*
2070 * TODO: this part is not in ACPI spec and current linux kernel boots fine
2071 * without these entries. But I recall there were issues the last time I
2072 * tried to remove it with some ancient guest OS, however I can't remember
2073 * what that was so keep this around for now
2074 */
2075 slots = (table_data->len - numa_mem_start) / 40 /* mem affinity len */;
2076 for (; slots < nb_numa_nodes + 2; slots++) {
2077 build_srat_memory(table_data, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
2078 }
2079
2080 /*
2081 * Entry is required for Windows to enable memory hotplug in OS
2082 * and for Linux to enable SWIOTLB when booted with less than
2083 * 4G of RAM. Windows works better if the entry sets proximity
2084 * to the highest NUMA node in the machine.
2085 * Memory devices may override proximity set by this entry,
2086 * providing _PXM method if necessary.
2087 */
2088 if (hotpluggable_address_space_size) {
2089 build_srat_memory(table_data, machine->device_memory->base,
2090 hotpluggable_address_space_size, nb_numa_nodes - 1,
2091 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
2092 }
2093
2094 acpi_table_end(linker, &table);
2095 }
2096
2097 /*
2098 * Insert DMAR scope for PCI bridges and endpoint devcie
2099 */
2100 static void
2101 insert_scope(PCIBus *bus, PCIDevice *dev, void *opaque)
2102 {
2103 const size_t device_scope_size = 6 /* device scope structure */ +
2104 2 /* 1 path entry */;
2105 GArray *scope_blob = opaque;
2106
2107 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) {
2108 /* Dmar Scope Type: 0x02 for PCI Bridge */
2109 build_append_int_noprefix(scope_blob, 0x02, 1);
2110 } else {
2111 /* Dmar Scope Type: 0x01 for PCI Endpoint Device */
2112 build_append_int_noprefix(scope_blob, 0x01, 1);
2113 }
2114
2115 /* length */
2116 build_append_int_noprefix(scope_blob, device_scope_size, 1);
2117 /* reserved */
2118 build_append_int_noprefix(scope_blob, 0, 2);
2119 /* enumeration_id */
2120 build_append_int_noprefix(scope_blob, 0, 1);
2121 /* bus */
2122 build_append_int_noprefix(scope_blob, pci_bus_num(bus), 1);
2123 /* device */
2124 build_append_int_noprefix(scope_blob, PCI_SLOT(dev->devfn), 1);
2125 /* function */
2126 build_append_int_noprefix(scope_blob, PCI_FUNC(dev->devfn), 1);
2127 }
2128
2129 /* For a given PCI host bridge, walk and insert DMAR scope */
2130 static int
2131 dmar_host_bridges(Object *obj, void *opaque)
2132 {
2133 GArray *scope_blob = opaque;
2134
2135 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) {
2136 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus;
2137
2138 if (bus && !pci_bus_bypass_iommu(bus)) {
2139 pci_for_each_device_under_bus(bus, insert_scope, scope_blob);
2140 }
2141 }
2142
2143 return 0;
2144 }
2145
2146 /*
2147 * Intel ® Virtualization Technology for Directed I/O
2148 * Architecture Specification. Revision 3.3
2149 * 8.1 DMA Remapping Reporting Structure
2150 */
2151 static void
2152 build_dmar_q35(GArray *table_data, BIOSLinker *linker, const char *oem_id,
2153 const char *oem_table_id)
2154 {
2155 uint8_t dmar_flags = 0;
2156 uint8_t rsvd10[10] = {};
2157 /* Root complex IOAPIC uses one path only */
2158 const size_t ioapic_scope_size = 6 /* device scope structure */ +
2159 2 /* 1 path entry */;
2160 X86IOMMUState *iommu = x86_iommu_get_default();
2161 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu);
2162 GArray *scope_blob = g_array_new(false, true, 1);
2163
2164 AcpiTable table = { .sig = "DMAR", .rev = 1, .oem_id = oem_id,
2165 .oem_table_id = oem_table_id };
2166
2167 /*
2168 * A PCI bus walk, for each PCI host bridge.
2169 * Insert scope for each PCI bridge and endpoint device which
2170 * is attached to a bus with iommu enabled.
2171 */
2172 object_child_foreach_recursive(object_get_root(),
2173 dmar_host_bridges, scope_blob);
2174
2175 assert(iommu);
2176 if (x86_iommu_ir_supported(iommu)) {
2177 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */
2178 }
2179
2180 acpi_table_begin(&table, table_data);
2181 /* Host Address Width */
2182 build_append_int_noprefix(table_data, intel_iommu->aw_bits - 1, 1);
2183 build_append_int_noprefix(table_data, dmar_flags, 1); /* Flags */
2184 g_array_append_vals(table_data, rsvd10, sizeof(rsvd10)); /* Reserved */
2185
2186 /* 8.3 DMAR Remapping Hardware Unit Definition structure */
2187 build_append_int_noprefix(table_data, 0, 2); /* Type */
2188 /* Length */
2189 build_append_int_noprefix(table_data,
2190 16 + ioapic_scope_size + scope_blob->len, 2);
2191 /* Flags */
2192 build_append_int_noprefix(table_data, 0 /* Don't include all pci device */ ,
2193 1);
2194 build_append_int_noprefix(table_data, 0 , 1); /* Reserved */
2195 build_append_int_noprefix(table_data, 0 , 2); /* Segment Number */
2196 /* Register Base Address */
2197 build_append_int_noprefix(table_data, Q35_HOST_BRIDGE_IOMMU_ADDR , 8);
2198
2199 /* Scope definition for the root-complex IOAPIC. See VT-d spec
2200 * 8.3.1 (version Oct. 2014 or later). */
2201 build_append_int_noprefix(table_data, 0x03 /* IOAPIC */, 1); /* Type */
2202 build_append_int_noprefix(table_data, ioapic_scope_size, 1); /* Length */
2203 build_append_int_noprefix(table_data, 0, 2); /* Reserved */
2204 /* Enumeration ID */
2205 build_append_int_noprefix(table_data, ACPI_BUILD_IOAPIC_ID, 1);
2206 /* Start Bus Number */
2207 build_append_int_noprefix(table_data, Q35_PSEUDO_BUS_PLATFORM, 1);
2208 /* Path, {Device, Function} pair */
2209 build_append_int_noprefix(table_data, PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC), 1);
2210 build_append_int_noprefix(table_data, PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC), 1);
2211
2212 /* Add scope found above */
2213 g_array_append_vals(table_data, scope_blob->data, scope_blob->len);
2214 g_array_free(scope_blob, true);
2215
2216 if (iommu->dt_supported) {
2217 /* 8.5 Root Port ATS Capability Reporting Structure */
2218 build_append_int_noprefix(table_data, 2, 2); /* Type */
2219 build_append_int_noprefix(table_data, 8, 2); /* Length */
2220 build_append_int_noprefix(table_data, 1 /* ALL_PORTS */, 1); /* Flags */
2221 build_append_int_noprefix(table_data, 0, 1); /* Reserved */
2222 build_append_int_noprefix(table_data, 0, 2); /* Segment Number */
2223 }
2224
2225 acpi_table_end(linker, &table);
2226 }
2227
2228 /*
2229 * Windows ACPI Emulated Devices Table
2230 * (Version 1.0 - April 6, 2009)
2231 * Spec: http://download.microsoft.com/download/7/E/7/7E7662CF-CBEA-470B-A97E-CE7CE0D98DC2/WAET.docx
2232 *
2233 * Helpful to speedup Windows guests and ignored by others.
2234 */
2235 static void
2236 build_waet(GArray *table_data, BIOSLinker *linker, const char *oem_id,
2237 const char *oem_table_id)
2238 {
2239 AcpiTable table = { .sig = "WAET", .rev = 1, .oem_id = oem_id,
2240 .oem_table_id = oem_table_id };
2241
2242 acpi_table_begin(&table, table_data);
2243 /*
2244 * Set "ACPI PM timer good" flag.
2245 *
2246 * Tells Windows guests that our ACPI PM timer is reliable in the
2247 * sense that guest can read it only once to obtain a reliable value.
2248 * Which avoids costly VMExits caused by guest re-reading it unnecessarily.
2249 */
2250 build_append_int_noprefix(table_data, 1 << 1 /* ACPI PM timer good */, 4);
2251 acpi_table_end(linker, &table);
2252 }
2253
2254 /*
2255 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2
2256 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf
2257 */
2258 #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0))
2259
2260 /*
2261 * Insert IVHD entry for device and recurse, insert alias, or insert range as
2262 * necessary for the PCI topology.
2263 */
2264 static void
2265 insert_ivhd(PCIBus *bus, PCIDevice *dev, void *opaque)
2266 {
2267 GArray *table_data = opaque;
2268 uint32_t entry;
2269
2270 /* "Select" IVHD entry, type 0x2 */
2271 entry = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn) << 8 | 0x2;
2272 build_append_int_noprefix(table_data, entry, 4);
2273
2274 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) {
2275 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev));
2276 uint8_t sec = pci_bus_num(sec_bus);
2277 uint8_t sub = dev->config[PCI_SUBORDINATE_BUS];
2278
2279 if (pci_bus_is_express(sec_bus)) {
2280 /*
2281 * Walk the bus if there are subordinates, otherwise use a range
2282 * to cover an entire leaf bus. We could potentially also use a
2283 * range for traversed buses, but we'd need to take care not to
2284 * create both Select and Range entries covering the same device.
2285 * This is easier and potentially more compact.
2286 *
2287 * An example bare metal system seems to use Select entries for
2288 * root ports without a slot (ie. built-ins) and Range entries
2289 * when there is a slot. The same system also only hard-codes
2290 * the alias range for an onboard PCIe-to-PCI bridge, apparently
2291 * making no effort to support nested bridges. We attempt to
2292 * be more thorough here.
2293 */
2294 if (sec == sub) { /* leaf bus */
2295 /* "Start of Range" IVHD entry, type 0x3 */
2296 entry = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)) << 8 | 0x3;
2297 build_append_int_noprefix(table_data, entry, 4);
2298 /* "End of Range" IVHD entry, type 0x4 */
2299 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4;
2300 build_append_int_noprefix(table_data, entry, 4);
2301 } else {
2302 pci_for_each_device(sec_bus, sec, insert_ivhd, table_data);
2303 }
2304 } else {
2305 /*
2306 * If the secondary bus is conventional, then we need to create an
2307 * Alias range for everything downstream. The range covers the
2308 * first devfn on the secondary bus to the last devfn on the
2309 * subordinate bus. The alias target depends on legacy versus
2310 * express bridges, just as in pci_device_iommu_address_space().
2311 * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec.
2312 */
2313 uint16_t dev_id_a, dev_id_b;
2314
2315 dev_id_a = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0));
2316
2317 if (pci_is_express(dev) &&
2318 pcie_cap_get_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) {
2319 dev_id_b = dev_id_a;
2320 } else {
2321 dev_id_b = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn);
2322 }
2323
2324 /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */
2325 build_append_int_noprefix(table_data, dev_id_a << 8 | 0x43, 4);
2326 build_append_int_noprefix(table_data, dev_id_b << 8 | 0x0, 4);
2327
2328 /* "End of Range" IVHD entry, type 0x4 */
2329 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4;
2330 build_append_int_noprefix(table_data, entry, 4);
2331 }
2332 }
2333 }
2334
2335 /* For all PCI host bridges, walk and insert IVHD entries */
2336 static int
2337 ivrs_host_bridges(Object *obj, void *opaque)
2338 {
2339 GArray *ivhd_blob = opaque;
2340
2341 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) {
2342 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus;
2343
2344 if (bus && !pci_bus_bypass_iommu(bus)) {
2345 pci_for_each_device_under_bus(bus, insert_ivhd, ivhd_blob);
2346 }
2347 }
2348
2349 return 0;
2350 }
2351
2352 static void
2353 build_amd_iommu(GArray *table_data, BIOSLinker *linker, const char *oem_id,
2354 const char *oem_table_id)
2355 {
2356 int ivhd_table_len = 24;
2357 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default());
2358 GArray *ivhd_blob = g_array_new(false, true, 1);
2359 AcpiTable table = { .sig = "IVRS", .rev = 1, .oem_id = oem_id,
2360 .oem_table_id = oem_table_id };
2361
2362 acpi_table_begin(&table, table_data);
2363 /* IVinfo - IO virtualization information common to all
2364 * IOMMU units in a system
2365 */
2366 build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4);
2367 /* reserved */
2368 build_append_int_noprefix(table_data, 0, 8);
2369
2370 /* IVHD definition - type 10h */
2371 build_append_int_noprefix(table_data, 0x10, 1);
2372 /* virtualization flags */
2373 build_append_int_noprefix(table_data,
2374 (1UL << 0) | /* HtTunEn */
2375 (1UL << 4) | /* iotblSup */
2376 (1UL << 6) | /* PrefSup */
2377 (1UL << 7), /* PPRSup */
2378 1);
2379
2380 /*
2381 * A PCI bus walk, for each PCI host bridge, is necessary to create a
2382 * complete set of IVHD entries. Do this into a separate blob so that we
2383 * can calculate the total IVRS table length here and then append the new
2384 * blob further below. Fall back to an entry covering all devices, which
2385 * is sufficient when no aliases are present.
2386 */
2387 object_child_foreach_recursive(object_get_root(),
2388 ivrs_host_bridges, ivhd_blob);
2389
2390 if (!ivhd_blob->len) {
2391 /*
2392 * Type 1 device entry reporting all devices
2393 * These are 4-byte device entries currently reporting the range of
2394 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte)
2395 */
2396 build_append_int_noprefix(ivhd_blob, 0x0000001, 4);
2397 }
2398
2399 ivhd_table_len += ivhd_blob->len;
2400
2401 /*
2402 * When interrupt remapping is supported, we add a special IVHD device
2403 * for type IO-APIC.
2404 */
2405 if (x86_iommu_ir_supported(x86_iommu_get_default())) {
2406 ivhd_table_len += 8;
2407 }
2408
2409 /* IVHD length */
2410 build_append_int_noprefix(table_data, ivhd_table_len, 2);
2411 /* DeviceID */
2412 build_append_int_noprefix(table_data, s->devid, 2);
2413 /* Capability offset */
2414 build_append_int_noprefix(table_data, s->capab_offset, 2);
2415 /* IOMMU base address */
2416 build_append_int_noprefix(table_data, s->mmio.addr, 8);
2417 /* PCI Segment Group */
2418 build_append_int_noprefix(table_data, 0, 2);
2419 /* IOMMU info */
2420 build_append_int_noprefix(table_data, 0, 2);
2421 /* IOMMU Feature Reporting */
2422 build_append_int_noprefix(table_data,
2423 (48UL << 30) | /* HATS */
2424 (48UL << 28) | /* GATS */
2425 (1UL << 2) | /* GTSup */
2426 (1UL << 6), /* GASup */
2427 4);
2428
2429 /* IVHD entries as found above */
2430 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len);
2431 g_array_free(ivhd_blob, TRUE);
2432
2433 /*
2434 * Add a special IVHD device type.
2435 * Refer to spec - Table 95: IVHD device entry type codes
2436 *
2437 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC).
2438 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059'
2439 */
2440 if (x86_iommu_ir_supported(x86_iommu_get_default())) {
2441 build_append_int_noprefix(table_data,
2442 (0x1ull << 56) | /* type IOAPIC */
2443 (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */
2444 0x48, /* special device */
2445 8);
2446 }
2447 acpi_table_end(linker, &table);
2448 }
2449
2450 typedef
2451 struct AcpiBuildState {
2452 /* Copy of table in RAM (for patching). */
2453 MemoryRegion *table_mr;
2454 /* Is table patched? */
2455 uint8_t patched;
2456 void *rsdp;
2457 MemoryRegion *rsdp_mr;
2458 MemoryRegion *linker_mr;
2459 } AcpiBuildState;
2460
2461 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
2462 {
2463 Object *pci_host;
2464 QObject *o;
2465
2466 pci_host = acpi_get_i386_pci_host();
2467 if (!pci_host) {
2468 return false;
2469 }
2470
2471 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
2472 if (!o) {
2473 return false;
2474 }
2475 mcfg->base = qnum_get_uint(qobject_to(QNum, o));
2476 qobject_unref(o);
2477 if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) {
2478 return false;
2479 }
2480
2481 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
2482 assert(o);
2483 mcfg->size = qnum_get_uint(qobject_to(QNum, o));
2484 qobject_unref(o);
2485 return true;
2486 }
2487
2488 static
2489 void acpi_build(AcpiBuildTables *tables, MachineState *machine)
2490 {
2491 PCMachineState *pcms = PC_MACHINE(machine);
2492 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2493 X86MachineState *x86ms = X86_MACHINE(machine);
2494 DeviceState *iommu = pcms->iommu;
2495 GArray *table_offsets;
2496 unsigned facs, dsdt, rsdt, fadt;
2497 AcpiPmInfo pm;
2498 AcpiMiscInfo misc;
2499 AcpiMcfgInfo mcfg;
2500 Range pci_hole = {}, pci_hole64 = {};
2501 uint8_t *u;
2502 size_t aml_len = 0;
2503 GArray *tables_blob = tables->table_data;
2504 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL };
2505 Object *vmgenid_dev;
2506 char *oem_id;
2507 char *oem_table_id;
2508
2509 acpi_get_pm_info(machine, &pm);
2510 acpi_get_misc_info(&misc);
2511 acpi_get_pci_holes(&pci_hole, &pci_hole64);
2512 acpi_get_slic_oem(&slic_oem);
2513
2514 if (slic_oem.id) {
2515 oem_id = slic_oem.id;
2516 } else {
2517 oem_id = x86ms->oem_id;
2518 }
2519
2520 if (slic_oem.table_id) {
2521 oem_table_id = slic_oem.table_id;
2522 } else {
2523 oem_table_id = x86ms->oem_table_id;
2524 }
2525
2526 table_offsets = g_array_new(false, true /* clear */,
2527 sizeof(uint32_t));
2528 ACPI_BUILD_DPRINTF("init ACPI tables\n");
2529
2530 bios_linker_loader_alloc(tables->linker,
2531 ACPI_BUILD_TABLE_FILE, tables_blob,
2532 64 /* Ensure FACS is aligned */,
2533 false /* high memory */);
2534
2535 /*
2536 * FACS is pointed to by FADT.
2537 * We place it first since it's the only table that has alignment
2538 * requirements.
2539 */
2540 facs = tables_blob->len;
2541 build_facs(tables_blob);
2542
2543 /* DSDT is pointed to by FADT */
2544 dsdt = tables_blob->len;
2545 build_dsdt(tables_blob, tables->linker, &pm, &misc,
2546 &pci_hole, &pci_hole64, machine);
2547
2548 /* Count the size of the DSDT and SSDT, we will need it for legacy
2549 * sizing of ACPI tables.
2550 */
2551 aml_len += tables_blob->len - dsdt;
2552
2553 /* ACPI tables pointed to by RSDT */
2554 fadt = tables_blob->len;
2555 acpi_add_table(table_offsets, tables_blob);
2556 pm.fadt.facs_tbl_offset = &facs;
2557 pm.fadt.dsdt_tbl_offset = &dsdt;
2558 pm.fadt.xdsdt_tbl_offset = &dsdt;
2559 build_fadt(tables_blob, tables->linker, &pm.fadt, oem_id, oem_table_id);
2560 aml_len += tables_blob->len - fadt;
2561
2562 acpi_add_table(table_offsets, tables_blob);
2563 acpi_build_madt(tables_blob, tables->linker, x86ms,
2564 ACPI_DEVICE_IF(x86ms->acpi_dev), x86ms->oem_id,
2565 x86ms->oem_table_id);
2566
2567 #ifdef CONFIG_ACPI_ERST
2568 {
2569 Object *erst_dev;
2570 erst_dev = find_erst_dev();
2571 if (erst_dev) {
2572 acpi_add_table(table_offsets, tables_blob);
2573 build_erst(tables_blob, tables->linker, erst_dev,
2574 x86ms->oem_id, x86ms->oem_table_id);
2575 }
2576 }
2577 #endif
2578
2579 vmgenid_dev = find_vmgenid_dev();
2580 if (vmgenid_dev) {
2581 acpi_add_table(table_offsets, tables_blob);
2582 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob,
2583 tables->vmgenid, tables->linker, x86ms->oem_id);
2584 }
2585
2586 if (misc.has_hpet) {
2587 acpi_add_table(table_offsets, tables_blob);
2588 build_hpet(tables_blob, tables->linker, x86ms->oem_id,
2589 x86ms->oem_table_id);
2590 }
2591 #ifdef CONFIG_TPM
2592 if (misc.tpm_version != TPM_VERSION_UNSPEC) {
2593 if (misc.tpm_version == TPM_VERSION_1_2) {
2594 acpi_add_table(table_offsets, tables_blob);
2595 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog,
2596 x86ms->oem_id, x86ms->oem_table_id);
2597 } else { /* TPM_VERSION_2_0 */
2598 acpi_add_table(table_offsets, tables_blob);
2599 build_tpm2(tables_blob, tables->linker, tables->tcpalog,
2600 x86ms->oem_id, x86ms->oem_table_id);
2601 }
2602 }
2603 #endif
2604 if (machine->numa_state->num_nodes) {
2605 acpi_add_table(table_offsets, tables_blob);
2606 build_srat(tables_blob, tables->linker, machine);
2607 if (machine->numa_state->have_numa_distance) {
2608 acpi_add_table(table_offsets, tables_blob);
2609 build_slit(tables_blob, tables->linker, machine, x86ms->oem_id,
2610 x86ms->oem_table_id);
2611 }
2612 if (machine->numa_state->hmat_enabled) {
2613 acpi_add_table(table_offsets, tables_blob);
2614 build_hmat(tables_blob, tables->linker, machine->numa_state,
2615 x86ms->oem_id, x86ms->oem_table_id);
2616 }
2617 }
2618 if (acpi_get_mcfg(&mcfg)) {
2619 acpi_add_table(table_offsets, tables_blob);
2620 build_mcfg(tables_blob, tables->linker, &mcfg, x86ms->oem_id,
2621 x86ms->oem_table_id);
2622 }
2623 if (object_dynamic_cast(OBJECT(iommu), TYPE_AMD_IOMMU_DEVICE)) {
2624 acpi_add_table(table_offsets, tables_blob);
2625 build_amd_iommu(tables_blob, tables->linker, x86ms->oem_id,
2626 x86ms->oem_table_id);
2627 } else if (object_dynamic_cast(OBJECT(iommu), TYPE_INTEL_IOMMU_DEVICE)) {
2628 acpi_add_table(table_offsets, tables_blob);
2629 build_dmar_q35(tables_blob, tables->linker, x86ms->oem_id,
2630 x86ms->oem_table_id);
2631 } else if (object_dynamic_cast(OBJECT(iommu), TYPE_VIRTIO_IOMMU_PCI)) {
2632 PCIDevice *pdev = PCI_DEVICE(iommu);
2633
2634 acpi_add_table(table_offsets, tables_blob);
2635 build_viot(machine, tables_blob, tables->linker, pci_get_bdf(pdev),
2636 x86ms->oem_id, x86ms->oem_table_id);
2637 }
2638 if (machine->nvdimms_state->is_enabled) {
2639 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker,
2640 machine->nvdimms_state, machine->ram_slots,
2641 x86ms->oem_id, x86ms->oem_table_id);
2642 }
2643 if (pcms->cxl_devices_state.is_enabled) {
2644 cxl_build_cedt(table_offsets, tables_blob, tables->linker,
2645 x86ms->oem_id, x86ms->oem_table_id, &pcms->cxl_devices_state);
2646 }
2647
2648 acpi_add_table(table_offsets, tables_blob);
2649 build_waet(tables_blob, tables->linker, x86ms->oem_id, x86ms->oem_table_id);
2650
2651 /* Add tables supplied by user (if any) */
2652 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
2653 unsigned len = acpi_table_len(u);
2654
2655 acpi_add_table(table_offsets, tables_blob);
2656 g_array_append_vals(tables_blob, u, len);
2657 }
2658
2659 /* RSDT is pointed to by RSDP */
2660 rsdt = tables_blob->len;
2661 build_rsdt(tables_blob, tables->linker, table_offsets,
2662 oem_id, oem_table_id);
2663
2664 /* RSDP is in FSEG memory, so allocate it separately */
2665 {
2666 AcpiRsdpData rsdp_data = {
2667 .revision = 0,
2668 .oem_id = x86ms->oem_id,
2669 .xsdt_tbl_offset = NULL,
2670 .rsdt_tbl_offset = &rsdt,
2671 };
2672 build_rsdp(tables->rsdp, tables->linker, &rsdp_data);
2673 if (!pcmc->rsdp_in_ram) {
2674 /* We used to allocate some extra space for RSDP revision 2 but
2675 * only used the RSDP revision 0 space. The extra bytes were
2676 * zeroed out and not used.
2677 * Here we continue wasting those extra 16 bytes to make sure we
2678 * don't break migration for machine types 2.2 and older due to
2679 * RSDP blob size mismatch.
2680 */
2681 build_append_int_noprefix(tables->rsdp, 0, 16);
2682 }
2683 }
2684
2685 /* We'll expose it all to Guest so we want to reduce
2686 * chance of size changes.
2687 *
2688 * We used to align the tables to 4k, but of course this would
2689 * too simple to be enough. 4k turned out to be too small an
2690 * alignment very soon, and in fact it is almost impossible to
2691 * keep the table size stable for all (max_cpus, max_memory_slots)
2692 * combinations. So the table size is always 64k for pc-i440fx-2.1
2693 * and we give an error if the table grows beyond that limit.
2694 *
2695 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
2696 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2697 * than 2.0 and we can always pad the smaller tables with zeros. We can
2698 * then use the exact size of the 2.0 tables.
2699 *
2700 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
2701 */
2702 if (pcmc->legacy_acpi_table_size) {
2703 /* Subtracting aml_len gives the size of fixed tables. Then add the
2704 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2705 */
2706 int legacy_aml_len =
2707 pcmc->legacy_acpi_table_size +
2708 ACPI_BUILD_LEGACY_CPU_AML_SIZE * x86ms->apic_id_limit;
2709 int legacy_table_size =
2710 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
2711 ACPI_BUILD_ALIGN_SIZE);
2712 if (tables_blob->len > legacy_table_size) {
2713 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
2714 warn_report("ACPI table size %u exceeds %d bytes,"
2715 " migration may not work",
2716 tables_blob->len, legacy_table_size);
2717 error_printf("Try removing CPUs, NUMA nodes, memory slots"
2718 " or PCI bridges.");
2719 }
2720 g_array_set_size(tables_blob, legacy_table_size);
2721 } else {
2722 /* Make sure we have a buffer in case we need to resize the tables. */
2723 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
2724 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
2725 warn_report("ACPI table size %u exceeds %d bytes,"
2726 " migration may not work",
2727 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2);
2728 error_printf("Try removing CPUs, NUMA nodes, memory slots"
2729 " or PCI bridges.");
2730 }
2731 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
2732 }
2733
2734 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE);
2735
2736 /* Cleanup memory that's no longer used. */
2737 g_array_free(table_offsets, true);
2738 g_free(slic_oem.id);
2739 g_free(slic_oem.table_id);
2740 }
2741
2742 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
2743 {
2744 uint32_t size = acpi_data_len(data);
2745
2746 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
2747 memory_region_ram_resize(mr, size, &error_abort);
2748
2749 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
2750 memory_region_set_dirty(mr, 0, size);
2751 }
2752
2753 static void acpi_build_update(void *build_opaque)
2754 {
2755 AcpiBuildState *build_state = build_opaque;
2756 AcpiBuildTables tables;
2757
2758 /* No state to update or already patched? Nothing to do. */
2759 if (!build_state || build_state->patched) {
2760 return;
2761 }
2762 build_state->patched = 1;
2763
2764 acpi_build_tables_init(&tables);
2765
2766 acpi_build(&tables, MACHINE(qdev_get_machine()));
2767
2768 acpi_ram_update(build_state->table_mr, tables.table_data);
2769
2770 if (build_state->rsdp) {
2771 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp));
2772 } else {
2773 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
2774 }
2775
2776 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
2777 acpi_build_tables_cleanup(&tables, true);
2778 }
2779
2780 static void acpi_build_reset(void *build_opaque)
2781 {
2782 AcpiBuildState *build_state = build_opaque;
2783 build_state->patched = 0;
2784 }
2785
2786 static const VMStateDescription vmstate_acpi_build = {
2787 .name = "acpi_build",
2788 .version_id = 1,
2789 .minimum_version_id = 1,
2790 .fields = (VMStateField[]) {
2791 VMSTATE_UINT8(patched, AcpiBuildState),
2792 VMSTATE_END_OF_LIST()
2793 },
2794 };
2795
2796 void acpi_setup(void)
2797 {
2798 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
2799 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2800 X86MachineState *x86ms = X86_MACHINE(pcms);
2801 AcpiBuildTables tables;
2802 AcpiBuildState *build_state;
2803 Object *vmgenid_dev;
2804 #ifdef CONFIG_TPM
2805 TPMIf *tpm;
2806 static FwCfgTPMConfig tpm_config;
2807 #endif
2808
2809 if (!x86ms->fw_cfg) {
2810 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
2811 return;
2812 }
2813
2814 if (!pcms->acpi_build_enabled) {
2815 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
2816 return;
2817 }
2818
2819 if (!x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) {
2820 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
2821 return;
2822 }
2823
2824 build_state = g_malloc0(sizeof *build_state);
2825
2826 acpi_build_tables_init(&tables);
2827 acpi_build(&tables, MACHINE(pcms));
2828
2829 /* Now expose it all to Guest */
2830 build_state->table_mr = acpi_add_rom_blob(acpi_build_update,
2831 build_state, tables.table_data,
2832 ACPI_BUILD_TABLE_FILE);
2833 assert(build_state->table_mr != NULL);
2834
2835 build_state->linker_mr =
2836 acpi_add_rom_blob(acpi_build_update, build_state,
2837 tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE);
2838
2839 #ifdef CONFIG_TPM
2840 fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
2841 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
2842
2843 tpm = tpm_find();
2844 if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) {
2845 tpm_config = (FwCfgTPMConfig) {
2846 .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE),
2847 .tpm_version = tpm_get_version(tpm),
2848 .tpmppi_version = TPM_PPI_VERSION_1_30
2849 };
2850 fw_cfg_add_file(x86ms->fw_cfg, "etc/tpm/config",
2851 &tpm_config, sizeof tpm_config);
2852 }
2853 #endif
2854
2855 vmgenid_dev = find_vmgenid_dev();
2856 if (vmgenid_dev) {
2857 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), x86ms->fw_cfg,
2858 tables.vmgenid);
2859 }
2860
2861 if (!pcmc->rsdp_in_ram) {
2862 /*
2863 * Keep for compatibility with old machine types.
2864 * Though RSDP is small, its contents isn't immutable, so
2865 * we'll update it along with the rest of tables on guest access.
2866 */
2867 uint32_t rsdp_size = acpi_data_len(tables.rsdp);
2868
2869 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
2870 fw_cfg_add_file_callback(x86ms->fw_cfg, ACPI_BUILD_RSDP_FILE,
2871 acpi_build_update, NULL, build_state,
2872 build_state->rsdp, rsdp_size, true);
2873 build_state->rsdp_mr = NULL;
2874 } else {
2875 build_state->rsdp = NULL;
2876 build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update,
2877 build_state, tables.rsdp,
2878 ACPI_BUILD_RSDP_FILE);
2879 }
2880
2881 qemu_register_reset(acpi_build_reset, build_state);
2882 acpi_build_reset(build_state);
2883 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
2884
2885 /* Cleanup tables but don't free the memory: we track it
2886 * in build_state.
2887 */
2888 acpi_build_tables_cleanup(&tables, false);
2889 }
QEmu