2 * ASPEED SoC 2600 family
4 * Copyright (c) 2016-2019, IBM Corporation.
6 * This code is licensed under the GPL version 2 or later. See
7 * the COPYING file in the top-level directory.
10 #include "qemu/osdep.h"
11 #include "qapi/error.h"
12 #include "hw/misc/unimp.h"
13 #include "hw/arm/aspeed_soc.h"
14 #include "hw/char/serial.h"
15 #include "qemu/module.h"
16 #include "qemu/error-report.h"
17 #include "hw/i2c/aspeed_i2c.h"
19 #include "sysemu/sysemu.h"
21 #define ASPEED_SOC_IOMEM_SIZE 0x00200000
23 static const hwaddr aspeed_soc_ast2600_memmap
[] = {
24 [ASPEED_DEV_SRAM
] = 0x10000000,
25 /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */
26 [ASPEED_DEV_IOMEM
] = 0x1E600000,
27 [ASPEED_DEV_PWM
] = 0x1E610000,
28 [ASPEED_DEV_FMC
] = 0x1E620000,
29 [ASPEED_DEV_SPI1
] = 0x1E630000,
30 [ASPEED_DEV_SPI2
] = 0x1E641000,
31 [ASPEED_DEV_EHCI1
] = 0x1E6A1000,
32 [ASPEED_DEV_EHCI2
] = 0x1E6A3000,
33 [ASPEED_DEV_MII1
] = 0x1E650000,
34 [ASPEED_DEV_MII2
] = 0x1E650008,
35 [ASPEED_DEV_MII3
] = 0x1E650010,
36 [ASPEED_DEV_MII4
] = 0x1E650018,
37 [ASPEED_DEV_ETH1
] = 0x1E660000,
38 [ASPEED_DEV_ETH3
] = 0x1E670000,
39 [ASPEED_DEV_ETH2
] = 0x1E680000,
40 [ASPEED_DEV_ETH4
] = 0x1E690000,
41 [ASPEED_DEV_VIC
] = 0x1E6C0000,
42 [ASPEED_DEV_HACE
] = 0x1E6D0000,
43 [ASPEED_DEV_SDMC
] = 0x1E6E0000,
44 [ASPEED_DEV_SCU
] = 0x1E6E2000,
45 [ASPEED_DEV_XDMA
] = 0x1E6E7000,
46 [ASPEED_DEV_ADC
] = 0x1E6E9000,
47 [ASPEED_DEV_VIDEO
] = 0x1E700000,
48 [ASPEED_DEV_SDHCI
] = 0x1E740000,
49 [ASPEED_DEV_EMMC
] = 0x1E750000,
50 [ASPEED_DEV_GPIO
] = 0x1E780000,
51 [ASPEED_DEV_GPIO_1_8V
] = 0x1E780800,
52 [ASPEED_DEV_RTC
] = 0x1E781000,
53 [ASPEED_DEV_TIMER1
] = 0x1E782000,
54 [ASPEED_DEV_WDT
] = 0x1E785000,
55 [ASPEED_DEV_LPC
] = 0x1E789000,
56 [ASPEED_DEV_IBT
] = 0x1E789140,
57 [ASPEED_DEV_I2C
] = 0x1E78A000,
58 [ASPEED_DEV_UART1
] = 0x1E783000,
59 [ASPEED_DEV_UART5
] = 0x1E784000,
60 [ASPEED_DEV_VUART
] = 0x1E787000,
61 [ASPEED_DEV_SDRAM
] = 0x80000000,
64 #define ASPEED_A7MPCORE_ADDR 0x40460000
66 #define AST2600_MAX_IRQ 197
68 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */
69 static const int aspeed_soc_ast2600_irqmap
[] = {
70 [ASPEED_DEV_UART1
] = 47,
71 [ASPEED_DEV_UART2
] = 48,
72 [ASPEED_DEV_UART3
] = 49,
73 [ASPEED_DEV_UART4
] = 50,
74 [ASPEED_DEV_UART5
] = 8,
75 [ASPEED_DEV_VUART
] = 8,
76 [ASPEED_DEV_FMC
] = 39,
77 [ASPEED_DEV_SDMC
] = 0,
78 [ASPEED_DEV_SCU
] = 12,
79 [ASPEED_DEV_ADC
] = 78,
80 [ASPEED_DEV_XDMA
] = 6,
81 [ASPEED_DEV_SDHCI
] = 43,
82 [ASPEED_DEV_EHCI1
] = 5,
83 [ASPEED_DEV_EHCI2
] = 9,
84 [ASPEED_DEV_EMMC
] = 15,
85 [ASPEED_DEV_GPIO
] = 40,
86 [ASPEED_DEV_GPIO_1_8V
] = 11,
87 [ASPEED_DEV_RTC
] = 13,
88 [ASPEED_DEV_TIMER1
] = 16,
89 [ASPEED_DEV_TIMER2
] = 17,
90 [ASPEED_DEV_TIMER3
] = 18,
91 [ASPEED_DEV_TIMER4
] = 19,
92 [ASPEED_DEV_TIMER5
] = 20,
93 [ASPEED_DEV_TIMER6
] = 21,
94 [ASPEED_DEV_TIMER7
] = 22,
95 [ASPEED_DEV_TIMER8
] = 23,
96 [ASPEED_DEV_WDT
] = 24,
97 [ASPEED_DEV_PWM
] = 44,
98 [ASPEED_DEV_LPC
] = 35,
99 [ASPEED_DEV_IBT
] = 143,
100 [ASPEED_DEV_I2C
] = 110, /* 110 -> 125 */
101 [ASPEED_DEV_ETH1
] = 2,
102 [ASPEED_DEV_ETH2
] = 3,
103 [ASPEED_DEV_HACE
] = 4,
104 [ASPEED_DEV_ETH3
] = 32,
105 [ASPEED_DEV_ETH4
] = 33,
106 [ASPEED_DEV_KCS
] = 138, /* 138 -> 142 */
109 static qemu_irq
aspeed_soc_get_irq(AspeedSoCState
*s
, int ctrl
)
111 AspeedSoCClass
*sc
= ASPEED_SOC_GET_CLASS(s
);
113 return qdev_get_gpio_in(DEVICE(&s
->a7mpcore
), sc
->irqmap
[ctrl
]);
116 static void aspeed_soc_ast2600_init(Object
*obj
)
118 AspeedSoCState
*s
= ASPEED_SOC(obj
);
119 AspeedSoCClass
*sc
= ASPEED_SOC_GET_CLASS(s
);
124 if (sscanf(sc
->name
, "%7s", socname
) != 1) {
125 g_assert_not_reached();
128 for (i
= 0; i
< sc
->num_cpus
; i
++) {
129 object_initialize_child(obj
, "cpu[*]", &s
->cpu
[i
], sc
->cpu_type
);
132 snprintf(typename
, sizeof(typename
), "aspeed.scu-%s", socname
);
133 object_initialize_child(obj
, "scu", &s
->scu
, typename
);
134 qdev_prop_set_uint32(DEVICE(&s
->scu
), "silicon-rev",
136 object_property_add_alias(obj
, "hw-strap1", OBJECT(&s
->scu
),
138 object_property_add_alias(obj
, "hw-strap2", OBJECT(&s
->scu
),
140 object_property_add_alias(obj
, "hw-prot-key", OBJECT(&s
->scu
),
143 object_initialize_child(obj
, "a7mpcore", &s
->a7mpcore
,
144 TYPE_A15MPCORE_PRIV
);
146 object_initialize_child(obj
, "rtc", &s
->rtc
, TYPE_ASPEED_RTC
);
148 snprintf(typename
, sizeof(typename
), "aspeed.timer-%s", socname
);
149 object_initialize_child(obj
, "timerctrl", &s
->timerctrl
, typename
);
151 snprintf(typename
, sizeof(typename
), "aspeed.adc-%s", socname
);
152 object_initialize_child(obj
, "adc", &s
->adc
, typename
);
154 snprintf(typename
, sizeof(typename
), "aspeed.i2c-%s", socname
);
155 object_initialize_child(obj
, "i2c", &s
->i2c
, typename
);
157 snprintf(typename
, sizeof(typename
), "aspeed.fmc-%s", socname
);
158 object_initialize_child(obj
, "fmc", &s
->fmc
, typename
);
159 object_property_add_alias(obj
, "num-cs", OBJECT(&s
->fmc
), "num-cs");
161 for (i
= 0; i
< sc
->spis_num
; i
++) {
162 snprintf(typename
, sizeof(typename
), "aspeed.spi%d-%s", i
+ 1, socname
);
163 object_initialize_child(obj
, "spi[*]", &s
->spi
[i
], typename
);
166 for (i
= 0; i
< sc
->ehcis_num
; i
++) {
167 object_initialize_child(obj
, "ehci[*]", &s
->ehci
[i
],
171 snprintf(typename
, sizeof(typename
), "aspeed.sdmc-%s", socname
);
172 object_initialize_child(obj
, "sdmc", &s
->sdmc
, typename
);
173 object_property_add_alias(obj
, "ram-size", OBJECT(&s
->sdmc
),
175 object_property_add_alias(obj
, "max-ram-size", OBJECT(&s
->sdmc
),
178 for (i
= 0; i
< sc
->wdts_num
; i
++) {
179 snprintf(typename
, sizeof(typename
), "aspeed.wdt-%s", socname
);
180 object_initialize_child(obj
, "wdt[*]", &s
->wdt
[i
], typename
);
183 for (i
= 0; i
< sc
->macs_num
; i
++) {
184 object_initialize_child(obj
, "ftgmac100[*]", &s
->ftgmac100
[i
],
187 object_initialize_child(obj
, "mii[*]", &s
->mii
[i
], TYPE_ASPEED_MII
);
190 snprintf(typename
, sizeof(typename
), TYPE_ASPEED_XDMA
"-%s", socname
);
191 object_initialize_child(obj
, "xdma", &s
->xdma
, typename
);
193 snprintf(typename
, sizeof(typename
), "aspeed.gpio-%s", socname
);
194 object_initialize_child(obj
, "gpio", &s
->gpio
, typename
);
196 snprintf(typename
, sizeof(typename
), "aspeed.gpio-%s-1_8v", socname
);
197 object_initialize_child(obj
, "gpio_1_8v", &s
->gpio_1_8v
, typename
);
199 object_initialize_child(obj
, "sd-controller", &s
->sdhci
,
202 object_property_set_int(OBJECT(&s
->sdhci
), "num-slots", 2, &error_abort
);
204 /* Init sd card slot class here so that they're under the correct parent */
205 for (i
= 0; i
< ASPEED_SDHCI_NUM_SLOTS
; ++i
) {
206 object_initialize_child(obj
, "sd-controller.sdhci[*]",
207 &s
->sdhci
.slots
[i
], TYPE_SYSBUS_SDHCI
);
210 object_initialize_child(obj
, "emmc-controller", &s
->emmc
,
213 object_property_set_int(OBJECT(&s
->emmc
), "num-slots", 1, &error_abort
);
215 object_initialize_child(obj
, "emmc-controller.sdhci", &s
->emmc
.slots
[0],
218 object_initialize_child(obj
, "lpc", &s
->lpc
, TYPE_ASPEED_LPC
);
220 snprintf(typename
, sizeof(typename
), "aspeed.hace-%s", socname
);
221 object_initialize_child(obj
, "hace", &s
->hace
, typename
);
225 * ASPEED ast2600 has 0xf as cluster ID
227 * https://developer.arm.com/documentation/ddi0388/e/the-system-control-coprocessors/summary-of-system-control-coprocessor-registers/multiprocessor-affinity-register
229 static uint64_t aspeed_calc_affinity(int cpu
)
231 return (0xf << ARM_AFF1_SHIFT
) | cpu
;
234 static void aspeed_soc_ast2600_realize(DeviceState
*dev
, Error
**errp
)
237 AspeedSoCState
*s
= ASPEED_SOC(dev
);
238 AspeedSoCClass
*sc
= ASPEED_SOC_GET_CLASS(s
);
243 create_unimplemented_device("aspeed_soc.io", sc
->memmap
[ASPEED_DEV_IOMEM
],
244 ASPEED_SOC_IOMEM_SIZE
);
246 /* Video engine stub */
247 create_unimplemented_device("aspeed.video", sc
->memmap
[ASPEED_DEV_VIDEO
],
251 for (i
= 0; i
< sc
->num_cpus
; i
++) {
252 if (sc
->num_cpus
> 1) {
253 object_property_set_int(OBJECT(&s
->cpu
[i
]), "reset-cbar",
254 ASPEED_A7MPCORE_ADDR
, &error_abort
);
256 object_property_set_int(OBJECT(&s
->cpu
[i
]), "mp-affinity",
257 aspeed_calc_affinity(i
), &error_abort
);
259 object_property_set_int(OBJECT(&s
->cpu
[i
]), "cntfrq", 1125000000,
262 if (!qdev_realize(DEVICE(&s
->cpu
[i
]), NULL
, errp
)) {
268 object_property_set_int(OBJECT(&s
->a7mpcore
), "num-cpu", sc
->num_cpus
,
270 object_property_set_int(OBJECT(&s
->a7mpcore
), "num-irq",
271 ROUND_UP(AST2600_MAX_IRQ
+ GIC_INTERNAL
, 32),
274 sysbus_realize(SYS_BUS_DEVICE(&s
->a7mpcore
), &error_abort
);
275 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->a7mpcore
), 0, ASPEED_A7MPCORE_ADDR
);
277 for (i
= 0; i
< sc
->num_cpus
; i
++) {
278 SysBusDevice
*sbd
= SYS_BUS_DEVICE(&s
->a7mpcore
);
279 DeviceState
*d
= DEVICE(qemu_get_cpu(i
));
281 irq
= qdev_get_gpio_in(d
, ARM_CPU_IRQ
);
282 sysbus_connect_irq(sbd
, i
, irq
);
283 irq
= qdev_get_gpio_in(d
, ARM_CPU_FIQ
);
284 sysbus_connect_irq(sbd
, i
+ sc
->num_cpus
, irq
);
285 irq
= qdev_get_gpio_in(d
, ARM_CPU_VIRQ
);
286 sysbus_connect_irq(sbd
, i
+ 2 * sc
->num_cpus
, irq
);
287 irq
= qdev_get_gpio_in(d
, ARM_CPU_VFIQ
);
288 sysbus_connect_irq(sbd
, i
+ 3 * sc
->num_cpus
, irq
);
292 memory_region_init_ram(&s
->sram
, OBJECT(dev
), "aspeed.sram",
293 sc
->sram_size
, &err
);
295 error_propagate(errp
, err
);
298 memory_region_add_subregion(get_system_memory(),
299 sc
->memmap
[ASPEED_DEV_SRAM
], &s
->sram
);
302 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->scu
), errp
)) {
305 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->scu
), 0, sc
->memmap
[ASPEED_DEV_SCU
]);
308 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->rtc
), errp
)) {
311 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->rtc
), 0, sc
->memmap
[ASPEED_DEV_RTC
]);
312 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->rtc
), 0,
313 aspeed_soc_get_irq(s
, ASPEED_DEV_RTC
));
316 object_property_set_link(OBJECT(&s
->timerctrl
), "scu", OBJECT(&s
->scu
),
318 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->timerctrl
), errp
)) {
321 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->timerctrl
), 0,
322 sc
->memmap
[ASPEED_DEV_TIMER1
]);
323 for (i
= 0; i
< ASPEED_TIMER_NR_TIMERS
; i
++) {
324 qemu_irq irq
= aspeed_soc_get_irq(s
, ASPEED_DEV_TIMER1
+ i
);
325 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->timerctrl
), i
, irq
);
329 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->adc
), errp
)) {
332 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->adc
), 0, sc
->memmap
[ASPEED_DEV_ADC
]);
333 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->adc
), 0,
334 aspeed_soc_get_irq(s
, ASPEED_DEV_ADC
));
336 /* UART - attach an 8250 to the IO space as our UART */
337 serial_mm_init(get_system_memory(), sc
->memmap
[s
->uart_default
], 2,
338 aspeed_soc_get_irq(s
, s
->uart_default
), 38400,
339 serial_hd(0), DEVICE_LITTLE_ENDIAN
);
342 object_property_set_link(OBJECT(&s
->i2c
), "dram", OBJECT(s
->dram_mr
),
344 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->i2c
), errp
)) {
347 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->i2c
), 0, sc
->memmap
[ASPEED_DEV_I2C
]);
348 for (i
= 0; i
< ASPEED_I2C_GET_CLASS(&s
->i2c
)->num_busses
; i
++) {
349 qemu_irq irq
= qdev_get_gpio_in(DEVICE(&s
->a7mpcore
),
350 sc
->irqmap
[ASPEED_DEV_I2C
] + i
);
351 /* The AST2600 I2C controller has one IRQ per bus. */
352 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->i2c
.busses
[i
]), 0, irq
);
355 /* FMC, The number of CS is set at the board level */
356 object_property_set_link(OBJECT(&s
->fmc
), "dram", OBJECT(s
->dram_mr
),
358 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->fmc
), errp
)) {
361 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->fmc
), 0, sc
->memmap
[ASPEED_DEV_FMC
]);
362 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->fmc
), 1,
363 ASPEED_SMC_GET_CLASS(&s
->fmc
)->flash_window_base
);
364 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->fmc
), 0,
365 aspeed_soc_get_irq(s
, ASPEED_DEV_FMC
));
368 for (i
= 0; i
< sc
->spis_num
; i
++) {
369 object_property_set_link(OBJECT(&s
->spi
[i
]), "dram",
370 OBJECT(s
->dram_mr
), &error_abort
);
371 object_property_set_int(OBJECT(&s
->spi
[i
]), "num-cs", 1, &error_abort
);
372 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->spi
[i
]), errp
)) {
375 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->spi
[i
]), 0,
376 sc
->memmap
[ASPEED_DEV_SPI1
+ i
]);
377 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->spi
[i
]), 1,
378 ASPEED_SMC_GET_CLASS(&s
->spi
[i
])->flash_window_base
);
382 for (i
= 0; i
< sc
->ehcis_num
; i
++) {
383 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->ehci
[i
]), errp
)) {
386 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->ehci
[i
]), 0,
387 sc
->memmap
[ASPEED_DEV_EHCI1
+ i
]);
388 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->ehci
[i
]), 0,
389 aspeed_soc_get_irq(s
, ASPEED_DEV_EHCI1
+ i
));
392 /* SDMC - SDRAM Memory Controller */
393 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->sdmc
), errp
)) {
396 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->sdmc
), 0, sc
->memmap
[ASPEED_DEV_SDMC
]);
399 for (i
= 0; i
< sc
->wdts_num
; i
++) {
400 AspeedWDTClass
*awc
= ASPEED_WDT_GET_CLASS(&s
->wdt
[i
]);
402 object_property_set_link(OBJECT(&s
->wdt
[i
]), "scu", OBJECT(&s
->scu
),
404 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->wdt
[i
]), errp
)) {
407 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->wdt
[i
]), 0,
408 sc
->memmap
[ASPEED_DEV_WDT
] + i
* awc
->offset
);
412 for (i
= 0; i
< sc
->macs_num
; i
++) {
413 object_property_set_bool(OBJECT(&s
->ftgmac100
[i
]), "aspeed", true,
415 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->ftgmac100
[i
]), errp
)) {
418 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->ftgmac100
[i
]), 0,
419 sc
->memmap
[ASPEED_DEV_ETH1
+ i
]);
420 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->ftgmac100
[i
]), 0,
421 aspeed_soc_get_irq(s
, ASPEED_DEV_ETH1
+ i
));
423 object_property_set_link(OBJECT(&s
->mii
[i
]), "nic",
424 OBJECT(&s
->ftgmac100
[i
]), &error_abort
);
425 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->mii
[i
]), errp
)) {
429 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->mii
[i
]), 0,
430 sc
->memmap
[ASPEED_DEV_MII1
+ i
]);
434 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->xdma
), errp
)) {
437 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->xdma
), 0,
438 sc
->memmap
[ASPEED_DEV_XDMA
]);
439 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->xdma
), 0,
440 aspeed_soc_get_irq(s
, ASPEED_DEV_XDMA
));
443 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->gpio
), errp
)) {
446 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->gpio
), 0, sc
->memmap
[ASPEED_DEV_GPIO
]);
447 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gpio
), 0,
448 aspeed_soc_get_irq(s
, ASPEED_DEV_GPIO
));
450 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->gpio_1_8v
), errp
)) {
453 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->gpio_1_8v
), 0,
454 sc
->memmap
[ASPEED_DEV_GPIO_1_8V
]);
455 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gpio_1_8v
), 0,
456 aspeed_soc_get_irq(s
, ASPEED_DEV_GPIO_1_8V
));
459 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->sdhci
), errp
)) {
462 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->sdhci
), 0,
463 sc
->memmap
[ASPEED_DEV_SDHCI
]);
464 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->sdhci
), 0,
465 aspeed_soc_get_irq(s
, ASPEED_DEV_SDHCI
));
468 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->emmc
), errp
)) {
471 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->emmc
), 0, sc
->memmap
[ASPEED_DEV_EMMC
]);
472 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->emmc
), 0,
473 aspeed_soc_get_irq(s
, ASPEED_DEV_EMMC
));
476 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->lpc
), errp
)) {
479 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->lpc
), 0, sc
->memmap
[ASPEED_DEV_LPC
]);
481 /* Connect the LPC IRQ to the GIC. It is otherwise unused. */
482 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->lpc
), 0,
483 aspeed_soc_get_irq(s
, ASPEED_DEV_LPC
));
486 * On the AST2600 LPC subdevice IRQs are connected straight to the GIC.
488 * LPC subdevice IRQ sources are offset from 1 because the LPC model caters
489 * to the AST2400 and AST2500. SoCs before the AST2600 have one LPC IRQ
490 * shared across the subdevices, and the shared IRQ output to the VIC is at
493 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->lpc
), 1 + aspeed_lpc_kcs_1
,
494 qdev_get_gpio_in(DEVICE(&s
->a7mpcore
),
495 sc
->irqmap
[ASPEED_DEV_KCS
] + aspeed_lpc_kcs_1
));
497 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->lpc
), 1 + aspeed_lpc_kcs_2
,
498 qdev_get_gpio_in(DEVICE(&s
->a7mpcore
),
499 sc
->irqmap
[ASPEED_DEV_KCS
] + aspeed_lpc_kcs_2
));
501 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->lpc
), 1 + aspeed_lpc_kcs_3
,
502 qdev_get_gpio_in(DEVICE(&s
->a7mpcore
),
503 sc
->irqmap
[ASPEED_DEV_KCS
] + aspeed_lpc_kcs_3
));
505 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->lpc
), 1 + aspeed_lpc_kcs_4
,
506 qdev_get_gpio_in(DEVICE(&s
->a7mpcore
),
507 sc
->irqmap
[ASPEED_DEV_KCS
] + aspeed_lpc_kcs_4
));
510 object_property_set_link(OBJECT(&s
->hace
), "dram", OBJECT(s
->dram_mr
),
512 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->hace
), errp
)) {
515 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->hace
), 0, sc
->memmap
[ASPEED_DEV_HACE
]);
516 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->hace
), 0,
517 aspeed_soc_get_irq(s
, ASPEED_DEV_HACE
));
520 static void aspeed_soc_ast2600_class_init(ObjectClass
*oc
, void *data
)
522 DeviceClass
*dc
= DEVICE_CLASS(oc
);
523 AspeedSoCClass
*sc
= ASPEED_SOC_CLASS(oc
);
525 dc
->realize
= aspeed_soc_ast2600_realize
;
527 sc
->name
= "ast2600-a3";
528 sc
->cpu_type
= ARM_CPU_TYPE_NAME("cortex-a7");
529 sc
->silicon_rev
= AST2600_A3_SILICON_REV
;
530 sc
->sram_size
= 0x16400;
535 sc
->irqmap
= aspeed_soc_ast2600_irqmap
;
536 sc
->memmap
= aspeed_soc_ast2600_memmap
;
540 static const TypeInfo aspeed_soc_ast2600_type_info
= {
541 .name
= "ast2600-a3",
542 .parent
= TYPE_ASPEED_SOC
,
543 .instance_size
= sizeof(AspeedSoCState
),
544 .instance_init
= aspeed_soc_ast2600_init
,
545 .class_init
= aspeed_soc_ast2600_class_init
,
546 .class_size
= sizeof(AspeedSoCClass
),
549 static void aspeed_soc_register_types(void)
551 type_register_static(&aspeed_soc_ast2600_type_info
);
554 type_init(aspeed_soc_register_types
)