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virtio-blk: live migrate s->rq with multiqueue
[qemu.git] / hw / block / m25p80.c
blob326b688e83281f461ab00e3a607412dfa645c8d1
1 /*
2 * ST M25P80 emulator. Emulate all SPI flash devices based on the m25p80 command
3 * set. Known devices table current as of Jun/2012 and taken from linux.
4 * See drivers/mtd/devices/m25p80.c.
5 *
6 * Copyright (C) 2011 Edgar E. Iglesias <edgar.iglesias@gmail.com>
7 * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
8 * Copyright (C) 2012 PetaLogix
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 or
13 * (at your option) a later version of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, see <http://www.gnu.org/licenses/>.
22 */
23
24 #include "qemu/osdep.h"
25 #include "hw/hw.h"
26 #include "sysemu/block-backend.h"
27 #include "sysemu/blockdev.h"
28 #include "hw/ssi/ssi.h"
29 #include "qemu/bitops.h"
30 #include "qemu/log.h"
31
32 #ifndef M25P80_ERR_DEBUG
33 #define M25P80_ERR_DEBUG 0
34 #endif
35
36 #define DB_PRINT_L(level, ...) do { \
37 if (M25P80_ERR_DEBUG > (level)) { \
38 fprintf(stderr, ": %s: ", __func__); \
39 fprintf(stderr, ## __VA_ARGS__); \
40 } \
41 } while (0);
42
43 /* Fields for FlashPartInfo->flags */
44
45 /* erase capabilities */
46 #define ER_4K 1
47 #define ER_32K 2
48 /* set to allow the page program command to write 0s back to 1. Useful for
49 * modelling EEPROM with SPI flash command set
50 */
51 #define EEPROM 0x100
52
53 /* 16 MiB max in 3 byte address mode */
54 #define MAX_3BYTES_SIZE 0x1000000
55
56 #define SPI_NOR_MAX_ID_LEN 6
57
58 typedef struct FlashPartInfo {
59 const char *part_name;
60 /*
61 * This array stores the ID bytes.
62 * The first three bytes are the JEDIC ID.
63 * JEDEC ID zero means "no ID" (mostly older chips).
64 */
65 uint8_t id[SPI_NOR_MAX_ID_LEN];
66 uint8_t id_len;
67 /* there is confusion between manufacturers as to what a sector is. In this
68 * device model, a "sector" is the size that is erased by the ERASE_SECTOR
69 * command (opcode 0xd8).
70 */
71 uint32_t sector_size;
72 uint32_t n_sectors;
73 uint32_t page_size;
74 uint16_t flags;
75 } FlashPartInfo;
76
77 /* adapted from linux */
78 /* Used when the "_ext_id" is two bytes at most */
79 #define INFO(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\
80 .part_name = _part_name,\
81 .id = {\
82 ((_jedec_id) >> 16) & 0xff,\
83 ((_jedec_id) >> 8) & 0xff,\
84 (_jedec_id) & 0xff,\
85 ((_ext_id) >> 8) & 0xff,\
86 (_ext_id) & 0xff,\
87 },\
88 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\
89 .sector_size = (_sector_size),\
90 .n_sectors = (_n_sectors),\
91 .page_size = 256,\
92 .flags = (_flags),
93
94 #define INFO6(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\
95 .part_name = _part_name,\
96 .id = {\
97 ((_jedec_id) >> 16) & 0xff,\
98 ((_jedec_id) >> 8) & 0xff,\
99 (_jedec_id) & 0xff,\
100 ((_ext_id) >> 16) & 0xff,\
101 ((_ext_id) >> 8) & 0xff,\
102 (_ext_id) & 0xff,\
103 },\
104 .id_len = 6,\
105 .sector_size = (_sector_size),\
106 .n_sectors = (_n_sectors),\
107 .page_size = 256,\
108 .flags = (_flags),\
109
110 #define JEDEC_NUMONYX 0x20
111 #define JEDEC_WINBOND 0xEF
112 #define JEDEC_SPANSION 0x01
113
114 /* Numonyx (Micron) Configuration register macros */
115 #define VCFG_DUMMY 0x1
116 #define VCFG_WRAP_SEQUENTIAL 0x2
117 #define NVCFG_XIP_MODE_DISABLED (7 << 9)
118 #define NVCFG_XIP_MODE_MASK (7 << 9)
119 #define VCFG_XIP_MODE_ENABLED (1 << 3)
120 #define CFG_DUMMY_CLK_LEN 4
121 #define NVCFG_DUMMY_CLK_POS 12
122 #define VCFG_DUMMY_CLK_POS 4
123 #define EVCFG_OUT_DRIVER_STRENGHT_DEF 7
124 #define EVCFG_VPP_ACCELERATOR (1 << 3)
125 #define EVCFG_RESET_HOLD_ENABLED (1 << 4)
126 #define NVCFG_DUAL_IO_MASK (1 << 2)
127 #define EVCFG_DUAL_IO_ENABLED (1 << 6)
128 #define NVCFG_QUAD_IO_MASK (1 << 3)
129 #define EVCFG_QUAD_IO_ENABLED (1 << 7)
130 #define NVCFG_4BYTE_ADDR_MASK (1 << 0)
131 #define NVCFG_LOWER_SEGMENT_MASK (1 << 1)
132
133 /* Numonyx (Micron) Flag Status Register macros */
134 #define FSR_4BYTE_ADDR_MODE_ENABLED 0x1
135 #define FSR_FLASH_READY (1 << 7)
136
137 /* Spansion configuration registers macros. */
138 #define SPANSION_QUAD_CFG_POS 0
139 #define SPANSION_QUAD_CFG_LEN 1
140 #define SPANSION_DUMMY_CLK_POS 0
141 #define SPANSION_DUMMY_CLK_LEN 4
142 #define SPANSION_ADDR_LEN_POS 7
143 #define SPANSION_ADDR_LEN_LEN 1
144
145 /*
146 * Spansion read mode command length in bytes,
147 * the mode is currently not supported.
148 */
149
150 #define SPANSION_CONTINUOUS_READ_MODE_CMD_LEN 1
151
152 static const FlashPartInfo known_devices[] = {
153 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
154 { INFO("at25fs010", 0x1f6601, 0, 32 << 10, 4, ER_4K) },
155 { INFO("at25fs040", 0x1f6604, 0, 64 << 10, 8, ER_4K) },
156
157 { INFO("at25df041a", 0x1f4401, 0, 64 << 10, 8, ER_4K) },
158 { INFO("at25df321a", 0x1f4701, 0, 64 << 10, 64, ER_4K) },
159 { INFO("at25df641", 0x1f4800, 0, 64 << 10, 128, ER_4K) },
160
161 { INFO("at26f004", 0x1f0400, 0, 64 << 10, 8, ER_4K) },
162 { INFO("at26df081a", 0x1f4501, 0, 64 << 10, 16, ER_4K) },
163 { INFO("at26df161a", 0x1f4601, 0, 64 << 10, 32, ER_4K) },
164 { INFO("at26df321", 0x1f4700, 0, 64 << 10, 64, ER_4K) },
165
166 { INFO("at45db081d", 0x1f2500, 0, 64 << 10, 16, ER_4K) },
167
168 /* Atmel EEPROMS - it is assumed, that don't care bit in command
169 * is set to 0. Block protection is not supported.
170 */
171 { INFO("at25128a-nonjedec", 0x0, 0, 1, 131072, EEPROM) },
172 { INFO("at25256a-nonjedec", 0x0, 0, 1, 262144, EEPROM) },
173
174 /* EON -- en25xxx */
175 { INFO("en25f32", 0x1c3116, 0, 64 << 10, 64, ER_4K) },
176 { INFO("en25p32", 0x1c2016, 0, 64 << 10, 64, 0) },
177 { INFO("en25q32b", 0x1c3016, 0, 64 << 10, 64, 0) },
178 { INFO("en25p64", 0x1c2017, 0, 64 << 10, 128, 0) },
179 { INFO("en25q64", 0x1c3017, 0, 64 << 10, 128, ER_4K) },
180
181 /* GigaDevice */
182 { INFO("gd25q32", 0xc84016, 0, 64 << 10, 64, ER_4K) },
183 { INFO("gd25q64", 0xc84017, 0, 64 << 10, 128, ER_4K) },
184
185 /* Intel/Numonyx -- xxxs33b */
186 { INFO("160s33b", 0x898911, 0, 64 << 10, 32, 0) },
187 { INFO("320s33b", 0x898912, 0, 64 << 10, 64, 0) },
188 { INFO("640s33b", 0x898913, 0, 64 << 10, 128, 0) },
189 { INFO("n25q064", 0x20ba17, 0, 64 << 10, 128, 0) },
190
191 /* Macronix */
192 { INFO("mx25l2005a", 0xc22012, 0, 64 << 10, 4, ER_4K) },
193 { INFO("mx25l4005a", 0xc22013, 0, 64 << 10, 8, ER_4K) },
194 { INFO("mx25l8005", 0xc22014, 0, 64 << 10, 16, 0) },
195 { INFO("mx25l1606e", 0xc22015, 0, 64 << 10, 32, ER_4K) },
196 { INFO("mx25l3205d", 0xc22016, 0, 64 << 10, 64, 0) },
197 { INFO("mx25l6405d", 0xc22017, 0, 64 << 10, 128, 0) },
198 { INFO("mx25l12805d", 0xc22018, 0, 64 << 10, 256, 0) },
199 { INFO("mx25l12855e", 0xc22618, 0, 64 << 10, 256, 0) },
200 { INFO("mx25l25635e", 0xc22019, 0, 64 << 10, 512, 0) },
201 { INFO("mx25l25655e", 0xc22619, 0, 64 << 10, 512, 0) },
202 { INFO("mx66u51235f", 0xc2253a, 0, 64 << 10, 1024, ER_4K | ER_32K) },
203 { INFO("mx66u1g45g", 0xc2253b, 0, 64 << 10, 2048, ER_4K | ER_32K) },
204
205 /* Micron */
206 { INFO("n25q032a11", 0x20bb16, 0, 64 << 10, 64, ER_4K) },
207 { INFO("n25q032a13", 0x20ba16, 0, 64 << 10, 64, ER_4K) },
208 { INFO("n25q064a11", 0x20bb17, 0, 64 << 10, 128, ER_4K) },
209 { INFO("n25q064a13", 0x20ba17, 0, 64 << 10, 128, ER_4K) },
210 { INFO("n25q128a11", 0x20bb18, 0, 64 << 10, 256, ER_4K) },
211 { INFO("n25q128a13", 0x20ba18, 0, 64 << 10, 256, ER_4K) },
212 { INFO("n25q256a11", 0x20bb19, 0, 64 << 10, 512, ER_4K) },
213 { INFO("n25q256a13", 0x20ba19, 0, 64 << 10, 512, ER_4K) },
214 { INFO("n25q128", 0x20ba18, 0, 64 << 10, 256, 0) },
215 { INFO("n25q256a", 0x20ba19, 0, 64 << 10, 512, ER_4K) },
216 { INFO("n25q512a", 0x20ba20, 0, 64 << 10, 1024, ER_4K) },
217 { INFO("mt25ql01g", 0x20ba21, 0, 64 << 10, 2048, ER_4K) },
218 { INFO("mt25qu01g", 0x20bb21, 0, 64 << 10, 2048, ER_4K) },
219
220 /* Spansion -- single (large) sector size only, at least
221 * for the chips listed here (without boot sectors).
222 */
223 { INFO("s25sl032p", 0x010215, 0x4d00, 64 << 10, 64, ER_4K) },
224 { INFO("s25sl064p", 0x010216, 0x4d00, 64 << 10, 128, ER_4K) },
225 { INFO("s25fl256s0", 0x010219, 0x4d00, 256 << 10, 128, 0) },
226 { INFO("s25fl256s1", 0x010219, 0x4d01, 64 << 10, 512, 0) },
227 { INFO6("s25fl512s", 0x010220, 0x4d0080, 256 << 10, 256, 0) },
228 { INFO6("s70fl01gs", 0x010221, 0x4d0080, 256 << 10, 512, 0) },
229 { INFO("s25sl12800", 0x012018, 0x0300, 256 << 10, 64, 0) },
230 { INFO("s25sl12801", 0x012018, 0x0301, 64 << 10, 256, 0) },
231 { INFO("s25fl129p0", 0x012018, 0x4d00, 256 << 10, 64, 0) },
232 { INFO("s25fl129p1", 0x012018, 0x4d01, 64 << 10, 256, 0) },
233 { INFO("s25sl004a", 0x010212, 0, 64 << 10, 8, 0) },
234 { INFO("s25sl008a", 0x010213, 0, 64 << 10, 16, 0) },
235 { INFO("s25sl016a", 0x010214, 0, 64 << 10, 32, 0) },
236 { INFO("s25sl032a", 0x010215, 0, 64 << 10, 64, 0) },
237 { INFO("s25sl064a", 0x010216, 0, 64 << 10, 128, 0) },
238 { INFO("s25fl016k", 0xef4015, 0, 64 << 10, 32, ER_4K | ER_32K) },
239 { INFO("s25fl064k", 0xef4017, 0, 64 << 10, 128, ER_4K | ER_32K) },
240
241 /* Spansion -- boot sectors support */
242 { INFO6("s25fs512s", 0x010220, 0x4d0081, 256 << 10, 256, 0) },
243 { INFO6("s70fs01gs", 0x010221, 0x4d0081, 256 << 10, 512, 0) },
244
245 /* SST -- large erase sizes are "overlays", "sectors" are 4<< 10 */
246 { INFO("sst25vf040b", 0xbf258d, 0, 64 << 10, 8, ER_4K) },
247 { INFO("sst25vf080b", 0xbf258e, 0, 64 << 10, 16, ER_4K) },
248 { INFO("sst25vf016b", 0xbf2541, 0, 64 << 10, 32, ER_4K) },
249 { INFO("sst25vf032b", 0xbf254a, 0, 64 << 10, 64, ER_4K) },
250 { INFO("sst25wf512", 0xbf2501, 0, 64 << 10, 1, ER_4K) },
251 { INFO("sst25wf010", 0xbf2502, 0, 64 << 10, 2, ER_4K) },
252 { INFO("sst25wf020", 0xbf2503, 0, 64 << 10, 4, ER_4K) },
253 { INFO("sst25wf040", 0xbf2504, 0, 64 << 10, 8, ER_4K) },
254 { INFO("sst25wf080", 0xbf2505, 0, 64 << 10, 16, ER_4K) },
255
256 /* ST Microelectronics -- newer production may have feature updates */
257 { INFO("m25p05", 0x202010, 0, 32 << 10, 2, 0) },
258 { INFO("m25p10", 0x202011, 0, 32 << 10, 4, 0) },
259 { INFO("m25p20", 0x202012, 0, 64 << 10, 4, 0) },
260 { INFO("m25p40", 0x202013, 0, 64 << 10, 8, 0) },
261 { INFO("m25p80", 0x202014, 0, 64 << 10, 16, 0) },
262 { INFO("m25p16", 0x202015, 0, 64 << 10, 32, 0) },
263 { INFO("m25p32", 0x202016, 0, 64 << 10, 64, 0) },
264 { INFO("m25p64", 0x202017, 0, 64 << 10, 128, 0) },
265 { INFO("m25p128", 0x202018, 0, 256 << 10, 64, 0) },
266 { INFO("n25q032", 0x20ba16, 0, 64 << 10, 64, 0) },
267
268 { INFO("m45pe10", 0x204011, 0, 64 << 10, 2, 0) },
269 { INFO("m45pe80", 0x204014, 0, 64 << 10, 16, 0) },
270 { INFO("m45pe16", 0x204015, 0, 64 << 10, 32, 0) },
271
272 { INFO("m25pe20", 0x208012, 0, 64 << 10, 4, 0) },
273 { INFO("m25pe80", 0x208014, 0, 64 << 10, 16, 0) },
274 { INFO("m25pe16", 0x208015, 0, 64 << 10, 32, ER_4K) },
275
276 { INFO("m25px32", 0x207116, 0, 64 << 10, 64, ER_4K) },
277 { INFO("m25px32-s0", 0x207316, 0, 64 << 10, 64, ER_4K) },
278 { INFO("m25px32-s1", 0x206316, 0, 64 << 10, 64, ER_4K) },
279 { INFO("m25px64", 0x207117, 0, 64 << 10, 128, 0) },
280
281 /* Winbond -- w25x "blocks" are 64k, "sectors" are 4KiB */
282 { INFO("w25x10", 0xef3011, 0, 64 << 10, 2, ER_4K) },
283 { INFO("w25x20", 0xef3012, 0, 64 << 10, 4, ER_4K) },
284 { INFO("w25x40", 0xef3013, 0, 64 << 10, 8, ER_4K) },
285 { INFO("w25x80", 0xef3014, 0, 64 << 10, 16, ER_4K) },
286 { INFO("w25x16", 0xef3015, 0, 64 << 10, 32, ER_4K) },
287 { INFO("w25x32", 0xef3016, 0, 64 << 10, 64, ER_4K) },
288 { INFO("w25q32", 0xef4016, 0, 64 << 10, 64, ER_4K) },
289 { INFO("w25q32dw", 0xef6016, 0, 64 << 10, 64, ER_4K) },
290 { INFO("w25x64", 0xef3017, 0, 64 << 10, 128, ER_4K) },
291 { INFO("w25q64", 0xef4017, 0, 64 << 10, 128, ER_4K) },
292 { INFO("w25q80", 0xef5014, 0, 64 << 10, 16, ER_4K) },
293 { INFO("w25q80bl", 0xef4014, 0, 64 << 10, 16, ER_4K) },
294 { INFO("w25q256", 0xef4019, 0, 64 << 10, 512, ER_4K) },
295 };
296
297 typedef enum {
298 NOP = 0,
299 WRSR = 0x1,
300 WRDI = 0x4,
301 RDSR = 0x5,
302 WREN = 0x6,
303 JEDEC_READ = 0x9f,
304 BULK_ERASE = 0xc7,
305 READ_FSR = 0x70,
306 RDCR = 0x15,
307
308 READ = 0x03,
309 READ4 = 0x13,
310 FAST_READ = 0x0b,
311 FAST_READ4 = 0x0c,
312 DOR = 0x3b,
313 DOR4 = 0x3c,
314 QOR = 0x6b,
315 QOR4 = 0x6c,
316 DIOR = 0xbb,
317 DIOR4 = 0xbc,
318 QIOR = 0xeb,
319 QIOR4 = 0xec,
320
321 PP = 0x02,
322 PP4 = 0x12,
323 PP4_4 = 0x3e,
324 DPP = 0xa2,
325 QPP = 0x32,
326
327 ERASE_4K = 0x20,
328 ERASE4_4K = 0x21,
329 ERASE_32K = 0x52,
330 ERASE4_32K = 0x5c,
331 ERASE_SECTOR = 0xd8,
332 ERASE4_SECTOR = 0xdc,
333
334 EN_4BYTE_ADDR = 0xB7,
335 EX_4BYTE_ADDR = 0xE9,
336
337 EXTEND_ADDR_READ = 0xC8,
338 EXTEND_ADDR_WRITE = 0xC5,
339
340 RESET_ENABLE = 0x66,
341 RESET_MEMORY = 0x99,
342
343 /*
344 * Micron: 0x35 - enable QPI
345 * Spansion: 0x35 - read control register
346 */
347 RDCR_EQIO = 0x35,
348 RSTQIO = 0xf5,
349
350 RNVCR = 0xB5,
351 WNVCR = 0xB1,
352
353 RVCR = 0x85,
354 WVCR = 0x81,
355
356 REVCR = 0x65,
357 WEVCR = 0x61,
358 } FlashCMD;
359
360 typedef enum {
361 STATE_IDLE,
362 STATE_PAGE_PROGRAM,
363 STATE_READ,
364 STATE_COLLECTING_DATA,
365 STATE_COLLECTING_VAR_LEN_DATA,
366 STATE_READING_DATA,
367 } CMDState;
368
369 typedef enum {
370 MAN_SPANSION,
371 MAN_MACRONIX,
372 MAN_NUMONYX,
373 MAN_WINBOND,
374 MAN_GENERIC,
375 } Manufacturer;
376
377 typedef struct Flash {
378 SSISlave parent_obj;
379
380 BlockBackend *blk;
381
382 uint8_t *storage;
383 uint32_t size;
384 int page_size;
385
386 uint8_t state;
387 uint8_t data[16];
388 uint32_t len;
389 uint32_t pos;
390 uint8_t needed_bytes;
391 uint8_t cmd_in_progress;
392 uint64_t cur_addr;
393 uint32_t nonvolatile_cfg;
394 /* Configuration register for Macronix */
395 uint32_t volatile_cfg;
396 uint32_t enh_volatile_cfg;
397 /* Spansion cfg registers. */
398 uint8_t spansion_cr1nv;
399 uint8_t spansion_cr2nv;
400 uint8_t spansion_cr3nv;
401 uint8_t spansion_cr4nv;
402 uint8_t spansion_cr1v;
403 uint8_t spansion_cr2v;
404 uint8_t spansion_cr3v;
405 uint8_t spansion_cr4v;
406 bool write_enable;
407 bool four_bytes_address_mode;
408 bool reset_enable;
409 bool quad_enable;
410 uint8_t ear;
411
412 int64_t dirty_page;
413
414 const FlashPartInfo *pi;
415
416 } Flash;
417
418 typedef struct M25P80Class {
419 SSISlaveClass parent_class;
420 FlashPartInfo *pi;
421 } M25P80Class;
422
423 #define TYPE_M25P80 "m25p80-generic"
424 #define M25P80(obj) \
425 OBJECT_CHECK(Flash, (obj), TYPE_M25P80)
426 #define M25P80_CLASS(klass) \
427 OBJECT_CLASS_CHECK(M25P80Class, (klass), TYPE_M25P80)
428 #define M25P80_GET_CLASS(obj) \
429 OBJECT_GET_CLASS(M25P80Class, (obj), TYPE_M25P80)
430
431 static inline Manufacturer get_man(Flash *s)
432 {
433 switch (s->pi->id[0]) {
434 case 0x20:
435 return MAN_NUMONYX;
436 case 0xEF:
437 return MAN_WINBOND;
438 case 0x01:
439 return MAN_SPANSION;
440 case 0xC2:
441 return MAN_MACRONIX;
442 default:
443 return MAN_GENERIC;
444 }
445 }
446
447 static void blk_sync_complete(void *opaque, int ret)
448 {
449 /* do nothing. Masters do not directly interact with the backing store,
450 * only the working copy so no mutexing required.
451 */
452 }
453
454 static void flash_sync_page(Flash *s, int page)
455 {
456 QEMUIOVector iov;
457
458 if (!s->blk || blk_is_read_only(s->blk)) {
459 return;
460 }
461
462 qemu_iovec_init(&iov, 1);
463 qemu_iovec_add(&iov, s->storage + page * s->pi->page_size,
464 s->pi->page_size);
465 blk_aio_pwritev(s->blk, page * s->pi->page_size, &iov, 0,
466 blk_sync_complete, NULL);
467 }
468
469 static inline void flash_sync_area(Flash *s, int64_t off, int64_t len)
470 {
471 QEMUIOVector iov;
472
473 if (!s->blk || blk_is_read_only(s->blk)) {
474 return;
475 }
476
477 assert(!(len % BDRV_SECTOR_SIZE));
478 qemu_iovec_init(&iov, 1);
479 qemu_iovec_add(&iov, s->storage + off, len);
480 blk_aio_pwritev(s->blk, off, &iov, 0, blk_sync_complete, NULL);
481 }
482
483 static void flash_erase(Flash *s, int offset, FlashCMD cmd)
484 {
485 uint32_t len;
486 uint8_t capa_to_assert = 0;
487
488 switch (cmd) {
489 case ERASE_4K:
490 case ERASE4_4K:
491 len = 4 << 10;
492 capa_to_assert = ER_4K;
493 break;
494 case ERASE_32K:
495 case ERASE4_32K:
496 len = 32 << 10;
497 capa_to_assert = ER_32K;
498 break;
499 case ERASE_SECTOR:
500 case ERASE4_SECTOR:
501 len = s->pi->sector_size;
502 break;
503 case BULK_ERASE:
504 len = s->size;
505 break;
506 default:
507 abort();
508 }
509
510 DB_PRINT_L(0, "offset = %#x, len = %d\n", offset, len);
511 if ((s->pi->flags & capa_to_assert) != capa_to_assert) {
512 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: %d erase size not supported by"
513 " device\n", len);
514 }
515
516 if (!s->write_enable) {
517 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: erase with write protect!\n");
518 return;
519 }
520 memset(s->storage + offset, 0xff, len);
521 flash_sync_area(s, offset, len);
522 }
523
524 static inline void flash_sync_dirty(Flash *s, int64_t newpage)
525 {
526 if (s->dirty_page >= 0 && s->dirty_page != newpage) {
527 flash_sync_page(s, s->dirty_page);
528 s->dirty_page = newpage;
529 }
530 }
531
532 static inline
533 void flash_write8(Flash *s, uint64_t addr, uint8_t data)
534 {
535 int64_t page = addr / s->pi->page_size;
536 uint8_t prev = s->storage[s->cur_addr];
537
538 if (!s->write_enable) {
539 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: write with write protect!\n");
540 }
541
542 if ((prev ^ data) & data) {
543 DB_PRINT_L(1, "programming zero to one! addr=%" PRIx64 " %" PRIx8
544 " -> %" PRIx8 "\n", addr, prev, data);
545 }
546
547 if (s->pi->flags & EEPROM) {
548 s->storage[s->cur_addr] = data;
549 } else {
550 s->storage[s->cur_addr] &= data;
551 }
552
553 flash_sync_dirty(s, page);
554 s->dirty_page = page;
555 }
556
557 static inline int get_addr_length(Flash *s)
558 {
559 /* check if eeprom is in use */
560 if (s->pi->flags == EEPROM) {
561 return 2;
562 }
563
564 switch (s->cmd_in_progress) {
565 case PP4:
566 case PP4_4:
567 case READ4:
568 case QIOR4:
569 case ERASE4_4K:
570 case ERASE4_32K:
571 case ERASE4_SECTOR:
572 case FAST_READ4:
573 case DOR4:
574 case QOR4:
575 case DIOR4:
576 return 4;
577 default:
578 return s->four_bytes_address_mode ? 4 : 3;
579 }
580 }
581
582 static void complete_collecting_data(Flash *s)
583 {
584 int i;
585
586 s->cur_addr = 0;
587
588 for (i = 0; i < get_addr_length(s); ++i) {
589 s->cur_addr <<= 8;
590 s->cur_addr |= s->data[i];
591 }
592
593 if (get_addr_length(s) == 3) {
594 s->cur_addr += s->ear * MAX_3BYTES_SIZE;
595 }
596
597 s->state = STATE_IDLE;
598
599 switch (s->cmd_in_progress) {
600 case DPP:
601 case QPP:
602 case PP:
603 case PP4:
604 case PP4_4:
605 s->state = STATE_PAGE_PROGRAM;
606 break;
607 case READ:
608 case READ4:
609 case FAST_READ:
610 case FAST_READ4:
611 case DOR:
612 case DOR4:
613 case QOR:
614 case QOR4:
615 case DIOR:
616 case DIOR4:
617 case QIOR:
618 case QIOR4:
619 s->state = STATE_READ;
620 break;
621 case ERASE_4K:
622 case ERASE4_4K:
623 case ERASE_32K:
624 case ERASE4_32K:
625 case ERASE_SECTOR:
626 case ERASE4_SECTOR:
627 flash_erase(s, s->cur_addr, s->cmd_in_progress);
628 break;
629 case WRSR:
630 switch (get_man(s)) {
631 case MAN_SPANSION:
632 s->quad_enable = !!(s->data[1] & 0x02);
633 break;
634 case MAN_MACRONIX:
635 s->quad_enable = extract32(s->data[0], 6, 1);
636 if (s->len > 1) {
637 s->four_bytes_address_mode = extract32(s->data[1], 5, 1);
638 }
639 break;
640 default:
641 break;
642 }
643 if (s->write_enable) {
644 s->write_enable = false;
645 }
646 break;
647 case EXTEND_ADDR_WRITE:
648 s->ear = s->data[0];
649 break;
650 case WNVCR:
651 s->nonvolatile_cfg = s->data[0] | (s->data[1] << 8);
652 break;
653 case WVCR:
654 s->volatile_cfg = s->data[0];
655 break;
656 case WEVCR:
657 s->enh_volatile_cfg = s->data[0];
658 break;
659 default:
660 break;
661 }
662 }
663
664 static void reset_memory(Flash *s)
665 {
666 s->cmd_in_progress = NOP;
667 s->cur_addr = 0;
668 s->ear = 0;
669 s->four_bytes_address_mode = false;
670 s->len = 0;
671 s->needed_bytes = 0;
672 s->pos = 0;
673 s->state = STATE_IDLE;
674 s->write_enable = false;
675 s->reset_enable = false;
676 s->quad_enable = false;
677
678 switch (get_man(s)) {
679 case MAN_NUMONYX:
680 s->volatile_cfg = 0;
681 s->volatile_cfg |= VCFG_DUMMY;
682 s->volatile_cfg |= VCFG_WRAP_SEQUENTIAL;
683 if ((s->nonvolatile_cfg & NVCFG_XIP_MODE_MASK)
684 != NVCFG_XIP_MODE_DISABLED) {
685 s->volatile_cfg |= VCFG_XIP_MODE_ENABLED;
686 }
687 s->volatile_cfg |= deposit32(s->volatile_cfg,
688 VCFG_DUMMY_CLK_POS,
689 CFG_DUMMY_CLK_LEN,
690 extract32(s->nonvolatile_cfg,
691 NVCFG_DUMMY_CLK_POS,
692 CFG_DUMMY_CLK_LEN)
693 );
694
695 s->enh_volatile_cfg = 0;
696 s->enh_volatile_cfg |= EVCFG_OUT_DRIVER_STRENGHT_DEF;
697 s->enh_volatile_cfg |= EVCFG_VPP_ACCELERATOR;
698 s->enh_volatile_cfg |= EVCFG_RESET_HOLD_ENABLED;
699 if (s->nonvolatile_cfg & NVCFG_DUAL_IO_MASK) {
700 s->enh_volatile_cfg |= EVCFG_DUAL_IO_ENABLED;
701 }
702 if (s->nonvolatile_cfg & NVCFG_QUAD_IO_MASK) {
703 s->enh_volatile_cfg |= EVCFG_QUAD_IO_ENABLED;
704 }
705 if (!(s->nonvolatile_cfg & NVCFG_4BYTE_ADDR_MASK)) {
706 s->four_bytes_address_mode = true;
707 }
708 if (!(s->nonvolatile_cfg & NVCFG_LOWER_SEGMENT_MASK)) {
709 s->ear = s->size / MAX_3BYTES_SIZE - 1;
710 }
711 break;
712 case MAN_MACRONIX:
713 s->volatile_cfg = 0x7;
714 break;
715 case MAN_SPANSION:
716 s->spansion_cr1v = s->spansion_cr1nv;
717 s->spansion_cr2v = s->spansion_cr2nv;
718 s->spansion_cr3v = s->spansion_cr3nv;
719 s->spansion_cr4v = s->spansion_cr4nv;
720 s->quad_enable = extract32(s->spansion_cr1v,
721 SPANSION_QUAD_CFG_POS,
722 SPANSION_QUAD_CFG_LEN
723 );
724 s->four_bytes_address_mode = extract32(s->spansion_cr2v,
725 SPANSION_ADDR_LEN_POS,
726 SPANSION_ADDR_LEN_LEN
727 );
728 break;
729 default:
730 break;
731 }
732
733 DB_PRINT_L(0, "Reset done.\n");
734 }
735
736 static void decode_fast_read_cmd(Flash *s)
737 {
738 s->needed_bytes = get_addr_length(s);
739 switch (get_man(s)) {
740 /* Dummy cycles - modeled with bytes writes instead of bits */
741 case MAN_WINBOND:
742 s->needed_bytes += 8;
743 break;
744 case MAN_NUMONYX:
745 s->needed_bytes += extract32(s->volatile_cfg, 4, 4);
746 break;
747 case MAN_MACRONIX:
748 if (extract32(s->volatile_cfg, 6, 2) == 1) {
749 s->needed_bytes += 6;
750 } else {
751 s->needed_bytes += 8;
752 }
753 break;
754 case MAN_SPANSION:
755 s->needed_bytes += extract32(s->spansion_cr2v,
756 SPANSION_DUMMY_CLK_POS,
757 SPANSION_DUMMY_CLK_LEN
758 );
759 break;
760 default:
761 break;
762 }
763 s->pos = 0;
764 s->len = 0;
765 s->state = STATE_COLLECTING_DATA;
766 }
767
768 static void decode_dio_read_cmd(Flash *s)
769 {
770 s->needed_bytes = get_addr_length(s);
771 /* Dummy cycles modeled with bytes writes instead of bits */
772 switch (get_man(s)) {
773 case MAN_WINBOND:
774 s->needed_bytes += 8;
775 break;
776 case MAN_SPANSION:
777 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN;
778 s->needed_bytes += extract32(s->spansion_cr2v,
779 SPANSION_DUMMY_CLK_POS,
780 SPANSION_DUMMY_CLK_LEN
781 );
782 break;
783 case MAN_NUMONYX:
784 s->needed_bytes += extract32(s->volatile_cfg, 4, 4);
785 break;
786 case MAN_MACRONIX:
787 switch (extract32(s->volatile_cfg, 6, 2)) {
788 case 1:
789 s->needed_bytes += 6;
790 break;
791 case 2:
792 s->needed_bytes += 8;
793 break;
794 default:
795 s->needed_bytes += 4;
796 break;
797 }
798 break;
799 default:
800 break;
801 }
802 s->pos = 0;
803 s->len = 0;
804 s->state = STATE_COLLECTING_DATA;
805 }
806
807 static void decode_qio_read_cmd(Flash *s)
808 {
809 s->needed_bytes = get_addr_length(s);
810 /* Dummy cycles modeled with bytes writes instead of bits */
811 switch (get_man(s)) {
812 case MAN_WINBOND:
813 s->needed_bytes += 8;
814 break;
815 case MAN_SPANSION:
816 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN;
817 s->needed_bytes += extract32(s->spansion_cr2v,
818 SPANSION_DUMMY_CLK_POS,
819 SPANSION_DUMMY_CLK_LEN
820 );
821 break;
822 case MAN_NUMONYX:
823 s->needed_bytes += extract32(s->volatile_cfg, 4, 4);
824 break;
825 case MAN_MACRONIX:
826 switch (extract32(s->volatile_cfg, 6, 2)) {
827 case 1:
828 s->needed_bytes += 4;
829 break;
830 case 2:
831 s->needed_bytes += 8;
832 break;
833 default:
834 s->needed_bytes += 6;
835 break;
836 }
837 break;
838 default:
839 break;
840 }
841 s->pos = 0;
842 s->len = 0;
843 s->state = STATE_COLLECTING_DATA;
844 }
845
846 static void decode_new_cmd(Flash *s, uint32_t value)
847 {
848 s->cmd_in_progress = value;
849 int i;
850 DB_PRINT_L(0, "decoded new command:%x\n", value);
851
852 if (value != RESET_MEMORY) {
853 s->reset_enable = false;
854 }
855
856 switch (value) {
857
858 case ERASE_4K:
859 case ERASE4_4K:
860 case ERASE_32K:
861 case ERASE4_32K:
862 case ERASE_SECTOR:
863 case ERASE4_SECTOR:
864 case READ:
865 case READ4:
866 case DPP:
867 case QPP:
868 case PP:
869 case PP4:
870 case PP4_4:
871 s->needed_bytes = get_addr_length(s);
872 s->pos = 0;
873 s->len = 0;
874 s->state = STATE_COLLECTING_DATA;
875 break;
876
877 case FAST_READ:
878 case FAST_READ4:
879 case DOR:
880 case DOR4:
881 case QOR:
882 case QOR4:
883 decode_fast_read_cmd(s);
884 break;
885
886 case DIOR:
887 case DIOR4:
888 decode_dio_read_cmd(s);
889 break;
890
891 case QIOR:
892 case QIOR4:
893 decode_qio_read_cmd(s);
894 break;
895
896 case WRSR:
897 if (s->write_enable) {
898 switch (get_man(s)) {
899 case MAN_SPANSION:
900 s->needed_bytes = 2;
901 s->state = STATE_COLLECTING_DATA;
902 break;
903 case MAN_MACRONIX:
904 s->needed_bytes = 2;
905 s->state = STATE_COLLECTING_VAR_LEN_DATA;
906 break;
907 default:
908 s->needed_bytes = 1;
909 s->state = STATE_COLLECTING_DATA;
910 }
911 s->pos = 0;
912 }
913 break;
914
915 case WRDI:
916 s->write_enable = false;
917 break;
918 case WREN:
919 s->write_enable = true;
920 break;
921
922 case RDSR:
923 s->data[0] = (!!s->write_enable) << 1;
924 if (get_man(s) == MAN_MACRONIX) {
925 s->data[0] |= (!!s->quad_enable) << 6;
926 }
927 s->pos = 0;
928 s->len = 1;
929 s->state = STATE_READING_DATA;
930 break;
931
932 case READ_FSR:
933 s->data[0] = FSR_FLASH_READY;
934 if (s->four_bytes_address_mode) {
935 s->data[0] |= FSR_4BYTE_ADDR_MODE_ENABLED;
936 }
937 s->pos = 0;
938 s->len = 1;
939 s->state = STATE_READING_DATA;
940 break;
941
942 case JEDEC_READ:
943 DB_PRINT_L(0, "populated jedec code\n");
944 for (i = 0; i < s->pi->id_len; i++) {
945 s->data[i] = s->pi->id[i];
946 }
947
948 s->len = s->pi->id_len;
949 s->pos = 0;
950 s->state = STATE_READING_DATA;
951 break;
952
953 case RDCR:
954 s->data[0] = s->volatile_cfg & 0xFF;
955 s->data[0] |= (!!s->four_bytes_address_mode) << 5;
956 s->pos = 0;
957 s->len = 1;
958 s->state = STATE_READING_DATA;
959 break;
960
961 case BULK_ERASE:
962 if (s->write_enable) {
963 DB_PRINT_L(0, "chip erase\n");
964 flash_erase(s, 0, BULK_ERASE);
965 } else {
966 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: chip erase with write "
967 "protect!\n");
968 }
969 break;
970 case NOP:
971 break;
972 case EN_4BYTE_ADDR:
973 s->four_bytes_address_mode = true;
974 break;
975 case EX_4BYTE_ADDR:
976 s->four_bytes_address_mode = false;
977 break;
978 case EXTEND_ADDR_READ:
979 s->data[0] = s->ear;
980 s->pos = 0;
981 s->len = 1;
982 s->state = STATE_READING_DATA;
983 break;
984 case EXTEND_ADDR_WRITE:
985 if (s->write_enable) {
986 s->needed_bytes = 1;
987 s->pos = 0;
988 s->len = 0;
989 s->state = STATE_COLLECTING_DATA;
990 }
991 break;
992 case RNVCR:
993 s->data[0] = s->nonvolatile_cfg & 0xFF;
994 s->data[1] = (s->nonvolatile_cfg >> 8) & 0xFF;
995 s->pos = 0;
996 s->len = 2;
997 s->state = STATE_READING_DATA;
998 break;
999 case WNVCR:
1000 if (s->write_enable && get_man(s) == MAN_NUMONYX) {
1001 s->needed_bytes = 2;
1002 s->pos = 0;
1003 s->len = 0;
1004 s->state = STATE_COLLECTING_DATA;
1005 }
1006 break;
1007 case RVCR:
1008 s->data[0] = s->volatile_cfg & 0xFF;
1009 s->pos = 0;
1010 s->len = 1;
1011 s->state = STATE_READING_DATA;
1012 break;
1013 case WVCR:
1014 if (s->write_enable) {
1015 s->needed_bytes = 1;
1016 s->pos = 0;
1017 s->len = 0;
1018 s->state = STATE_COLLECTING_DATA;
1019 }
1020 break;
1021 case REVCR:
1022 s->data[0] = s->enh_volatile_cfg & 0xFF;
1023 s->pos = 0;
1024 s->len = 1;
1025 s->state = STATE_READING_DATA;
1026 break;
1027 case WEVCR:
1028 if (s->write_enable) {
1029 s->needed_bytes = 1;
1030 s->pos = 0;
1031 s->len = 0;
1032 s->state = STATE_COLLECTING_DATA;
1033 }
1034 break;
1035 case RESET_ENABLE:
1036 s->reset_enable = true;
1037 break;
1038 case RESET_MEMORY:
1039 if (s->reset_enable) {
1040 reset_memory(s);
1041 }
1042 break;
1043 case RDCR_EQIO:
1044 switch (get_man(s)) {
1045 case MAN_SPANSION:
1046 s->data[0] = (!!s->quad_enable) << 1;
1047 s->pos = 0;
1048 s->len = 1;
1049 s->state = STATE_READING_DATA;
1050 break;
1051 case MAN_MACRONIX:
1052 s->quad_enable = true;
1053 break;
1054 default:
1055 break;
1056 }
1057 break;
1058 case RSTQIO:
1059 s->quad_enable = false;
1060 break;
1061 default:
1062 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value);
1063 break;
1064 }
1065 }
1066
1067 static int m25p80_cs(SSISlave *ss, bool select)
1068 {
1069 Flash *s = M25P80(ss);
1070
1071 if (select) {
1072 if (s->state == STATE_COLLECTING_VAR_LEN_DATA) {
1073 complete_collecting_data(s);
1074 }
1075 s->len = 0;
1076 s->pos = 0;
1077 s->state = STATE_IDLE;
1078 flash_sync_dirty(s, -1);
1079 }
1080
1081 DB_PRINT_L(0, "%sselect\n", select ? "de" : "");
1082
1083 return 0;
1084 }
1085
1086 static uint32_t m25p80_transfer8(SSISlave *ss, uint32_t tx)
1087 {
1088 Flash *s = M25P80(ss);
1089 uint32_t r = 0;
1090
1091 switch (s->state) {
1092
1093 case STATE_PAGE_PROGRAM:
1094 DB_PRINT_L(1, "page program cur_addr=%#" PRIx64 " data=%" PRIx8 "\n",
1095 s->cur_addr, (uint8_t)tx);
1096 flash_write8(s, s->cur_addr, (uint8_t)tx);
1097 s->cur_addr++;
1098 break;
1099
1100 case STATE_READ:
1101 r = s->storage[s->cur_addr];
1102 DB_PRINT_L(1, "READ 0x%" PRIx64 "=%" PRIx8 "\n", s->cur_addr,
1103 (uint8_t)r);
1104 s->cur_addr = (s->cur_addr + 1) % s->size;
1105 break;
1106
1107 case STATE_COLLECTING_DATA:
1108 case STATE_COLLECTING_VAR_LEN_DATA:
1109 s->data[s->len] = (uint8_t)tx;
1110 s->len++;
1111
1112 if (s->len == s->needed_bytes) {
1113 complete_collecting_data(s);
1114 }
1115 break;
1116
1117 case STATE_READING_DATA:
1118 r = s->data[s->pos];
1119 s->pos++;
1120 if (s->pos == s->len) {
1121 s->pos = 0;
1122 s->state = STATE_IDLE;
1123 }
1124 break;
1125
1126 default:
1127 case STATE_IDLE:
1128 decode_new_cmd(s, (uint8_t)tx);
1129 break;
1130 }
1131
1132 return r;
1133 }
1134
1135 static int m25p80_init(SSISlave *ss)
1136 {
1137 DriveInfo *dinfo;
1138 Flash *s = M25P80(ss);
1139 M25P80Class *mc = M25P80_GET_CLASS(s);
1140
1141 s->pi = mc->pi;
1142
1143 s->size = s->pi->sector_size * s->pi->n_sectors;
1144 s->dirty_page = -1;
1145
1146 /* FIXME use a qdev drive property instead of drive_get_next() */
1147 dinfo = drive_get_next(IF_MTD);
1148
1149 if (dinfo) {
1150 DB_PRINT_L(0, "Binding to IF_MTD drive\n");
1151 s->blk = blk_by_legacy_dinfo(dinfo);
1152 blk_attach_dev_nofail(s->blk, s);
1153
1154 s->storage = blk_blockalign(s->blk, s->size);
1155
1156 /* FIXME: Move to late init */
1157 if (blk_pread(s->blk, 0, s->storage, s->size) != s->size) {
1158 fprintf(stderr, "Failed to initialize SPI flash!\n");
1159 return 1;
1160 }
1161 } else {
1162 DB_PRINT_L(0, "No BDRV - binding to RAM\n");
1163 s->storage = blk_blockalign(NULL, s->size);
1164 memset(s->storage, 0xFF, s->size);
1165 }
1166
1167 return 0;
1168 }
1169
1170 static void m25p80_reset(DeviceState *d)
1171 {
1172 Flash *s = M25P80(d);
1173
1174 reset_memory(s);
1175 }
1176
1177 static void m25p80_pre_save(void *opaque)
1178 {
1179 flash_sync_dirty((Flash *)opaque, -1);
1180 }
1181
1182 static Property m25p80_properties[] = {
1183 /* This is default value for Micron flash */
1184 DEFINE_PROP_UINT32("nonvolatile-cfg", Flash, nonvolatile_cfg, 0x8FFF),
1185 DEFINE_PROP_UINT8("spansion-cr1nv", Flash, spansion_cr1nv, 0x0),
1186 DEFINE_PROP_UINT8("spansion-cr2nv", Flash, spansion_cr2nv, 0x8),
1187 DEFINE_PROP_UINT8("spansion-cr3nv", Flash, spansion_cr3nv, 0x2),
1188 DEFINE_PROP_UINT8("spansion-cr4nv", Flash, spansion_cr4nv, 0x10),
1189 DEFINE_PROP_END_OF_LIST(),
1190 };
1191
1192 static const VMStateDescription vmstate_m25p80 = {
1193 .name = "xilinx_spi",
1194 .version_id = 3,
1195 .minimum_version_id = 1,
1196 .pre_save = m25p80_pre_save,
1197 .fields = (VMStateField[]) {
1198 VMSTATE_UINT8(state, Flash),
1199 VMSTATE_UINT8_ARRAY(data, Flash, 16),
1200 VMSTATE_UINT32(len, Flash),
1201 VMSTATE_UINT32(pos, Flash),
1202 VMSTATE_UINT8(needed_bytes, Flash),
1203 VMSTATE_UINT8(cmd_in_progress, Flash),
1204 VMSTATE_UINT64(cur_addr, Flash),
1205 VMSTATE_BOOL(write_enable, Flash),
1206 VMSTATE_BOOL_V(reset_enable, Flash, 2),
1207 VMSTATE_UINT8_V(ear, Flash, 2),
1208 VMSTATE_BOOL_V(four_bytes_address_mode, Flash, 2),
1209 VMSTATE_UINT32_V(nonvolatile_cfg, Flash, 2),
1210 VMSTATE_UINT32_V(volatile_cfg, Flash, 2),
1211 VMSTATE_UINT32_V(enh_volatile_cfg, Flash, 2),
1212 VMSTATE_BOOL_V(quad_enable, Flash, 3),
1213 VMSTATE_UINT8_V(spansion_cr1nv, Flash, 3),
1214 VMSTATE_UINT8_V(spansion_cr2nv, Flash, 3),
1215 VMSTATE_UINT8_V(spansion_cr3nv, Flash, 3),
1216 VMSTATE_UINT8_V(spansion_cr4nv, Flash, 3),
1217 VMSTATE_END_OF_LIST()
1218 }
1219 };
1220
1221 static void m25p80_class_init(ObjectClass *klass, void *data)
1222 {
1223 DeviceClass *dc = DEVICE_CLASS(klass);
1224 SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
1225 M25P80Class *mc = M25P80_CLASS(klass);
1226
1227 k->init = m25p80_init;
1228 k->transfer = m25p80_transfer8;
1229 k->set_cs = m25p80_cs;
1230 k->cs_polarity = SSI_CS_LOW;
1231 dc->vmsd = &vmstate_m25p80;
1232 dc->props = m25p80_properties;
1233 dc->reset = m25p80_reset;
1234 mc->pi = data;
1235 }
1236
1237 static const TypeInfo m25p80_info = {
1238 .name = TYPE_M25P80,
1239 .parent = TYPE_SSI_SLAVE,
1240 .instance_size = sizeof(Flash),
1241 .class_size = sizeof(M25P80Class),
1242 .abstract = true,
1243 };
1244
1245 static void m25p80_register_types(void)
1246 {
1247 int i;
1248
1249 type_register_static(&m25p80_info);
1250 for (i = 0; i < ARRAY_SIZE(known_devices); ++i) {
1251 TypeInfo ti = {
1252 .name = known_devices[i].part_name,
1253 .parent = TYPE_M25P80,
1254 .class_init = m25p80_class_init,
1255 .class_data = (void *)&known_devices[i],
1256 };
1257 type_register(&ti);
1258 }
1259 }
1260
1261 type_init(m25p80_register_types)
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