hw/apic.c

   1 /*
   2  *  APIC support
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  18  */
  19 #include "hw.h"
  20 #include "apic.h"
  21 #include "ioapic.h"
  22 #include "qemu-timer.h"
  23 #include "host-utils.h"
  24 #include "sysbus.h"
  25 #include "trace.h"
  26 #include "pc.h"
  27
  28 /* APIC Local Vector Table */
  29 #define APIC_LVT_TIMER   0
  30 #define APIC_LVT_THERMAL 1
  31 #define APIC_LVT_PERFORM 2
  32 #define APIC_LVT_LINT0   3
  33 #define APIC_LVT_LINT1   4
  34 #define APIC_LVT_ERROR   5
  35 #define APIC_LVT_NB      6
  36
  37 /* APIC delivery modes */
  38 #define APIC_DM_FIXED   0
  39 #define APIC_DM_LOWPRI  1
  40 #define APIC_DM_SMI     2
  41 #define APIC_DM_NMI     4
  42 #define APIC_DM_INIT    5
  43 #define APIC_DM_SIPI    6
  44 #define APIC_DM_EXTINT  7
  45
  46 /* APIC destination mode */
  47 #define APIC_DESTMODE_FLAT      0xf
  48 #define APIC_DESTMODE_CLUSTER   1
  49
  50 #define APIC_TRIGGER_EDGE  0
  51 #define APIC_TRIGGER_LEVEL 1
  52
  53 #define APIC_LVT_TIMER_PERIODIC         (1<<17)
  54 #define APIC_LVT_MASKED                 (1<<16)
  55 #define APIC_LVT_LEVEL_TRIGGER          (1<<15)
  56 #define APIC_LVT_REMOTE_IRR             (1<<14)
  57 #define APIC_INPUT_POLARITY             (1<<13)
  58 #define APIC_SEND_PENDING               (1<<12)
  59
  60 #define ESR_ILLEGAL_ADDRESS (1 << 7)
  61
  62 #define APIC_SV_DIRECTED_IO             (1<<12)
  63 #define APIC_SV_ENABLE                  (1<<8)
  64
  65 #define MAX_APICS 255
  66 #define MAX_APIC_WORDS 8
  67
  68 /* Intel APIC constants: from include/asm/msidef.h */
  69 #define MSI_DATA_VECTOR_SHIFT           0
  70 #define MSI_DATA_VECTOR_MASK            0x000000ff
  71 #define MSI_DATA_DELIVERY_MODE_SHIFT    8
  72 #define MSI_DATA_TRIGGER_SHIFT          15
  73 #define MSI_DATA_LEVEL_SHIFT            14
  74 #define MSI_ADDR_DEST_MODE_SHIFT        2
  75 #define MSI_ADDR_DEST_ID_SHIFT          12
  76 #define MSI_ADDR_DEST_ID_MASK           0x00ffff0
  77
  78 #define MSI_ADDR_SIZE                   0x100000
  79
  80 typedef struct APICState APICState;
  81
  82 struct APICState {
  83     SysBusDevice busdev;
  84     MemoryRegion io_memory;
  85     void *cpu_env;
  86     uint32_t apicbase;
  87     uint8_t id;
  88     uint8_t arb_id;
  89     uint8_t tpr;
  90     uint32_t spurious_vec;
  91     uint8_t log_dest;
  92     uint8_t dest_mode;
  93     uint32_t isr[8];  /* in service register */
  94     uint32_t tmr[8];  /* trigger mode register */
  95     uint32_t irr[8]; /* interrupt request register */
  96     uint32_t lvt[APIC_LVT_NB];
  97     uint32_t esr; /* error register */
  98     uint32_t icr[2];
  99
 100     uint32_t divide_conf;
 101     int count_shift;
 102     uint32_t initial_count;
 103     int64_t initial_count_load_time, next_time;
 104     uint32_t idx;
 105     QEMUTimer *timer;
 106     int sipi_vector;
 107     int wait_for_sipi;
 108 };
 109
 110 static APICState *local_apics[MAX_APICS + 1];
 111 static int apic_irq_delivered;
 112
 113 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode);
 114 static void apic_update_irq(APICState *s);
 115 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
 116                                       uint8_t dest, uint8_t dest_mode);
 117
 118 /* Find first bit starting from msb */
 119 static int fls_bit(uint32_t value)
 120 {
 121     return 31 - clz32(value);
 122 }
 123
 124 /* Find first bit starting from lsb */
 125 static int ffs_bit(uint32_t value)
 126 {
 127     return ctz32(value);
 128 }
 129
 130 static inline void set_bit(uint32_t *tab, int index)
 131 {
 132     int i, mask;
 133     i = index >> 5;
 134     mask = 1 << (index & 0x1f);
 135     tab[i] |= mask;
 136 }
 137
 138 static inline void reset_bit(uint32_t *tab, int index)
 139 {
 140     int i, mask;
 141     i = index >> 5;
 142     mask = 1 << (index & 0x1f);
 143     tab[i] &= ~mask;
 144 }
 145
 146 static inline int get_bit(uint32_t *tab, int index)
 147 {
 148     int i, mask;
 149     i = index >> 5;
 150     mask = 1 << (index & 0x1f);
 151     return !!(tab[i] & mask);
 152 }
 153
 154 static void apic_local_deliver(APICState *s, int vector)
 155 {
 156     uint32_t lvt = s->lvt[vector];
 157     int trigger_mode;
 158
 159     trace_apic_local_deliver(vector, (lvt >> 8) & 7);
 160
 161     if (lvt & APIC_LVT_MASKED)
 162         return;
 163
 164     switch ((lvt >> 8) & 7) {
 165     case APIC_DM_SMI:
 166         cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SMI);
 167         break;
 168
 169     case APIC_DM_NMI:
 170         cpu_interrupt(s->cpu_env, CPU_INTERRUPT_NMI);
 171         break;
 172
 173     case APIC_DM_EXTINT:
 174         cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
 175         break;
 176
 177     case APIC_DM_FIXED:
 178         trigger_mode = APIC_TRIGGER_EDGE;
 179         if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) &&
 180             (lvt & APIC_LVT_LEVEL_TRIGGER))
 181             trigger_mode = APIC_TRIGGER_LEVEL;
 182         apic_set_irq(s, lvt & 0xff, trigger_mode);
 183     }
 184 }
 185
 186 void apic_deliver_pic_intr(DeviceState *d, int level)
 187 {
 188     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 189
 190     if (level) {
 191         apic_local_deliver(s, APIC_LVT_LINT0);
 192     } else {
 193         uint32_t lvt = s->lvt[APIC_LVT_LINT0];
 194
 195         switch ((lvt >> 8) & 7) {
 196         case APIC_DM_FIXED:
 197             if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
 198                 break;
 199             reset_bit(s->irr, lvt & 0xff);
 200             /* fall through */
 201         case APIC_DM_EXTINT:
 202             cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
 203             break;
 204         }
 205     }
 206 }
 207
 208 void apic_deliver_nmi(DeviceState *d)
 209 {
 210     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 211
 212     apic_local_deliver(s, APIC_LVT_LINT1);
 213 }
 214
 215 #define foreach_apic(apic, deliver_bitmask, code) \
 216 {\
 217     int __i, __j, __mask;\
 218     for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
 219         __mask = deliver_bitmask[__i];\
 220         if (__mask) {\
 221             for(__j = 0; __j < 32; __j++) {\
 222                 if (__mask & (1 << __j)) {\
 223                     apic = local_apics[__i * 32 + __j];\
 224                     if (apic) {\
 225                         code;\
 226                     }\
 227                 }\
 228             }\
 229         }\
 230     }\
 231 }
 232
 233 static void apic_bus_deliver(const uint32_t *deliver_bitmask,
 234                              uint8_t delivery_mode, uint8_t vector_num,
 235                              uint8_t trigger_mode)
 236 {
 237     APICState *apic_iter;
 238
 239     switch (delivery_mode) {
 240         case APIC_DM_LOWPRI:
 241             /* XXX: search for focus processor, arbitration */
 242             {
 243                 int i, d;
 244                 d = -1;
 245                 for(i = 0; i < MAX_APIC_WORDS; i++) {
 246                     if (deliver_bitmask[i]) {
 247                         d = i * 32 + ffs_bit(deliver_bitmask[i]);
 248                         break;
 249                     }
 250                 }
 251                 if (d >= 0) {
 252                     apic_iter = local_apics[d];
 253                     if (apic_iter) {
 254                         apic_set_irq(apic_iter, vector_num, trigger_mode);
 255                     }
 256                 }
 257             }
 258             return;
 259
 260         case APIC_DM_FIXED:
 261             break;
 262
 263         case APIC_DM_SMI:
 264             foreach_apic(apic_iter, deliver_bitmask,
 265                 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) );
 266             return;
 267
 268         case APIC_DM_NMI:
 269             foreach_apic(apic_iter, deliver_bitmask,
 270                 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) );
 271             return;
 272
 273         case APIC_DM_INIT:
 274             /* normal INIT IPI sent to processors */
 275             foreach_apic(apic_iter, deliver_bitmask,
 276                          cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_INIT) );
 277             return;
 278
 279         case APIC_DM_EXTINT:
 280             /* handled in I/O APIC code */
 281             break;
 282
 283         default:
 284             return;
 285     }
 286
 287     foreach_apic(apic_iter, deliver_bitmask,
 288                  apic_set_irq(apic_iter, vector_num, trigger_mode) );
 289 }
 290
 291 void apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode,
 292                       uint8_t vector_num, uint8_t trigger_mode)
 293 {
 294     uint32_t deliver_bitmask[MAX_APIC_WORDS];
 295
 296     trace_apic_deliver_irq(dest, dest_mode, delivery_mode, vector_num,
 297                            trigger_mode);
 298
 299     apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
 300     apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode);
 301 }
 302
 303 void cpu_set_apic_base(DeviceState *d, uint64_t val)
 304 {
 305     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 306
 307     trace_cpu_set_apic_base(val);
 308
 309     if (!s)
 310         return;
 311     s->apicbase = (val & 0xfffff000) |
 312         (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
 313     /* if disabled, cannot be enabled again */
 314     if (!(val & MSR_IA32_APICBASE_ENABLE)) {
 315         s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
 316         cpu_clear_apic_feature(s->cpu_env);
 317         s->spurious_vec &= ~APIC_SV_ENABLE;
 318     }
 319 }
 320
 321 uint64_t cpu_get_apic_base(DeviceState *d)
 322 {
 323     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 324
 325     trace_cpu_get_apic_base(s ? (uint64_t)s->apicbase: 0);
 326
 327     return s ? s->apicbase : 0;
 328 }
 329
 330 void cpu_set_apic_tpr(DeviceState *d, uint8_t val)
 331 {
 332     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 333
 334     if (!s)
 335         return;
 336     s->tpr = (val & 0x0f) << 4;
 337     apic_update_irq(s);
 338 }
 339
 340 uint8_t cpu_get_apic_tpr(DeviceState *d)
 341 {
 342     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 343
 344     return s ? s->tpr >> 4 : 0;
 345 }
 346
 347 /* return -1 if no bit is set */
 348 static int get_highest_priority_int(uint32_t *tab)
 349 {
 350     int i;
 351     for(i = 7; i >= 0; i--) {
 352         if (tab[i] != 0) {
 353             return i * 32 + fls_bit(tab[i]);
 354         }
 355     }
 356     return -1;
 357 }
 358
 359 static int apic_get_ppr(APICState *s)
 360 {
 361     int tpr, isrv, ppr;
 362
 363     tpr = (s->tpr >> 4);
 364     isrv = get_highest_priority_int(s->isr);
 365     if (isrv < 0)
 366         isrv = 0;
 367     isrv >>= 4;
 368     if (tpr >= isrv)
 369         ppr = s->tpr;
 370     else
 371         ppr = isrv << 4;
 372     return ppr;
 373 }
 374
 375 static int apic_get_arb_pri(APICState *s)
 376 {
 377     /* XXX: arbitration */
 378     return 0;
 379 }
 380
 381
 382 /*
 383  * <0 - low prio interrupt,
 384  * 0  - no interrupt,
 385  * >0 - interrupt number
 386  */
 387 static int apic_irq_pending(APICState *s)
 388 {
 389     int irrv, ppr;
 390     irrv = get_highest_priority_int(s->irr);
 391     if (irrv < 0) {
 392         return 0;
 393     }
 394     ppr = apic_get_ppr(s);
 395     if (ppr && (irrv & 0xf0) <= (ppr & 0xf0)) {
 396         return -1;
 397     }
 398
 399     return irrv;
 400 }
 401
 402 /* signal the CPU if an irq is pending */
 403 static void apic_update_irq(APICState *s)
 404 {
 405     if (!(s->spurious_vec & APIC_SV_ENABLE)) {
 406         return;
 407     }
 408     if (apic_irq_pending(s) > 0) {
 409         cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
 410     } else if (apic_accept_pic_intr(&s->busdev.qdev) &&
 411                pic_get_output(isa_pic)) {
 412         apic_deliver_pic_intr(&s->busdev.qdev, 1);
 413     }
 414 }
 415
 416 void apic_reset_irq_delivered(void)
 417 {
 418     trace_apic_reset_irq_delivered(apic_irq_delivered);
 419
 420     apic_irq_delivered = 0;
 421 }
 422
 423 int apic_get_irq_delivered(void)
 424 {
 425     trace_apic_get_irq_delivered(apic_irq_delivered);
 426
 427     return apic_irq_delivered;
 428 }
 429
 430 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode)
 431 {
 432     apic_irq_delivered += !get_bit(s->irr, vector_num);
 433
 434     trace_apic_set_irq(apic_irq_delivered);
 435
 436     set_bit(s->irr, vector_num);
 437     if (trigger_mode)
 438         set_bit(s->tmr, vector_num);
 439     else
 440         reset_bit(s->tmr, vector_num);
 441     apic_update_irq(s);
 442 }
 443
 444 static void apic_eoi(APICState *s)
 445 {
 446     int isrv;
 447     isrv = get_highest_priority_int(s->isr);
 448     if (isrv < 0)
 449         return;
 450     reset_bit(s->isr, isrv);
 451     if (!(s->spurious_vec & APIC_SV_DIRECTED_IO) && get_bit(s->tmr, isrv)) {
 452         ioapic_eoi_broadcast(isrv);
 453     }
 454     apic_update_irq(s);
 455 }
 456
 457 static int apic_find_dest(uint8_t dest)
 458 {
 459     APICState *apic = local_apics[dest];
 460     int i;
 461
 462     if (apic && apic->id == dest)
 463         return dest;  /* shortcut in case apic->id == apic->idx */
 464
 465     for (i = 0; i < MAX_APICS; i++) {
 466         apic = local_apics[i];
 467         if (apic && apic->id == dest)
 468             return i;
 469         if (!apic)
 470             break;
 471     }
 472
 473     return -1;
 474 }
 475
 476 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
 477                                       uint8_t dest, uint8_t dest_mode)
 478 {
 479     APICState *apic_iter;
 480     int i;
 481
 482     if (dest_mode == 0) {
 483         if (dest == 0xff) {
 484             memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t));
 485         } else {
 486             int idx = apic_find_dest(dest);
 487             memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 488             if (idx >= 0)
 489                 set_bit(deliver_bitmask, idx);
 490         }
 491     } else {
 492         /* XXX: cluster mode */
 493         memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 494         for(i = 0; i < MAX_APICS; i++) {
 495             apic_iter = local_apics[i];
 496             if (apic_iter) {
 497                 if (apic_iter->dest_mode == 0xf) {
 498                     if (dest & apic_iter->log_dest)
 499                         set_bit(deliver_bitmask, i);
 500                 } else if (apic_iter->dest_mode == 0x0) {
 501                     if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) &&
 502                         (dest & apic_iter->log_dest & 0x0f)) {
 503                         set_bit(deliver_bitmask, i);
 504                     }
 505                 }
 506             } else {
 507                 break;
 508             }
 509         }
 510     }
 511 }
 512
 513 void apic_init_reset(DeviceState *d)
 514 {
 515     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 516     int i;
 517
 518     if (!s)
 519         return;
 520
 521     s->tpr = 0;
 522     s->spurious_vec = 0xff;
 523     s->log_dest = 0;
 524     s->dest_mode = 0xf;
 525     memset(s->isr, 0, sizeof(s->isr));
 526     memset(s->tmr, 0, sizeof(s->tmr));
 527     memset(s->irr, 0, sizeof(s->irr));
 528     for(i = 0; i < APIC_LVT_NB; i++)
 529         s->lvt[i] = 1 << 16; /* mask LVT */
 530     s->esr = 0;
 531     memset(s->icr, 0, sizeof(s->icr));
 532     s->divide_conf = 0;
 533     s->count_shift = 0;
 534     s->initial_count = 0;
 535     s->initial_count_load_time = 0;
 536     s->next_time = 0;
 537     s->wait_for_sipi = 1;
 538
 539     qemu_del_timer(s->timer);
 540 }
 541
 542 static void apic_startup(APICState *s, int vector_num)
 543 {
 544     s->sipi_vector = vector_num;
 545     cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI);
 546 }
 547
 548 void apic_sipi(DeviceState *d)
 549 {
 550     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 551
 552     cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI);
 553
 554     if (!s->wait_for_sipi)
 555         return;
 556     cpu_x86_load_seg_cache_sipi(s->cpu_env, s->sipi_vector);
 557     s->wait_for_sipi = 0;
 558 }
 559
 560 static void apic_deliver(DeviceState *d, uint8_t dest, uint8_t dest_mode,
 561                          uint8_t delivery_mode, uint8_t vector_num,
 562                          uint8_t trigger_mode)
 563 {
 564     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 565     uint32_t deliver_bitmask[MAX_APIC_WORDS];
 566     int dest_shorthand = (s->icr[0] >> 18) & 3;
 567     APICState *apic_iter;
 568
 569     switch (dest_shorthand) {
 570     case 0:
 571         apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
 572         break;
 573     case 1:
 574         memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask));
 575         set_bit(deliver_bitmask, s->idx);
 576         break;
 577     case 2:
 578         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 579         break;
 580     case 3:
 581         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 582         reset_bit(deliver_bitmask, s->idx);
 583         break;
 584     }
 585
 586     switch (delivery_mode) {
 587         case APIC_DM_INIT:
 588             {
 589                 int trig_mode = (s->icr[0] >> 15) & 1;
 590                 int level = (s->icr[0] >> 14) & 1;
 591                 if (level == 0 && trig_mode == 1) {
 592                     foreach_apic(apic_iter, deliver_bitmask,
 593                                  apic_iter->arb_id = apic_iter->id );
 594                     return;
 595                 }
 596             }
 597             break;
 598
 599         case APIC_DM_SIPI:
 600             foreach_apic(apic_iter, deliver_bitmask,
 601                          apic_startup(apic_iter, vector_num) );
 602             return;
 603     }
 604
 605     apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode);
 606 }
 607
 608 int apic_get_interrupt(DeviceState *d)
 609 {
 610     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 611     int intno;
 612
 613     /* if the APIC is installed or enabled, we let the 8259 handle the
 614        IRQs */
 615     if (!s)
 616         return -1;
 617     if (!(s->spurious_vec & APIC_SV_ENABLE))
 618         return -1;
 619
 620     intno = apic_irq_pending(s);
 621
 622     if (intno == 0) {
 623         return -1;
 624     } else if (intno < 0) {
 625         return s->spurious_vec & 0xff;
 626     }
 627     reset_bit(s->irr, intno);
 628     set_bit(s->isr, intno);
 629     apic_update_irq(s);
 630     return intno;
 631 }
 632
 633 int apic_accept_pic_intr(DeviceState *d)
 634 {
 635     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 636     uint32_t lvt0;
 637
 638     if (!s)
 639         return -1;
 640
 641     lvt0 = s->lvt[APIC_LVT_LINT0];
 642
 643     if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 ||
 644         (lvt0 & APIC_LVT_MASKED) == 0)
 645         return 1;
 646
 647     return 0;
 648 }
 649
 650 static uint32_t apic_get_current_count(APICState *s)
 651 {
 652     int64_t d;
 653     uint32_t val;
 654     d = (qemu_get_clock_ns(vm_clock) - s->initial_count_load_time) >>
 655         s->count_shift;
 656     if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 657         /* periodic */
 658         val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
 659     } else {
 660         if (d >= s->initial_count)
 661             val = 0;
 662         else
 663             val = s->initial_count - d;
 664     }
 665     return val;
 666 }
 667
 668 static void apic_timer_update(APICState *s, int64_t current_time)
 669 {
 670     int64_t next_time, d;
 671
 672     if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
 673         d = (current_time - s->initial_count_load_time) >>
 674             s->count_shift;
 675         if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 676             if (!s->initial_count)
 677                 goto no_timer;
 678             d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1);
 679         } else {
 680             if (d >= s->initial_count)
 681                 goto no_timer;
 682             d = (uint64_t)s->initial_count + 1;
 683         }
 684         next_time = s->initial_count_load_time + (d << s->count_shift);
 685         qemu_mod_timer(s->timer, next_time);
 686         s->next_time = next_time;
 687     } else {
 688     no_timer:
 689         qemu_del_timer(s->timer);
 690     }
 691 }
 692
 693 static void apic_timer(void *opaque)
 694 {
 695     APICState *s = opaque;
 696
 697     apic_local_deliver(s, APIC_LVT_TIMER);
 698     apic_timer_update(s, s->next_time);
 699 }
 700
 701 static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
 702 {
 703     return 0;
 704 }
 705
 706 static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
 707 {
 708     return 0;
 709 }
 710
 711 static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
 712 {
 713 }
 714
 715 static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
 716 {
 717 }
 718
 719 static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
 720 {
 721     DeviceState *d;
 722     APICState *s;
 723     uint32_t val;
 724     int index;
 725
 726     d = cpu_get_current_apic();
 727     if (!d) {
 728         return 0;
 729     }
 730     s = DO_UPCAST(APICState, busdev.qdev, d);
 731
 732     index = (addr >> 4) & 0xff;
 733     switch(index) {
 734     case 0x02: /* id */
 735         val = s->id << 24;
 736         break;
 737     case 0x03: /* version */
 738         val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
 739         break;
 740     case 0x08:
 741         val = s->tpr;
 742         break;
 743     case 0x09:
 744         val = apic_get_arb_pri(s);
 745         break;
 746     case 0x0a:
 747         /* ppr */
 748         val = apic_get_ppr(s);
 749         break;
 750     case 0x0b:
 751         val = 0;
 752         break;
 753     case 0x0d:
 754         val = s->log_dest << 24;
 755         break;
 756     case 0x0e:
 757         val = s->dest_mode << 28;
 758         break;
 759     case 0x0f:
 760         val = s->spurious_vec;
 761         break;
 762     case 0x10 ... 0x17:
 763         val = s->isr[index & 7];
 764         break;
 765     case 0x18 ... 0x1f:
 766         val = s->tmr[index & 7];
 767         break;
 768     case 0x20 ... 0x27:
 769         val = s->irr[index & 7];
 770         break;
 771     case 0x28:
 772         val = s->esr;
 773         break;
 774     case 0x30:
 775     case 0x31:
 776         val = s->icr[index & 1];
 777         break;
 778     case 0x32 ... 0x37:
 779         val = s->lvt[index - 0x32];
 780         break;
 781     case 0x38:
 782         val = s->initial_count;
 783         break;
 784     case 0x39:
 785         val = apic_get_current_count(s);
 786         break;
 787     case 0x3e:
 788         val = s->divide_conf;
 789         break;
 790     default:
 791         s->esr |= ESR_ILLEGAL_ADDRESS;
 792         val = 0;
 793         break;
 794     }
 795     trace_apic_mem_readl(addr, val);
 796     return val;
 797 }
 798
 799 static void apic_send_msi(target_phys_addr_t addr, uint32_t data)
 800 {
 801     uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
 802     uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
 803     uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1;
 804     uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1;
 805     uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7;
 806     /* XXX: Ignore redirection hint. */
 807     apic_deliver_irq(dest, dest_mode, delivery, vector, trigger_mode);
 808 }
 809
 810 static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 811 {
 812     DeviceState *d;
 813     APICState *s;
 814     int index = (addr >> 4) & 0xff;
 815     if (addr > 0xfff || !index) {
 816         /* MSI and MMIO APIC are at the same memory location,
 817          * but actually not on the global bus: MSI is on PCI bus
 818          * APIC is connected directly to the CPU.
 819          * Mapping them on the global bus happens to work because
 820          * MSI registers are reserved in APIC MMIO and vice versa. */
 821         apic_send_msi(addr, val);
 822         return;
 823     }
 824
 825     d = cpu_get_current_apic();
 826     if (!d) {
 827         return;
 828     }
 829     s = DO_UPCAST(APICState, busdev.qdev, d);
 830
 831     trace_apic_mem_writel(addr, val);
 832
 833     switch(index) {
 834     case 0x02:
 835         s->id = (val >> 24);
 836         break;
 837     case 0x03:
 838         break;
 839     case 0x08:
 840         s->tpr = val;
 841         apic_update_irq(s);
 842         break;
 843     case 0x09:
 844     case 0x0a:
 845         break;
 846     case 0x0b: /* EOI */
 847         apic_eoi(s);
 848         break;
 849     case 0x0d:
 850         s->log_dest = val >> 24;
 851         break;
 852     case 0x0e:
 853         s->dest_mode = val >> 28;
 854         break;
 855     case 0x0f:
 856         s->spurious_vec = val & 0x1ff;
 857         apic_update_irq(s);
 858         break;
 859     case 0x10 ... 0x17:
 860     case 0x18 ... 0x1f:
 861     case 0x20 ... 0x27:
 862     case 0x28:
 863         break;
 864     case 0x30:
 865         s->icr[0] = val;
 866         apic_deliver(d, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
 867                      (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
 868                      (s->icr[0] >> 15) & 1);
 869         break;
 870     case 0x31:
 871         s->icr[1] = val;
 872         break;
 873     case 0x32 ... 0x37:
 874         {
 875             int n = index - 0x32;
 876             s->lvt[n] = val;
 877             if (n == APIC_LVT_TIMER)
 878                 apic_timer_update(s, qemu_get_clock_ns(vm_clock));
 879         }
 880         break;
 881     case 0x38:
 882         s->initial_count = val;
 883         s->initial_count_load_time = qemu_get_clock_ns(vm_clock);
 884         apic_timer_update(s, s->initial_count_load_time);
 885         break;
 886     case 0x39:
 887         break;
 888     case 0x3e:
 889         {
 890             int v;
 891             s->divide_conf = val & 0xb;
 892             v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
 893             s->count_shift = (v + 1) & 7;
 894         }
 895         break;
 896     default:
 897         s->esr |= ESR_ILLEGAL_ADDRESS;
 898         break;
 899     }
 900 }
 901
 902 /* This function is only used for old state version 1 and 2 */
 903 static int apic_load_old(QEMUFile *f, void *opaque, int version_id)
 904 {
 905     APICState *s = opaque;
 906     int i;
 907
 908     if (version_id > 2)
 909         return -EINVAL;
 910
 911     /* XXX: what if the base changes? (registered memory regions) */
 912     qemu_get_be32s(f, &s->apicbase);
 913     qemu_get_8s(f, &s->id);
 914     qemu_get_8s(f, &s->arb_id);
 915     qemu_get_8s(f, &s->tpr);
 916     qemu_get_be32s(f, &s->spurious_vec);
 917     qemu_get_8s(f, &s->log_dest);
 918     qemu_get_8s(f, &s->dest_mode);
 919     for (i = 0; i < 8; i++) {
 920         qemu_get_be32s(f, &s->isr[i]);
 921         qemu_get_be32s(f, &s->tmr[i]);
 922         qemu_get_be32s(f, &s->irr[i]);
 923     }
 924     for (i = 0; i < APIC_LVT_NB; i++) {
 925         qemu_get_be32s(f, &s->lvt[i]);
 926     }
 927     qemu_get_be32s(f, &s->esr);
 928     qemu_get_be32s(f, &s->icr[0]);
 929     qemu_get_be32s(f, &s->icr[1]);
 930     qemu_get_be32s(f, &s->divide_conf);
 931     s->count_shift=qemu_get_be32(f);
 932     qemu_get_be32s(f, &s->initial_count);
 933     s->initial_count_load_time=qemu_get_be64(f);
 934     s->next_time=qemu_get_be64(f);
 935
 936     if (version_id >= 2)
 937         qemu_get_timer(f, s->timer);
 938     return 0;
 939 }
 940
 941 static const VMStateDescription vmstate_apic = {
 942     .name = "apic",
 943     .version_id = 3,
 944     .minimum_version_id = 3,
 945     .minimum_version_id_old = 1,
 946     .load_state_old = apic_load_old,
 947     .fields      = (VMStateField []) {
 948         VMSTATE_UINT32(apicbase, APICState),
 949         VMSTATE_UINT8(id, APICState),
 950         VMSTATE_UINT8(arb_id, APICState),
 951         VMSTATE_UINT8(tpr, APICState),
 952         VMSTATE_UINT32(spurious_vec, APICState),
 953         VMSTATE_UINT8(log_dest, APICState),
 954         VMSTATE_UINT8(dest_mode, APICState),
 955         VMSTATE_UINT32_ARRAY(isr, APICState, 8),
 956         VMSTATE_UINT32_ARRAY(tmr, APICState, 8),
 957         VMSTATE_UINT32_ARRAY(irr, APICState, 8),
 958         VMSTATE_UINT32_ARRAY(lvt, APICState, APIC_LVT_NB),
 959         VMSTATE_UINT32(esr, APICState),
 960         VMSTATE_UINT32_ARRAY(icr, APICState, 2),
 961         VMSTATE_UINT32(divide_conf, APICState),
 962         VMSTATE_INT32(count_shift, APICState),
 963         VMSTATE_UINT32(initial_count, APICState),
 964         VMSTATE_INT64(initial_count_load_time, APICState),
 965         VMSTATE_INT64(next_time, APICState),
 966         VMSTATE_TIMER(timer, APICState),
 967         VMSTATE_END_OF_LIST()
 968     }
 969 };
 970
 971 static void apic_reset(DeviceState *d)
 972 {
 973     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 974     int bsp;
 975
 976     bsp = cpu_is_bsp(s->cpu_env);
 977     s->apicbase = 0xfee00000 |
 978         (bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE;
 979
 980     apic_init_reset(d);
 981
 982     if (bsp) {
 983         /*
 984          * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
 985          * time typically by BIOS, so PIC interrupt can be delivered to the
 986          * processor when local APIC is enabled.
 987          */
 988         s->lvt[APIC_LVT_LINT0] = 0x700;
 989     }
 990 }
 991
 992 static const MemoryRegionOps apic_io_ops = {
 993     .old_mmio = {
 994         .read = { apic_mem_readb, apic_mem_readw, apic_mem_readl, },
 995         .write = { apic_mem_writeb, apic_mem_writew, apic_mem_writel, },
 996     },
 997     .endianness = DEVICE_NATIVE_ENDIAN,
 998 };
 999
1000 static int apic_init1(SysBusDevice *dev)
1001 {
1002     APICState *s = FROM_SYSBUS(APICState, dev);
1003     static int last_apic_idx;
1004
1005     if (last_apic_idx >= MAX_APICS) {
1006         return -1;
1007     }
1008     memory_region_init_io(&s->io_memory, &apic_io_ops, s, "apic",
1009                           MSI_ADDR_SIZE);
1010     sysbus_init_mmio(dev, &s->io_memory);
1011
1012     s->timer = qemu_new_timer_ns(vm_clock, apic_timer, s);
1013     s->idx = last_apic_idx++;
1014     local_apics[s->idx] = s;
1015     return 0;
1016 }
1017
1018 static SysBusDeviceInfo apic_info = {
1019     .init = apic_init1,
1020     .qdev.name = "apic",
1021     .qdev.size = sizeof(APICState),
1022     .qdev.vmsd = &vmstate_apic,
1023     .qdev.reset = apic_reset,
1024     .qdev.no_user = 1,
1025     .qdev.props = (Property[]) {
1026         DEFINE_PROP_UINT8("id", APICState, id, -1),
1027         DEFINE_PROP_PTR("cpu_env", APICState, cpu_env),
1028         DEFINE_PROP_END_OF_LIST(),
1029     }
1030 };
1031
1032 static void apic_register_devices(void)
1033 {
1034     sysbus_register_withprop(&apic_info);
1035 }
1036
1037 device_init(apic_register_devices)