From 6407f37373093fd56cde9e20b0b5a878b67521ca Mon Sep 17 00:00:00 2001 From: Isaku Yamahata Date: Sun, 3 May 2009 19:03:00 +0000 Subject: [PATCH] use PCI_HEADER_TYPE. use symbolic value instead of 0x0e and related value. Signed-off-by: Isaku Yamahata --- hw/ac97.c | 2 +- hw/acpi.c | 2 +- hw/apb_pci.c | 2 +- hw/cirrus_vga.c | 3 +-- hw/grackle_pci.c | 4 ++-- hw/ide.c | 6 +++--- hw/macio.c | 2 +- hw/ne2000.c | 2 +- hw/openpic.c | 2 +- hw/pci.c | 3 ++- hw/pci.h | 4 ++++ hw/pcnet.c | 2 +- hw/piix_pci.c | 9 ++++++--- hw/prep_pci.c | 2 +- hw/rtl8139.c | 2 +- hw/sun4u.c | 2 +- hw/unin_pci.c | 8 ++++---- hw/usb-uhci.c | 4 ++-- hw/vga.c | 2 +- hw/virtio.c | 2 +- hw/vmware_vga.c | 4 +--- 21 files changed, 37 insertions(+), 32 deletions(-) diff --git a/hw/ac97.c b/hw/ac97.c index ade2719118..d9ef141744 100644 --- a/hw/ac97.c +++ b/hw/ac97.c @@ -1348,7 +1348,7 @@ int ac97_init (PCIBus *bus, AudioState *audio) c[0x08] = 0x01; /* rid revision ro */ c[0x09] = 0x00; /* pi programming interface ro */ pci_config_set_class(c, PCI_CLASS_MULTIMEDIA_AUDIO); /* ro */ - c[0x0e] = 0x00; /* headtyp header type ro */ + c[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; /* headtyp header type ro */ c[0x10] = 0x01; /* nabmar native audio mixer base address rw */ diff --git a/hw/acpi.c b/hw/acpi.c index 7e91405c38..dbaf18ade8 100644 --- a/hw/acpi.c +++ b/hw/acpi.c @@ -515,7 +515,7 @@ i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, pci_conf[0x08] = 0x03; // revision number pci_conf[0x09] = 0x00; pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER); - pci_conf[0x0e] = 0x00; // header_type + pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type pci_conf[0x3d] = 0x01; // interrupt pin 1 pci_conf[0x40] = 0x01; /* PM io base read only bit */ diff --git a/hw/apb_pci.c b/hw/apb_pci.c index a179acde7e..36ecb5584b 100644 --- a/hw/apb_pci.c +++ b/hw/apb_pci.c @@ -262,7 +262,7 @@ PCIBus *pci_apb_init(target_phys_addr_t special_base, d->config[0x09] = 0x00; // programming i/f pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST); d->config[0x0D] = 0x10; // latency_timer - d->config[0x0E] = 0x00; // header_type + d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type /* APB secondary busses */ *bus2 = pci_bridge_init(s->bus, 8, PCI_VENDOR_ID_SUN, diff --git a/hw/cirrus_vga.c b/hw/cirrus_vga.c index 52ac346d12..e4728a494a 100644 --- a/hw/cirrus_vga.c +++ b/hw/cirrus_vga.c @@ -187,7 +187,6 @@ // PCI 0x08, 0x00ff0000 #define PCI_CLASS_SUB_VGA 0x00 // PCI 0x0c, 0x00ff0000 (0x0c:cacheline,0x0d:latency,0x0e:headertype,0x0f:Built-in self test) -#define PCI_CLASS_HEADERTYPE_00h 0x00 // 0x10-0x3f (headertype 00h) // PCI 0x10,0x14,0x18,0x1c,0x20,0x24: base address mapping registers // 0x10: MEMBASE, 0x14: IOBASE(hard-coded in XFree86 3.x) @@ -3319,7 +3318,7 @@ void pci_cirrus_vga_init(PCIBus *bus, int vga_ram_size) pci_config_set_device_id(pci_conf, device_id); pci_conf[0x04] = PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS; pci_config_set_class(pci_conf, PCI_CLASS_DISPLAY_VGA); - pci_conf[0x0e] = PCI_CLASS_HEADERTYPE_00h; + pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; /* setup VGA */ s = &d->cirrus_vga; diff --git a/hw/grackle_pci.c b/hw/grackle_pci.c index 5161727917..61606b22f2 100644 --- a/hw/grackle_pci.c +++ b/hw/grackle_pci.c @@ -149,7 +149,7 @@ PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic) d->config[0x08] = 0x00; // revision d->config[0x09] = 0x01; pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST); - d->config[0x0e] = 0x00; // header_type + d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type #if 0 /* PCI2PCI bridge same values as PearPC - check this */ @@ -157,7 +157,7 @@ PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic) pci_config_set_device_id(d->config, PCI_DEVICE_ID_DEC_21154); d->config[0x08] = 0x02; // revision pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI); - d->config[0x0e] = 0x01; // header_type + d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_BRIDGE; // header_type d->config[0x18] = 0x0; // primary_bus d->config[0x19] = 0x1; // secondary_bus diff --git a/hw/ide.c b/hw/ide.c index e61cefb696..b2a1288f5d 100644 --- a/hw/ide.c +++ b/hw/ide.c @@ -3301,7 +3301,7 @@ void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table, pci_conf[0x09] = 0x8f; pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE); - pci_conf[0x0e] = 0x00; // header_type + pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type pci_conf[0x51] = 0x04; // enable IDE0 if (secondary_ide_enabled) { @@ -3371,7 +3371,7 @@ void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn, pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_1); pci_conf[0x09] = 0x80; // legacy ATA mode pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE); - pci_conf[0x0e] = 0x00; // header_type + pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type qemu_register_reset(piix3_reset, d); piix3_reset(d); @@ -3411,7 +3411,7 @@ void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn, pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB); pci_conf[0x09] = 0x80; // legacy ATA mode pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE); - pci_conf[0x0e] = 0x00; // header_type + pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type qemu_register_reset(piix3_reset, d); piix3_reset(d); diff --git a/hw/macio.c b/hw/macio.c index 1333aa3828..28dbaa720f 100644 --- a/hw/macio.c +++ b/hw/macio.c @@ -110,7 +110,7 @@ void macio_init (PCIBus *bus, int device_id, int is_oldworld, int pic_mem_index, pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE); pci_config_set_device_id(d->config, device_id); pci_config_set_class(d->config, PCI_CLASS_OTHERS << 8); - d->config[0x0e] = 0x00; // header_type + d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type d->config[0x3d] = 0x01; // interrupt on pin 1 diff --git a/hw/ne2000.c b/hw/ne2000.c index 613ac411f8..d778cb4ca8 100644 --- a/hw/ne2000.c +++ b/hw/ne2000.c @@ -817,7 +817,7 @@ PCIDevice *pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn) pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_REALTEK); pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_REALTEK_8029); pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET); - pci_conf[0x0e] = 0x00; // header_type + pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type pci_conf[0x3d] = 1; // interrupt pin 0 pci_register_io_region(&d->dev, 0, 0x100, diff --git a/hw/openpic.c b/hw/openpic.c index 733284ae8d..53747c4580 100644 --- a/hw/openpic.c +++ b/hw/openpic.c @@ -1208,7 +1208,7 @@ qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus, pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_IBM); pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_IBM_OPENPIC2); pci_config_set_class(pci_conf, PCI_CLASS_SYSTEM_OTHER); // FIXME? - pci_conf[0x0e] = 0x00; // header_type + pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type pci_conf[0x3d] = 0x00; // no interrupt pin /* Register I/O spaces */ diff --git a/hw/pci.c b/hw/pci.c index bfd394229f..827889466e 100644 --- a/hw/pci.c +++ b/hw/pci.c @@ -883,7 +883,8 @@ PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did, s->dev.config[0x09] = 0x00; // programming i/f pci_config_set_class(s->dev.config, PCI_CLASS_BRIDGE_PCI); s->dev.config[0x0D] = 0x10; // latency_timer - s->dev.config[0x0E] = 0x81; // header_type + s->dev.config[PCI_HEADER_TYPE] = + PCI_HEADER_TYPE_MULTI_FUNCTION | PCI_HEADER_TYPE_BRIDGE; // header_type s->dev.config[0x1E] = 0xa0; // secondary status s->bus = pci_register_secondary_bus(&s->dev, map_irq); diff --git a/hw/pci.h b/hw/pci.h index 4a30d9840c..ff858a1b3b 100644 --- a/hw/pci.h +++ b/hw/pci.h @@ -102,6 +102,10 @@ typedef struct PCIIORegion { #define PCI_REVISION_ID 0x08 /* 8 bits */ #define PCI_CLASS_DEVICE 0x0a /* Device class */ #define PCI_HEADER_TYPE 0x0e /* 8 bits */ +#define PCI_HEADER_TYPE_NORMAL 0 +#define PCI_HEADER_TYPE_BRIDGE 1 +#define PCI_HEADER_TYPE_CARDBUS 2 +#define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c /* 16 bits */ #define PCI_SUBSYSTEM_ID 0x2e /* 16 bits */ #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ diff --git a/hw/pcnet.c b/hw/pcnet.c index 654340b68f..13f14bef0a 100644 --- a/hw/pcnet.c +++ b/hw/pcnet.c @@ -2037,7 +2037,7 @@ PCIDevice *pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn) pci_conf[0x08] = 0x10; pci_conf[0x09] = 0x00; pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET); - pci_conf[0x0e] = 0x00; // header_type + pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type *(uint32_t *)&pci_conf[0x10] = cpu_to_le32(0x00000001); *(uint32_t *)&pci_conf[0x14] = cpu_to_le32(0x00000000); diff --git a/hw/piix_pci.c b/hw/piix_pci.c index b8607aaa7f..2b19cc6887 100644 --- a/hw/piix_pci.c +++ b/hw/piix_pci.c @@ -196,7 +196,7 @@ PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic) pci_config_set_device_id(d->config, PCI_DEVICE_ID_INTEL_82441); d->config[0x08] = 0x02; // revision pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST); - d->config[0x0e] = 0x00; // header_type + d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type d->config[0x72] = 0x02; /* SMRAM */ @@ -334,7 +334,8 @@ int piix3_init(PCIBus *bus, int devfn) pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_0); // 82371SB PIIX3 PCI-to-ISA bridge (Step A1) pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA); - pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic + pci_conf[PCI_HEADER_TYPE] = + PCI_HEADER_TYPE_NORMAL | PCI_HEADER_TYPE_MULTI_FUNCTION; // header_type = PCI_multifunction, generic piix3_reset(d); return d->devfn; @@ -355,7 +356,9 @@ int piix4_init(PCIBus *bus, int devfn) pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_0); // 82371AB/EB/MB PIIX4 PCI-to-ISA bridge pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA); - pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic + pci_conf[PCI_HEADER_TYPE] = + PCI_HEADER_TYPE_NORMAL | PCI_HEADER_TYPE_MULTI_FUNCTION; // header_type = PCI_multifunction, generic + piix4_reset(d); return d->devfn; diff --git a/hw/prep_pci.c b/hw/prep_pci.c index 2055005644..a97b845b43 100644 --- a/hw/prep_pci.c +++ b/hw/prep_pci.c @@ -161,7 +161,7 @@ PCIBus *pci_prep_init(qemu_irq *pic) pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST); d->config[0x0C] = 0x08; // cache_line_size d->config[0x0D] = 0x10; // latency_timer - d->config[0x0E] = 0x00; // header_type + d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type d->config[0x34] = 0x00; // capabilities_pointer return s->bus; diff --git a/hw/rtl8139.c b/hw/rtl8139.c index 19c7623c58..c0be1de829 100644 --- a/hw/rtl8139.c +++ b/hw/rtl8139.c @@ -3462,7 +3462,7 @@ PCIDevice *pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn) pci_conf[0x04] = 0x05; /* command = I/O space, Bus Master */ pci_conf[0x08] = RTL8139_PCI_REVID; /* PCI revision ID; >=0x20 is for 8139C+ */ pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET); - pci_conf[0x0e] = 0x00; /* header_type */ + pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; /* header_type */ pci_conf[0x3d] = 1; /* interrupt pin 0 */ pci_conf[0x34] = 0xdc; diff --git a/hw/sun4u.c b/hw/sun4u.c index de635d4293..8f9e56bb71 100644 --- a/hw/sun4u.c +++ b/hw/sun4u.c @@ -318,7 +318,7 @@ pci_ebus_init(PCIBus *bus, int devfn) s->config[0x09] = 0x00; // programming i/f pci_config_set_class(s->config, PCI_CLASS_BRIDGE_OTHER); s->config[0x0D] = 0x0a; // latency_timer - s->config[0x0E] = 0x00; // header_type + s->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type pci_register_io_region(s, 0, 0x1000000, PCI_ADDRESS_SPACE_MEM, ebus_mmio_mapfunc); diff --git a/hw/unin_pci.c b/hw/unin_pci.c index 9fc073ab54..b751916796 100644 --- a/hw/unin_pci.c +++ b/hw/unin_pci.c @@ -192,7 +192,7 @@ PCIBus *pci_pmac_init(qemu_irq *pic) pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST); d->config[0x0C] = 0x08; // cache_line_size d->config[0x0D] = 0x10; // latency_timer - d->config[0x0E] = 0x00; // header_type + d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type d->config[0x34] = 0x00; // capabilities_pointer #if 0 // XXX: not activated as PPC BIOS doesn't handle multiple buses properly @@ -205,7 +205,7 @@ PCIBus *pci_pmac_init(qemu_irq *pic) pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI); d->config[0x0C] = 0x08; // cache_line_size d->config[0x0D] = 0x20; // latency_timer - d->config[0x0E] = 0x01; // header_type + d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_BRIDGE; // header_type d->config[0x18] = 0x01; // primary_bus d->config[0x19] = 0x02; // secondary_bus @@ -240,7 +240,7 @@ PCIBus *pci_pmac_init(qemu_irq *pic) pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST); d->config[0x0C] = 0x08; // cache_line_size d->config[0x0D] = 0x10; // latency_timer - d->config[0x0E] = 0x00; // header_type + d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type // d->config[0x34] = 0x80; // capabilities_pointer #if 0 // XXX: not needed for now @@ -261,7 +261,7 @@ PCIBus *pci_pmac_init(qemu_irq *pic) pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST); d->config[0x0C] = 0x08; // cache_line_size d->config[0x0D] = 0x10; // latency_timer - d->config[0x0E] = 0x00; // header_type + d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type d->config[0x34] = 0x00; // capabilities_pointer #endif register_savevm("uninorth", 0, 1, pci_unin_save, pci_unin_load, d); diff --git a/hw/usb-uhci.c b/hw/usb-uhci.c index d42d394176..689d40ac69 100644 --- a/hw/usb-uhci.c +++ b/hw/usb-uhci.c @@ -1084,7 +1084,7 @@ void usb_uhci_piix3_init(PCIBus *bus, int devfn) pci_conf[0x08] = 0x01; // revision number pci_conf[0x09] = 0x00; pci_config_set_class(pci_conf, PCI_CLASS_SERIAL_USB); - pci_conf[0x0e] = 0x00; // header_type + pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type pci_conf[0x3d] = 4; // interrupt pin 3 pci_conf[0x60] = 0x10; // release number @@ -1118,7 +1118,7 @@ void usb_uhci_piix4_init(PCIBus *bus, int devfn) pci_conf[0x08] = 0x01; // revision number pci_conf[0x09] = 0x00; pci_config_set_class(pci_conf, PCI_CLASS_SERIAL_USB); - pci_conf[0x0e] = 0x00; // header_type + pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type pci_conf[0x3d] = 4; // interrupt pin 3 pci_conf[0x60] = 0x10; // release number diff --git a/hw/vga.c b/hw/vga.c index 517ce3d218..2de92afd8b 100644 --- a/hw/vga.c +++ b/hw/vga.c @@ -2507,7 +2507,7 @@ int pci_vga_init(PCIBus *bus, int vga_ram_size, pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_QEMU); pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_QEMU_VGA); pci_config_set_class(pci_conf, PCI_CLASS_DISPLAY_VGA); - pci_conf[0x0e] = 0x00; // header_type + pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type /* XXX: vga_ram_size must be a power of two */ pci_register_io_region(&d->dev, 0, vga_ram_size, diff --git a/hw/virtio.c b/hw/virtio.c index 4aa5f20a78..78c7637658 100644 --- a/hw/virtio.c +++ b/hw/virtio.c @@ -788,7 +788,7 @@ VirtIODevice *virtio_init_pci(PCIBus *bus, const char *name, config[0x09] = pif; pci_config_set_class(config, class_code); - config[0x0e] = 0x00; + config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; config[0x2c] = subvendor & 0xFF; config[0x2d] = (subvendor >> 8) & 0xFF; diff --git a/hw/vmware_vga.c b/hw/vmware_vga.c index 2299aff21c..26cf789817 100644 --- a/hw/vmware_vga.c +++ b/hw/vmware_vga.c @@ -1210,8 +1210,6 @@ static void pci_vmsvga_map_mem(PCIDevice *pci_dev, int region_num, iomemtype); } -#define PCI_CLASS_HEADERTYPE_00h 0x00 - void pci_vmsvga_init(PCIBus *bus, int vga_ram_size) { struct pci_vmsvga_state_s *s; @@ -1226,7 +1224,7 @@ void pci_vmsvga_init(PCIBus *bus, int vga_ram_size) pci_config_set_class(s->card.config, PCI_CLASS_DISPLAY_VGA); s->card.config[0x0c] = 0x08; /* Cache line size */ s->card.config[0x0d] = 0x40; /* Latency timer */ - s->card.config[0x0e] = PCI_CLASS_HEADERTYPE_00h; + s->card.config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; s->card.config[0x2c] = PCI_VENDOR_ID_VMWARE & 0xff; s->card.config[0x2d] = PCI_VENDOR_ID_VMWARE >> 8; s->card.config[0x2e] = SVGA_PCI_DEVICE_ID & 0xff; -- 2.11.4.GIT