target-i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include <sys/types.h>
  16 #include <sys/ioctl.h>
  17 #include <sys/mman.h>
  18
  19 #include <linux/kvm.h>
  20
  21 #include "qemu-common.h"
  22 #include "sysemu.h"
  23 #include "kvm.h"
  24 #include "cpu.h"
  25 #include "gdbstub.h"
  26
  27 //#define DEBUG_KVM
  28
  29 #ifdef DEBUG_KVM
  30 #define dprintf(fmt, ...) \
  31     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  32 #else
  33 #define dprintf(fmt, ...) \
  34     do { } while (0)
  35 #endif
  36
  37 #ifdef KVM_CAP_EXT_CPUID
  38
  39 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
  40 {
  41     struct kvm_cpuid2 *cpuid;
  42     int r, size;
  43
  44     size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
  45     cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size);
  46     cpuid->nent = max;
  47     r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
  48     if (r < 0) {
  49         if (r == -E2BIG) {
  50             qemu_free(cpuid);
  51             return NULL;
  52         } else {
  53             fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
  54                     strerror(-r));
  55             exit(1);
  56         }
  57     }
  58     return cpuid;
  59 }
  60
  61 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, int reg)
  62 {
  63     struct kvm_cpuid2 *cpuid;
  64     int i, max;
  65     uint32_t ret = 0;
  66     uint32_t cpuid_1_edx;
  67
  68     if (!kvm_check_extension(env->kvm_state, KVM_CAP_EXT_CPUID)) {
  69         return -1U;
  70     }
  71
  72     max = 1;
  73     while ((cpuid = try_get_cpuid(env->kvm_state, max)) == NULL) {
  74         max *= 2;
  75     }
  76
  77     for (i = 0; i < cpuid->nent; ++i) {
  78         if (cpuid->entries[i].function == function) {
  79             switch (reg) {
  80             case R_EAX:
  81                 ret = cpuid->entries[i].eax;
  82                 break;
  83             case R_EBX:
  84                 ret = cpuid->entries[i].ebx;
  85                 break;
  86             case R_ECX:
  87                 ret = cpuid->entries[i].ecx;
  88                 break;
  89             case R_EDX:
  90                 ret = cpuid->entries[i].edx;
  91                 if (function == 0x80000001) {
  92                     /* On Intel, kvm returns cpuid according to the Intel spec,
  93                      * so add missing bits according to the AMD spec:
  94                      */
  95                     cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, R_EDX);
  96                     ret |= cpuid_1_edx & 0xdfeff7ff;
  97                 }
  98                 break;
  99             }
 100         }
 101     }
 102
 103     qemu_free(cpuid);
 104
 105     return ret;
 106 }
 107
 108 #else
 109
 110 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, int reg)
 111 {
 112     return -1U;
 113 }
 114
 115 #endif
 116
 117 int kvm_arch_init_vcpu(CPUState *env)
 118 {
 119     struct {
 120         struct kvm_cpuid2 cpuid;
 121         struct kvm_cpuid_entry2 entries[100];
 122     } __attribute__((packed)) cpuid_data;
 123     uint32_t limit, i, j, cpuid_i;
 124     uint32_t unused;
 125
 126     cpuid_i = 0;
 127
 128     cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
 129
 130     for (i = 0; i <= limit; i++) {
 131         struct kvm_cpuid_entry2 *c = &cpuid_data.entries[cpuid_i++];
 132
 133         switch (i) {
 134         case 2: {
 135             /* Keep reading function 2 till all the input is received */
 136             int times;
 137
 138             c->function = i;
 139             c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
 140                        KVM_CPUID_FLAG_STATE_READ_NEXT;
 141             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 142             times = c->eax & 0xff;
 143
 144             for (j = 1; j < times; ++j) {
 145                 c = &cpuid_data.entries[cpuid_i++];
 146                 c->function = i;
 147                 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
 148                 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 149             }
 150             break;
 151         }
 152         case 4:
 153         case 0xb:
 154         case 0xd:
 155             for (j = 0; ; j++) {
 156                 c->function = i;
 157                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
 158                 c->index = j;
 159                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
 160
 161                 if (i == 4 && c->eax == 0)
 162                     break;
 163                 if (i == 0xb && !(c->ecx & 0xff00))
 164                     break;
 165                 if (i == 0xd && c->eax == 0)
 166                     break;
 167
 168                 c = &cpuid_data.entries[cpuid_i++];
 169             }
 170             break;
 171         default:
 172             c->function = i;
 173             c->flags = 0;
 174             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 175             break;
 176         }
 177     }
 178     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
 179
 180     for (i = 0x80000000; i <= limit; i++) {
 181         struct kvm_cpuid_entry2 *c = &cpuid_data.entries[cpuid_i++];
 182
 183         c->function = i;
 184         c->flags = 0;
 185         cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 186     }
 187
 188     cpuid_data.cpuid.nent = cpuid_i;
 189
 190     return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
 191 }
 192
 193 static int kvm_has_msr_star(CPUState *env)
 194 {
 195     static int has_msr_star;
 196     int ret;
 197
 198     /* first time */
 199     if (has_msr_star == 0) {
 200         struct kvm_msr_list msr_list, *kvm_msr_list;
 201
 202         has_msr_star = -1;
 203
 204         /* Obtain MSR list from KVM.  These are the MSRs that we must
 205          * save/restore */
 206         msr_list.nmsrs = 0;
 207         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, &msr_list);
 208         if (ret < 0)
 209             return 0;
 210
 211         kvm_msr_list = qemu_mallocz(sizeof(msr_list) +
 212                                     msr_list.nmsrs * sizeof(msr_list.indices[0]));
 213
 214         kvm_msr_list->nmsrs = msr_list.nmsrs;
 215         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
 216         if (ret >= 0) {
 217             int i;
 218
 219             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
 220                 if (kvm_msr_list->indices[i] == MSR_STAR) {
 221                     has_msr_star = 1;
 222                     break;
 223                 }
 224             }
 225         }
 226
 227         free(kvm_msr_list);
 228     }
 229
 230     if (has_msr_star == 1)
 231         return 1;
 232     return 0;
 233 }
 234
 235 int kvm_arch_init(KVMState *s, int smp_cpus)
 236 {
 237     int ret;
 238
 239     /* create vm86 tss.  KVM uses vm86 mode to emulate 16-bit code
 240      * directly.  In order to use vm86 mode, a TSS is needed.  Since this
 241      * must be part of guest physical memory, we need to allocate it.  Older
 242      * versions of KVM just assumed that it would be at the end of physical
 243      * memory but that doesn't work with more than 4GB of memory.  We simply
 244      * refuse to work with those older versions of KVM. */
 245     ret = kvm_ioctl(s, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
 246     if (ret <= 0) {
 247         fprintf(stderr, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
 248         return ret;
 249     }
 250
 251     /* this address is 3 pages before the bios, and the bios should present
 252      * as unavaible memory.  FIXME, need to ensure the e820 map deals with
 253      * this?
 254      */
 255     return kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, 0xfffbd000);
 256 }
 257
 258 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 259 {
 260     lhs->selector = rhs->selector;
 261     lhs->base = rhs->base;
 262     lhs->limit = rhs->limit;
 263     lhs->type = 3;
 264     lhs->present = 1;
 265     lhs->dpl = 3;
 266     lhs->db = 0;
 267     lhs->s = 1;
 268     lhs->l = 0;
 269     lhs->g = 0;
 270     lhs->avl = 0;
 271     lhs->unusable = 0;
 272 }
 273
 274 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 275 {
 276     unsigned flags = rhs->flags;
 277     lhs->selector = rhs->selector;
 278     lhs->base = rhs->base;
 279     lhs->limit = rhs->limit;
 280     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 281     lhs->present = (flags & DESC_P_MASK) != 0;
 282     lhs->dpl = rhs->selector & 3;
 283     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 284     lhs->s = (flags & DESC_S_MASK) != 0;
 285     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 286     lhs->g = (flags & DESC_G_MASK) != 0;
 287     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 288     lhs->unusable = 0;
 289 }
 290
 291 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 292 {
 293     lhs->selector = rhs->selector;
 294     lhs->base = rhs->base;
 295     lhs->limit = rhs->limit;
 296     lhs->flags =
 297         (rhs->type << DESC_TYPE_SHIFT)
 298         | (rhs->present * DESC_P_MASK)
 299         | (rhs->dpl << DESC_DPL_SHIFT)
 300         | (rhs->db << DESC_B_SHIFT)
 301         | (rhs->s * DESC_S_MASK)
 302         | (rhs->l << DESC_L_SHIFT)
 303         | (rhs->g * DESC_G_MASK)
 304         | (rhs->avl * DESC_AVL_MASK);
 305 }
 306
 307 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
 308 {
 309     if (set)
 310         *kvm_reg = *qemu_reg;
 311     else
 312         *qemu_reg = *kvm_reg;
 313 }
 314
 315 static int kvm_getput_regs(CPUState *env, int set)
 316 {
 317     struct kvm_regs regs;
 318     int ret = 0;
 319
 320     if (!set) {
 321         ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
 322         if (ret < 0)
 323             return ret;
 324     }
 325
 326     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
 327     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
 328     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
 329     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
 330     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
 331     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
 332     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
 333     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
 334 #ifdef TARGET_X86_64
 335     kvm_getput_reg(&regs.r8, &env->regs[8], set);
 336     kvm_getput_reg(&regs.r9, &env->regs[9], set);
 337     kvm_getput_reg(&regs.r10, &env->regs[10], set);
 338     kvm_getput_reg(&regs.r11, &env->regs[11], set);
 339     kvm_getput_reg(&regs.r12, &env->regs[12], set);
 340     kvm_getput_reg(&regs.r13, &env->regs[13], set);
 341     kvm_getput_reg(&regs.r14, &env->regs[14], set);
 342     kvm_getput_reg(&regs.r15, &env->regs[15], set);
 343 #endif
 344
 345     kvm_getput_reg(&regs.rflags, &env->eflags, set);
 346     kvm_getput_reg(&regs.rip, &env->eip, set);
 347
 348     if (set)
 349         ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
 350
 351     return ret;
 352 }
 353
 354 static int kvm_put_fpu(CPUState *env)
 355 {
 356     struct kvm_fpu fpu;
 357     int i;
 358
 359     memset(&fpu, 0, sizeof fpu);
 360     fpu.fsw = env->fpus & ~(7 << 11);
 361     fpu.fsw |= (env->fpstt & 7) << 11;
 362     fpu.fcw = env->fpuc;
 363     for (i = 0; i < 8; ++i)
 364         fpu.ftwx |= (!env->fptags[i]) << i;
 365     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 366     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 367     fpu.mxcsr = env->mxcsr;
 368
 369     return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
 370 }
 371
 372 static int kvm_put_sregs(CPUState *env)
 373 {
 374     struct kvm_sregs sregs;
 375
 376     memcpy(sregs.interrupt_bitmap,
 377            env->interrupt_bitmap,
 378            sizeof(sregs.interrupt_bitmap));
 379
 380     if ((env->eflags & VM_MASK)) {
 381             set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 382             set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 383             set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 384             set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 385             set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 386             set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 387     } else {
 388             set_seg(&sregs.cs, &env->segs[R_CS]);
 389             set_seg(&sregs.ds, &env->segs[R_DS]);
 390             set_seg(&sregs.es, &env->segs[R_ES]);
 391             set_seg(&sregs.fs, &env->segs[R_FS]);
 392             set_seg(&sregs.gs, &env->segs[R_GS]);
 393             set_seg(&sregs.ss, &env->segs[R_SS]);
 394
 395             if (env->cr[0] & CR0_PE_MASK) {
 396                 /* force ss cpl to cs cpl */
 397                 sregs.ss.selector = (sregs.ss.selector & ~3) |
 398                         (sregs.cs.selector & 3);
 399                 sregs.ss.dpl = sregs.ss.selector & 3;
 400             }
 401     }
 402
 403     set_seg(&sregs.tr, &env->tr);
 404     set_seg(&sregs.ldt, &env->ldt);
 405
 406     sregs.idt.limit = env->idt.limit;
 407     sregs.idt.base = env->idt.base;
 408     sregs.gdt.limit = env->gdt.limit;
 409     sregs.gdt.base = env->gdt.base;
 410
 411     sregs.cr0 = env->cr[0];
 412     sregs.cr2 = env->cr[2];
 413     sregs.cr3 = env->cr[3];
 414     sregs.cr4 = env->cr[4];
 415
 416     sregs.cr8 = cpu_get_apic_tpr(env);
 417     sregs.apic_base = cpu_get_apic_base(env);
 418
 419     sregs.efer = env->efer;
 420
 421     return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
 422 }
 423
 424 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
 425                               uint32_t index, uint64_t value)
 426 {
 427     entry->index = index;
 428     entry->data = value;
 429 }
 430
 431 static int kvm_put_msrs(CPUState *env)
 432 {
 433     struct {
 434         struct kvm_msrs info;
 435         struct kvm_msr_entry entries[100];
 436     } msr_data;
 437     struct kvm_msr_entry *msrs = msr_data.entries;
 438     int n = 0;
 439
 440     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
 441     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
 442     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
 443     if (kvm_has_msr_star(env))
 444         kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
 445     kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
 446     kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
 447 #ifdef TARGET_X86_64
 448     /* FIXME if lm capable */
 449     kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
 450     kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
 451     kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
 452     kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
 453 #endif
 454     msr_data.info.nmsrs = n;
 455
 456     return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
 457
 458 }
 459
 460
 461 static int kvm_get_fpu(CPUState *env)
 462 {
 463     struct kvm_fpu fpu;
 464     int i, ret;
 465
 466     ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
 467     if (ret < 0)
 468         return ret;
 469
 470     env->fpstt = (fpu.fsw >> 11) & 7;
 471     env->fpus = fpu.fsw;
 472     env->fpuc = fpu.fcw;
 473     for (i = 0; i < 8; ++i)
 474         env->fptags[i] = !((fpu.ftwx >> i) & 1);
 475     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
 476     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
 477     env->mxcsr = fpu.mxcsr;
 478
 479     return 0;
 480 }
 481
 482 static int kvm_get_sregs(CPUState *env)
 483 {
 484     struct kvm_sregs sregs;
 485     uint32_t hflags;
 486     int ret;
 487
 488     ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
 489     if (ret < 0)
 490         return ret;
 491
 492     memcpy(env->interrupt_bitmap,
 493            sregs.interrupt_bitmap,
 494            sizeof(sregs.interrupt_bitmap));
 495
 496     get_seg(&env->segs[R_CS], &sregs.cs);
 497     get_seg(&env->segs[R_DS], &sregs.ds);
 498     get_seg(&env->segs[R_ES], &sregs.es);
 499     get_seg(&env->segs[R_FS], &sregs.fs);
 500     get_seg(&env->segs[R_GS], &sregs.gs);
 501     get_seg(&env->segs[R_SS], &sregs.ss);
 502
 503     get_seg(&env->tr, &sregs.tr);
 504     get_seg(&env->ldt, &sregs.ldt);
 505
 506     env->idt.limit = sregs.idt.limit;
 507     env->idt.base = sregs.idt.base;
 508     env->gdt.limit = sregs.gdt.limit;
 509     env->gdt.base = sregs.gdt.base;
 510
 511     env->cr[0] = sregs.cr0;
 512     env->cr[2] = sregs.cr2;
 513     env->cr[3] = sregs.cr3;
 514     env->cr[4] = sregs.cr4;
 515
 516     cpu_set_apic_base(env, sregs.apic_base);
 517
 518     env->efer = sregs.efer;
 519     //cpu_set_apic_tpr(env, sregs.cr8);
 520
 521 #define HFLAG_COPY_MASK ~( \
 522                         HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
 523                         HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
 524                         HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
 525                         HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
 526
 527
 528
 529     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
 530     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
 531     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
 532             (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
 533     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
 534     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
 535             (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
 536
 537     if (env->efer & MSR_EFER_LMA) {
 538         hflags |= HF_LMA_MASK;
 539     }
 540
 541     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
 542         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
 543     } else {
 544         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
 545                 (DESC_B_SHIFT - HF_CS32_SHIFT);
 546         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
 547                 (DESC_B_SHIFT - HF_SS32_SHIFT);
 548         if (!(env->cr[0] & CR0_PE_MASK) ||
 549                    (env->eflags & VM_MASK) ||
 550                    !(hflags & HF_CS32_MASK)) {
 551                 hflags |= HF_ADDSEG_MASK;
 552             } else {
 553                 hflags |= ((env->segs[R_DS].base |
 554                                 env->segs[R_ES].base |
 555                                 env->segs[R_SS].base) != 0) <<
 556                     HF_ADDSEG_SHIFT;
 557             }
 558     }
 559     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
 560
 561     return 0;
 562 }
 563
 564 static int kvm_get_msrs(CPUState *env)
 565 {
 566     struct {
 567         struct kvm_msrs info;
 568         struct kvm_msr_entry entries[100];
 569     } msr_data;
 570     struct kvm_msr_entry *msrs = msr_data.entries;
 571     int ret, i, n;
 572
 573     n = 0;
 574     msrs[n++].index = MSR_IA32_SYSENTER_CS;
 575     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
 576     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
 577     if (kvm_has_msr_star(env))
 578         msrs[n++].index = MSR_STAR;
 579     msrs[n++].index = MSR_IA32_TSC;
 580     msrs[n++].index = MSR_VM_HSAVE_PA;
 581 #ifdef TARGET_X86_64
 582     /* FIXME lm_capable_kernel */
 583     msrs[n++].index = MSR_CSTAR;
 584     msrs[n++].index = MSR_KERNELGSBASE;
 585     msrs[n++].index = MSR_FMASK;
 586     msrs[n++].index = MSR_LSTAR;
 587 #endif
 588     msr_data.info.nmsrs = n;
 589     ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
 590     if (ret < 0)
 591         return ret;
 592
 593     for (i = 0; i < ret; i++) {
 594         switch (msrs[i].index) {
 595         case MSR_IA32_SYSENTER_CS:
 596             env->sysenter_cs = msrs[i].data;
 597             break;
 598         case MSR_IA32_SYSENTER_ESP:
 599             env->sysenter_esp = msrs[i].data;
 600             break;
 601         case MSR_IA32_SYSENTER_EIP:
 602             env->sysenter_eip = msrs[i].data;
 603             break;
 604         case MSR_STAR:
 605             env->star = msrs[i].data;
 606             break;
 607 #ifdef TARGET_X86_64
 608         case MSR_CSTAR:
 609             env->cstar = msrs[i].data;
 610             break;
 611         case MSR_KERNELGSBASE:
 612             env->kernelgsbase = msrs[i].data;
 613             break;
 614         case MSR_FMASK:
 615             env->fmask = msrs[i].data;
 616             break;
 617         case MSR_LSTAR:
 618             env->lstar = msrs[i].data;
 619             break;
 620 #endif
 621         case MSR_IA32_TSC:
 622             env->tsc = msrs[i].data;
 623             break;
 624         case MSR_VM_HSAVE_PA:
 625             env->vm_hsave = msrs[i].data;
 626             break;
 627         }
 628     }
 629
 630     return 0;
 631 }
 632
 633 int kvm_arch_put_registers(CPUState *env)
 634 {
 635     int ret;
 636
 637     ret = kvm_getput_regs(env, 1);
 638     if (ret < 0)
 639         return ret;
 640
 641     ret = kvm_put_fpu(env);
 642     if (ret < 0)
 643         return ret;
 644
 645     ret = kvm_put_sregs(env);
 646     if (ret < 0)
 647         return ret;
 648
 649     ret = kvm_put_msrs(env);
 650     if (ret < 0)
 651         return ret;
 652
 653     return 0;
 654 }
 655
 656 int kvm_arch_get_registers(CPUState *env)
 657 {
 658     int ret;
 659
 660     ret = kvm_getput_regs(env, 0);
 661     if (ret < 0)
 662         return ret;
 663
 664     ret = kvm_get_fpu(env);
 665     if (ret < 0)
 666         return ret;
 667
 668     ret = kvm_get_sregs(env);
 669     if (ret < 0)
 670         return ret;
 671
 672     ret = kvm_get_msrs(env);
 673     if (ret < 0)
 674         return ret;
 675
 676     return 0;
 677 }
 678
 679 int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
 680 {
 681     /* Try to inject an interrupt if the guest can accept it */
 682     if (run->ready_for_interrupt_injection &&
 683         (env->interrupt_request & CPU_INTERRUPT_HARD) &&
 684         (env->eflags & IF_MASK)) {
 685         int irq;
 686
 687         env->interrupt_request &= ~CPU_INTERRUPT_HARD;
 688         irq = cpu_get_pic_interrupt(env);
 689         if (irq >= 0) {
 690             struct kvm_interrupt intr;
 691             intr.irq = irq;
 692             /* FIXME: errors */
 693             dprintf("injected interrupt %d\n", irq);
 694             kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
 695         }
 696     }
 697
 698     /* If we have an interrupt but the guest is not ready to receive an
 699      * interrupt, request an interrupt window exit.  This will
 700      * cause a return to userspace as soon as the guest is ready to
 701      * receive interrupts. */
 702     if ((env->interrupt_request & CPU_INTERRUPT_HARD))
 703         run->request_interrupt_window = 1;
 704     else
 705         run->request_interrupt_window = 0;
 706
 707     dprintf("setting tpr\n");
 708     run->cr8 = cpu_get_apic_tpr(env);
 709
 710     return 0;
 711 }
 712
 713 int kvm_arch_post_run(CPUState *env, struct kvm_run *run)
 714 {
 715     if (run->if_flag)
 716         env->eflags |= IF_MASK;
 717     else
 718         env->eflags &= ~IF_MASK;
 719
 720     cpu_set_apic_tpr(env, run->cr8);
 721     cpu_set_apic_base(env, run->apic_base);
 722
 723     return 0;
 724 }
 725
 726 static int kvm_handle_halt(CPUState *env)
 727 {
 728     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
 729           (env->eflags & IF_MASK)) &&
 730         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
 731         env->halted = 1;
 732         env->exception_index = EXCP_HLT;
 733         return 0;
 734     }
 735
 736     return 1;
 737 }
 738
 739 int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
 740 {
 741     int ret = 0;
 742
 743     switch (run->exit_reason) {
 744     case KVM_EXIT_HLT:
 745         dprintf("handle_hlt\n");
 746         ret = kvm_handle_halt(env);
 747         break;
 748     }
 749
 750     return ret;
 751 }
 752
 753 #ifdef KVM_CAP_SET_GUEST_DEBUG
 754 int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
 755 {
 756     const static uint8_t int3 = 0xcc;
 757
 758     if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
 759         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1))
 760         return -EINVAL;
 761     return 0;
 762 }
 763
 764 int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
 765 {
 766     uint8_t int3;
 767
 768     if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
 769         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1))
 770         return -EINVAL;
 771     return 0;
 772 }
 773
 774 static struct {
 775     target_ulong addr;
 776     int len;
 777     int type;
 778 } hw_breakpoint[4];
 779
 780 static int nb_hw_breakpoint;
 781
 782 static int find_hw_breakpoint(target_ulong addr, int len, int type)
 783 {
 784     int n;
 785
 786     for (n = 0; n < nb_hw_breakpoint; n++)
 787         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
 788             (hw_breakpoint[n].len == len || len == -1))
 789             return n;
 790     return -1;
 791 }
 792
 793 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
 794                                   target_ulong len, int type)
 795 {
 796     switch (type) {
 797     case GDB_BREAKPOINT_HW:
 798         len = 1;
 799         break;
 800     case GDB_WATCHPOINT_WRITE:
 801     case GDB_WATCHPOINT_ACCESS:
 802         switch (len) {
 803         case 1:
 804             break;
 805         case 2:
 806         case 4:
 807         case 8:
 808             if (addr & (len - 1))
 809                 return -EINVAL;
 810             break;
 811         default:
 812             return -EINVAL;
 813         }
 814         break;
 815     default:
 816         return -ENOSYS;
 817     }
 818
 819     if (nb_hw_breakpoint == 4)
 820         return -ENOBUFS;
 821
 822     if (find_hw_breakpoint(addr, len, type) >= 0)
 823         return -EEXIST;
 824
 825     hw_breakpoint[nb_hw_breakpoint].addr = addr;
 826     hw_breakpoint[nb_hw_breakpoint].len = len;
 827     hw_breakpoint[nb_hw_breakpoint].type = type;
 828     nb_hw_breakpoint++;
 829
 830     return 0;
 831 }
 832
 833 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
 834                                   target_ulong len, int type)
 835 {
 836     int n;
 837
 838     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
 839     if (n < 0)
 840         return -ENOENT;
 841
 842     nb_hw_breakpoint--;
 843     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
 844
 845     return 0;
 846 }
 847
 848 void kvm_arch_remove_all_hw_breakpoints(void)
 849 {
 850     nb_hw_breakpoint = 0;
 851 }
 852
 853 static CPUWatchpoint hw_watchpoint;
 854
 855 int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
 856 {
 857     int handle = 0;
 858     int n;
 859
 860     if (arch_info->exception == 1) {
 861         if (arch_info->dr6 & (1 << 14)) {
 862             if (cpu_single_env->singlestep_enabled)
 863                 handle = 1;
 864         } else {
 865             for (n = 0; n < 4; n++)
 866                 if (arch_info->dr6 & (1 << n))
 867                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
 868                     case 0x0:
 869                         handle = 1;
 870                         break;
 871                     case 0x1:
 872                         handle = 1;
 873                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
 874                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
 875                         hw_watchpoint.flags = BP_MEM_WRITE;
 876                         break;
 877                     case 0x3:
 878                         handle = 1;
 879                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
 880                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
 881                         hw_watchpoint.flags = BP_MEM_ACCESS;
 882                         break;
 883                     }
 884         }
 885     } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc))
 886         handle = 1;
 887
 888     if (!handle)
 889         kvm_update_guest_debug(cpu_single_env,
 890                         (arch_info->exception == 1) ?
 891                         KVM_GUESTDBG_INJECT_DB : KVM_GUESTDBG_INJECT_BP);
 892
 893     return handle;
 894 }
 895
 896 void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
 897 {
 898     const uint8_t type_code[] = {
 899         [GDB_BREAKPOINT_HW] = 0x0,
 900         [GDB_WATCHPOINT_WRITE] = 0x1,
 901         [GDB_WATCHPOINT_ACCESS] = 0x3
 902     };
 903     const uint8_t len_code[] = {
 904         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
 905     };
 906     int n;
 907
 908     if (kvm_sw_breakpoints_active(env))
 909         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
 910
 911     if (nb_hw_breakpoint > 0) {
 912         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
 913         dbg->arch.debugreg[7] = 0x0600;
 914         for (n = 0; n < nb_hw_breakpoint; n++) {
 915             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
 916             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
 917                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
 918                 (len_code[hw_breakpoint[n].len] << (18 + n*4));
 919         }
 920     }
 921 }
 922 #endif /* KVM_CAP_SET_GUEST_DEBUG */