From ae01847f9cbbf9b80252cd36ec645ee821809037 Mon Sep 17 00:00:00 2001 From: Nathan Froyd Date: Tue, 23 Feb 2010 12:21:31 -0800 Subject: [PATCH] target-ppc: fix SPE evsplat* instructions The shifts in the gen_evsplat* functions were expecting rA to be masked, not extracted, and so used the wrong shift amounts to sign-extend or pad with zeroes. Signed-off-by: Nathan Froyd Signed-off-by: Aurelien Jarno --- target-ppc/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index d4e81ce89b..0b11fda880 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -7001,7 +7001,7 @@ static inline void gen_evmergelohi(DisasContext *ctx) } static inline void gen_evsplati(DisasContext *ctx) { - uint64_t imm = ((int32_t)(rA(ctx->opcode) << 11)) >> 27; + uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27; #if defined(TARGET_PPC64) tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm); @@ -7012,7 +7012,7 @@ static inline void gen_evsplati(DisasContext *ctx) } static inline void gen_evsplatfi(DisasContext *ctx) { - uint64_t imm = rA(ctx->opcode) << 11; + uint64_t imm = rA(ctx->opcode) << 27; #if defined(TARGET_PPC64) tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm); -- 2.11.4.GIT