target-mips: signal RI Exception on instructions removed in R6
commitfecd2646957bf7c2e0612c6b218903d982560014
authorLeon Alrae <leon.alrae@imgtec.com>
Fri, 27 Jun 2014 07:49:00 +0000 (27 08:49 +0100)
committerLeon Alrae <leon.alrae@imgtec.com>
Mon, 13 Oct 2014 11:38:24 +0000 (13 12:38 +0100)
tree74f0395c70500fb02ec16718524e4e3442f07ad7
parentfa0d2f69e716cdc67012109f1f991c32ab961082
target-mips: signal RI Exception on instructions removed in R6

Signal Reserved Instruction Exception on instructions that do not exist in R6.
In this commit the following groups of preR6 instructions are marked as deleted:
- Floating Point Paired Single
- Floating Point Compare
- conditional moves / branches on FPU conditions
- branch likelies
- unaligned loads / stores
- traps
- legacy accumulator instructions
- COP1X
- MIPS-3D

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips/translate.c