| commit | fa439fc5d7f9094eab4158a906b0e1498504c9cf | |
| author | Peter Maydell <peter.maydell@linaro.org> | |
| Fri, 12 Sep 2014 13:06:50 +0000 (12 14:06 +0100) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Fri, 12 Sep 2014 13:06:50 +0000 (12 14:06 +0100) | ||
| tree | 13f53d79a1a04ed9394bf80a679b69c48fe8a41c | treesnapshot (tar.gz zip) |
| parent | 995939a650c13ad6ac51db089aeb006e0771ea61 | commitdiff |
target-arm: Make *IS TLB maintenance ops affect all CPUs
The ARM architecture defines that the "IS" variants of TLB
maintenance operations must affect all TLBs in the Inner Shareable
domain, which for us means all CPUs. We were incorrectly implementing
these to only affect the current CPU, which meant that SMP TCG
operation was unstable.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1410274883-9578-3-git-send-email-peter.maydell@linaro.org
Cc: qemu-stable@nongnu.org
The ARM architecture defines that the "IS" variants of TLB
maintenance operations must affect all TLBs in the Inner Shareable
domain, which for us means all CPUs. We were incorrectly implementing
these to only affect the current CPU, which meant that SMP TCG
operation was unstable.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1410274883-9578-3-git-send-email-peter.maydell@linaro.org
Cc: qemu-stable@nongnu.org
| target-arm/helper.c | diffblobblamehistory |