| commit | f31b035a9f10dc9b57f01c426110af845d453ce2 | |
| author | Leon Alrae <leon.alrae@imgtec.com> | |
| Fri, 11 Jul 2014 15:11:35 +0000 (11 16:11 +0100) | ||
| committer | Leon Alrae <leon.alrae@imgtec.com> | |
| Mon, 3 Nov 2014 11:48:34 +0000 (3 11:48 +0000) | ||
| tree | ed772e97f451b594713583a7ce103dbe76638fef | treesnapshot (tar.gz zip) |
| parent | ba801af429aaa68f6cc03842c8b6be81a6ede65a | commitdiff |
target-mips: correctly handle access to unimplemented CP0 register
Release 6 limits the number of cases where software can cause UNDEFINED or
UNPREDICTABLE behaviour. In this case, when accessing reserved / unimplemented
CP0 register, writes are ignored and reads return 0.
In pre-R6 the behaviour is not specified, but generating RI exception is not
what the real HW does.
Additionally, remove CP0 Random register as it became reserved in Release 6.
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
Release 6 limits the number of cases where software can cause UNDEFINED or
UNPREDICTABLE behaviour. In this case, when accessing reserved / unimplemented
CP0 register, writes are ignored and reads return 0.
In pre-R6 the behaviour is not specified, but generating RI exception is not
what the real HW does.
Additionally, remove CP0 Random register as it became reserved in Release 6.
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
| target-mips/translate.c | diffblobblamehistory |