| commit | 5dffff5a4746075a4609366440c2c67983eec106 | |
| author | Tom Musta <tommusta@gmail.com> | |
| Wed, 12 Feb 2014 21:22:55 +0000 (12 15:22 -0600) | ||
| committer | Alexander Graf <agraf@suse.de> | |
| Wed, 5 Mar 2014 02:06:52 +0000 (5 03:06 +0100) | ||
| tree | 035e1bb4bc73b37f67ada7a4928638735443ea4a | treesnapshot (tar.gz zip) |
| parent | 9b47bb490c1b272c16b8f5e216b74456a3e17322 | commitdiff |
target-ppc: Altivec 2.07: Add Support for Dual Altivec Instructions
Some Alitvec instructions introduced in Power ISA Version 2.07 use bit 31
(aka the "Rc" bit) as an opcode bit. However, QEMU for PowerPC uses
bits 0-5 and 21-30 for opcodes and not bit 31.
This patch introduces macros that will handle this situation by injecting
an auxiliary handler which decodes bit 31 in invokes one of two standard
handlers. Since the instructions are not, in general, from the same version
of the ISA, two sets of PPC_*/PPC2_* instruction tags are supported.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Some Alitvec instructions introduced in Power ISA Version 2.07 use bit 31
(aka the "Rc" bit) as an opcode bit. However, QEMU for PowerPC uses
bits 0-5 and 21-30 for opcodes and not bit 31.
This patch introduces macros that will handle this situation by injecting
an auxiliary handler which decodes bit 31 in invokes one of two standard
handlers. Since the instructions are not, in general, from the same version
of the ISA, two sets of PPC_*/PPC2_* instruction tags are supported.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
| target-ppc/translate.c | diffblobblamehistory |