4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
8 * Anthony Liguori <aliguori@us.ibm.com>
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
15 #include <sys/types.h>
16 #include <sys/ioctl.h>
18 #include <sys/utsname.h>
20 #include <linux/kvm.h>
21 #include <linux/kvm_para.h>
23 #include "qemu-common.h"
29 #include "host-utils.h"
39 #define DPRINTF(fmt, ...) \
40 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
42 #define DPRINTF(fmt, ...) \
46 #define MSR_KVM_WALL_CLOCK 0x11
47 #define MSR_KVM_SYSTEM_TIME 0x12
50 #define BUS_MCEERR_AR 4
53 #define BUS_MCEERR_AO 5
56 const KVMCapabilityInfo kvm_arch_required_capabilities
[] = {
57 KVM_CAP_INFO(SET_TSS_ADDR
),
58 KVM_CAP_INFO(EXT_CPUID
),
59 KVM_CAP_INFO(MP_STATE
),
63 static bool has_msr_star
;
64 static bool has_msr_hsave_pa
;
65 static bool has_msr_tsc_deadline
;
66 static bool has_msr_async_pf_en
;
67 static bool has_msr_pv_eoi_en
;
68 static bool has_msr_misc_enable
;
69 static int lm_capable_kernel
;
71 bool kvm_allows_irq0_override(void)
73 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
76 static struct kvm_cpuid2
*try_get_cpuid(KVMState
*s
, int max
)
78 struct kvm_cpuid2
*cpuid
;
81 size
= sizeof(*cpuid
) + max
* sizeof(*cpuid
->entries
);
82 cpuid
= (struct kvm_cpuid2
*)g_malloc0(size
);
84 r
= kvm_ioctl(s
, KVM_GET_SUPPORTED_CPUID
, cpuid
);
85 if (r
== 0 && cpuid
->nent
>= max
) {
93 fprintf(stderr
, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
101 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
104 static struct kvm_cpuid2
*get_supported_cpuid(KVMState
*s
)
106 struct kvm_cpuid2
*cpuid
;
108 while ((cpuid
= try_get_cpuid(s
, max
)) == NULL
) {
114 struct kvm_para_features
{
117 } para_features
[] = {
118 { KVM_CAP_CLOCKSOURCE
, KVM_FEATURE_CLOCKSOURCE
},
119 { KVM_CAP_NOP_IO_DELAY
, KVM_FEATURE_NOP_IO_DELAY
},
120 { KVM_CAP_PV_MMU
, KVM_FEATURE_MMU_OP
},
121 { KVM_CAP_ASYNC_PF
, KVM_FEATURE_ASYNC_PF
},
125 static int get_para_features(KVMState
*s
)
129 for (i
= 0; i
< ARRAY_SIZE(para_features
) - 1; i
++) {
130 if (kvm_check_extension(s
, para_features
[i
].cap
)) {
131 features
|= (1 << para_features
[i
].feature
);
139 /* Returns the value for a specific register on the cpuid entry
141 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2
*entry
, int reg
)
161 /* Find matching entry for function/index on kvm_cpuid2 struct
163 static struct kvm_cpuid_entry2
*cpuid_find_entry(struct kvm_cpuid2
*cpuid
,
168 for (i
= 0; i
< cpuid
->nent
; ++i
) {
169 if (cpuid
->entries
[i
].function
== function
&&
170 cpuid
->entries
[i
].index
== index
) {
171 return &cpuid
->entries
[i
];
178 uint32_t kvm_arch_get_supported_cpuid(KVMState
*s
, uint32_t function
,
179 uint32_t index
, int reg
)
181 struct kvm_cpuid2
*cpuid
;
183 uint32_t cpuid_1_edx
;
186 cpuid
= get_supported_cpuid(s
);
188 struct kvm_cpuid_entry2
*entry
= cpuid_find_entry(cpuid
, function
, index
);
191 ret
= cpuid_entry_get_reg(entry
, reg
);
194 /* Fixups for the data returned by KVM, below */
199 /* KVM before 2.6.30 misreports the following features */
200 ret
|= CPUID_MTRR
| CPUID_PAT
| CPUID_MCE
| CPUID_MCA
;
203 /* On Intel, kvm returns cpuid according to the Intel spec,
204 * so add missing bits according to the AMD spec:
206 cpuid_1_edx
= kvm_arch_get_supported_cpuid(s
, 1, 0, R_EDX
);
207 ret
|= cpuid_1_edx
& CPUID_EXT2_AMD_ALIASES
;
214 /* fallback for older kernels */
215 if ((function
== KVM_CPUID_FEATURES
) && !found
) {
216 ret
= get_para_features(s
);
222 typedef struct HWPoisonPage
{
224 QLIST_ENTRY(HWPoisonPage
) list
;
227 static QLIST_HEAD(, HWPoisonPage
) hwpoison_page_list
=
228 QLIST_HEAD_INITIALIZER(hwpoison_page_list
);
230 static void kvm_unpoison_all(void *param
)
232 HWPoisonPage
*page
, *next_page
;
234 QLIST_FOREACH_SAFE(page
, &hwpoison_page_list
, list
, next_page
) {
235 QLIST_REMOVE(page
, list
);
236 qemu_ram_remap(page
->ram_addr
, TARGET_PAGE_SIZE
);
241 static void kvm_hwpoison_page_add(ram_addr_t ram_addr
)
245 QLIST_FOREACH(page
, &hwpoison_page_list
, list
) {
246 if (page
->ram_addr
== ram_addr
) {
250 page
= g_malloc(sizeof(HWPoisonPage
));
251 page
->ram_addr
= ram_addr
;
252 QLIST_INSERT_HEAD(&hwpoison_page_list
, page
, list
);
255 static int kvm_get_mce_cap_supported(KVMState
*s
, uint64_t *mce_cap
,
260 r
= kvm_check_extension(s
, KVM_CAP_MCE
);
263 return kvm_ioctl(s
, KVM_X86_GET_MCE_CAP_SUPPORTED
, mce_cap
);
268 static void kvm_mce_inject(CPUX86State
*env
, hwaddr paddr
, int code
)
270 uint64_t status
= MCI_STATUS_VAL
| MCI_STATUS_UC
| MCI_STATUS_EN
|
271 MCI_STATUS_MISCV
| MCI_STATUS_ADDRV
| MCI_STATUS_S
;
272 uint64_t mcg_status
= MCG_STATUS_MCIP
;
274 if (code
== BUS_MCEERR_AR
) {
275 status
|= MCI_STATUS_AR
| 0x134;
276 mcg_status
|= MCG_STATUS_EIPV
;
279 mcg_status
|= MCG_STATUS_RIPV
;
281 cpu_x86_inject_mce(NULL
, env
, 9, status
, mcg_status
, paddr
,
282 (MCM_ADDR_PHYS
<< 6) | 0xc,
283 cpu_x86_support_mca_broadcast(env
) ?
284 MCE_INJECT_BROADCAST
: 0);
287 static void hardware_memory_error(void)
289 fprintf(stderr
, "Hardware memory error!\n");
293 int kvm_arch_on_sigbus_vcpu(CPUX86State
*env
, int code
, void *addr
)
298 if ((env
->mcg_cap
& MCG_SER_P
) && addr
299 && (code
== BUS_MCEERR_AR
|| code
== BUS_MCEERR_AO
)) {
300 if (qemu_ram_addr_from_host(addr
, &ram_addr
) ||
301 !kvm_physical_memory_addr_from_host(env
->kvm_state
, addr
, &paddr
)) {
302 fprintf(stderr
, "Hardware memory error for memory used by "
303 "QEMU itself instead of guest system!\n");
304 /* Hope we are lucky for AO MCE */
305 if (code
== BUS_MCEERR_AO
) {
308 hardware_memory_error();
311 kvm_hwpoison_page_add(ram_addr
);
312 kvm_mce_inject(env
, paddr
, code
);
314 if (code
== BUS_MCEERR_AO
) {
316 } else if (code
== BUS_MCEERR_AR
) {
317 hardware_memory_error();
325 int kvm_arch_on_sigbus(int code
, void *addr
)
327 if ((first_cpu
->mcg_cap
& MCG_SER_P
) && addr
&& code
== BUS_MCEERR_AO
) {
331 /* Hope we are lucky for AO MCE */
332 if (qemu_ram_addr_from_host(addr
, &ram_addr
) ||
333 !kvm_physical_memory_addr_from_host(first_cpu
->kvm_state
, addr
,
335 fprintf(stderr
, "Hardware memory error for memory used by "
336 "QEMU itself instead of guest system!: %p\n", addr
);
339 kvm_hwpoison_page_add(ram_addr
);
340 kvm_mce_inject(first_cpu
, paddr
, code
);
342 if (code
== BUS_MCEERR_AO
) {
344 } else if (code
== BUS_MCEERR_AR
) {
345 hardware_memory_error();
353 static int kvm_inject_mce_oldstyle(CPUX86State
*env
)
355 if (!kvm_has_vcpu_events() && env
->exception_injected
== EXCP12_MCHK
) {
356 unsigned int bank
, bank_num
= env
->mcg_cap
& 0xff;
357 struct kvm_x86_mce mce
;
359 env
->exception_injected
= -1;
362 * There must be at least one bank in use if an MCE is pending.
363 * Find it and use its values for the event injection.
365 for (bank
= 0; bank
< bank_num
; bank
++) {
366 if (env
->mce_banks
[bank
* 4 + 1] & MCI_STATUS_VAL
) {
370 assert(bank
< bank_num
);
373 mce
.status
= env
->mce_banks
[bank
* 4 + 1];
374 mce
.mcg_status
= env
->mcg_status
;
375 mce
.addr
= env
->mce_banks
[bank
* 4 + 2];
376 mce
.misc
= env
->mce_banks
[bank
* 4 + 3];
378 return kvm_vcpu_ioctl(env
, KVM_X86_SET_MCE
, &mce
);
383 static void cpu_update_state(void *opaque
, int running
, RunState state
)
385 CPUX86State
*env
= opaque
;
388 env
->tsc_valid
= false;
392 int kvm_arch_init_vcpu(CPUX86State
*env
)
395 struct kvm_cpuid2 cpuid
;
396 struct kvm_cpuid_entry2 entries
[100];
397 } QEMU_PACKED cpuid_data
;
398 KVMState
*s
= env
->kvm_state
;
399 uint32_t limit
, i
, j
, cpuid_i
;
401 struct kvm_cpuid_entry2
*c
;
402 uint32_t signature
[3];
405 env
->cpuid_features
&= kvm_arch_get_supported_cpuid(s
, 1, 0, R_EDX
);
407 i
= env
->cpuid_ext_features
& CPUID_EXT_HYPERVISOR
;
408 j
= env
->cpuid_ext_features
& CPUID_EXT_TSC_DEADLINE_TIMER
;
409 env
->cpuid_ext_features
&= kvm_arch_get_supported_cpuid(s
, 1, 0, R_ECX
);
410 env
->cpuid_ext_features
|= i
;
411 if (j
&& kvm_irqchip_in_kernel() &&
412 kvm_check_extension(s
, KVM_CAP_TSC_DEADLINE_TIMER
)) {
413 env
->cpuid_ext_features
|= CPUID_EXT_TSC_DEADLINE_TIMER
;
416 env
->cpuid_ext2_features
&= kvm_arch_get_supported_cpuid(s
, 0x80000001,
418 env
->cpuid_ext3_features
&= kvm_arch_get_supported_cpuid(s
, 0x80000001,
420 env
->cpuid_svm_features
&= kvm_arch_get_supported_cpuid(s
, 0x8000000A,
425 /* Paravirtualization CPUIDs */
426 c
= &cpuid_data
.entries
[cpuid_i
++];
427 memset(c
, 0, sizeof(*c
));
428 c
->function
= KVM_CPUID_SIGNATURE
;
429 if (!hyperv_enabled()) {
430 memcpy(signature
, "KVMKVMKVM\0\0\0", 12);
433 memcpy(signature
, "Microsoft Hv", 12);
434 c
->eax
= HYPERV_CPUID_MIN
;
436 c
->ebx
= signature
[0];
437 c
->ecx
= signature
[1];
438 c
->edx
= signature
[2];
440 c
= &cpuid_data
.entries
[cpuid_i
++];
441 memset(c
, 0, sizeof(*c
));
442 c
->function
= KVM_CPUID_FEATURES
;
443 c
->eax
= env
->cpuid_kvm_features
&
444 kvm_arch_get_supported_cpuid(s
, KVM_CPUID_FEATURES
, 0, R_EAX
);
446 if (hyperv_enabled()) {
447 memcpy(signature
, "Hv#1\0\0\0\0\0\0\0\0", 12);
448 c
->eax
= signature
[0];
450 c
= &cpuid_data
.entries
[cpuid_i
++];
451 memset(c
, 0, sizeof(*c
));
452 c
->function
= HYPERV_CPUID_VERSION
;
456 c
= &cpuid_data
.entries
[cpuid_i
++];
457 memset(c
, 0, sizeof(*c
));
458 c
->function
= HYPERV_CPUID_FEATURES
;
459 if (hyperv_relaxed_timing_enabled()) {
460 c
->eax
|= HV_X64_MSR_HYPERCALL_AVAILABLE
;
462 if (hyperv_vapic_recommended()) {
463 c
->eax
|= HV_X64_MSR_HYPERCALL_AVAILABLE
;
464 c
->eax
|= HV_X64_MSR_APIC_ACCESS_AVAILABLE
;
467 c
= &cpuid_data
.entries
[cpuid_i
++];
468 memset(c
, 0, sizeof(*c
));
469 c
->function
= HYPERV_CPUID_ENLIGHTMENT_INFO
;
470 if (hyperv_relaxed_timing_enabled()) {
471 c
->eax
|= HV_X64_RELAXED_TIMING_RECOMMENDED
;
473 if (hyperv_vapic_recommended()) {
474 c
->eax
|= HV_X64_APIC_ACCESS_RECOMMENDED
;
476 c
->ebx
= hyperv_get_spinlock_retries();
478 c
= &cpuid_data
.entries
[cpuid_i
++];
479 memset(c
, 0, sizeof(*c
));
480 c
->function
= HYPERV_CPUID_IMPLEMENT_LIMITS
;
484 c
= &cpuid_data
.entries
[cpuid_i
++];
485 memset(c
, 0, sizeof(*c
));
486 c
->function
= KVM_CPUID_SIGNATURE_NEXT
;
487 memcpy(signature
, "KVMKVMKVM\0\0\0", 12);
489 c
->ebx
= signature
[0];
490 c
->ecx
= signature
[1];
491 c
->edx
= signature
[2];
494 has_msr_async_pf_en
= c
->eax
& (1 << KVM_FEATURE_ASYNC_PF
);
496 has_msr_pv_eoi_en
= c
->eax
& (1 << KVM_FEATURE_PV_EOI
);
498 cpu_x86_cpuid(env
, 0, 0, &limit
, &unused
, &unused
, &unused
);
500 for (i
= 0; i
<= limit
; i
++) {
501 c
= &cpuid_data
.entries
[cpuid_i
++];
505 /* Keep reading function 2 till all the input is received */
509 c
->flags
= KVM_CPUID_FLAG_STATEFUL_FUNC
|
510 KVM_CPUID_FLAG_STATE_READ_NEXT
;
511 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
512 times
= c
->eax
& 0xff;
514 for (j
= 1; j
< times
; ++j
) {
515 c
= &cpuid_data
.entries
[cpuid_i
++];
517 c
->flags
= KVM_CPUID_FLAG_STATEFUL_FUNC
;
518 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
526 if (i
== 0xd && j
== 64) {
530 c
->flags
= KVM_CPUID_FLAG_SIGNIFCANT_INDEX
;
532 cpu_x86_cpuid(env
, i
, j
, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
534 if (i
== 4 && c
->eax
== 0) {
537 if (i
== 0xb && !(c
->ecx
& 0xff00)) {
540 if (i
== 0xd && c
->eax
== 0) {
543 c
= &cpuid_data
.entries
[cpuid_i
++];
549 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
553 cpu_x86_cpuid(env
, 0x80000000, 0, &limit
, &unused
, &unused
, &unused
);
555 for (i
= 0x80000000; i
<= limit
; i
++) {
556 c
= &cpuid_data
.entries
[cpuid_i
++];
560 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
563 /* Call Centaur's CPUID instructions they are supported. */
564 if (env
->cpuid_xlevel2
> 0) {
565 env
->cpuid_ext4_features
&=
566 kvm_arch_get_supported_cpuid(s
, 0xC0000001, 0, R_EDX
);
567 cpu_x86_cpuid(env
, 0xC0000000, 0, &limit
, &unused
, &unused
, &unused
);
569 for (i
= 0xC0000000; i
<= limit
; i
++) {
570 c
= &cpuid_data
.entries
[cpuid_i
++];
574 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
578 cpuid_data
.cpuid
.nent
= cpuid_i
;
580 if (((env
->cpuid_version
>> 8)&0xF) >= 6
581 && (env
->cpuid_features
&(CPUID_MCE
|CPUID_MCA
)) == (CPUID_MCE
|CPUID_MCA
)
582 && kvm_check_extension(env
->kvm_state
, KVM_CAP_MCE
) > 0) {
587 ret
= kvm_get_mce_cap_supported(env
->kvm_state
, &mcg_cap
, &banks
);
589 fprintf(stderr
, "kvm_get_mce_cap_supported: %s", strerror(-ret
));
593 if (banks
> MCE_BANKS_DEF
) {
594 banks
= MCE_BANKS_DEF
;
596 mcg_cap
&= MCE_CAP_DEF
;
598 ret
= kvm_vcpu_ioctl(env
, KVM_X86_SETUP_MCE
, &mcg_cap
);
600 fprintf(stderr
, "KVM_X86_SETUP_MCE: %s", strerror(-ret
));
604 env
->mcg_cap
= mcg_cap
;
607 qemu_add_vm_change_state_handler(cpu_update_state
, env
);
609 cpuid_data
.cpuid
.padding
= 0;
610 r
= kvm_vcpu_ioctl(env
, KVM_SET_CPUID2
, &cpuid_data
);
615 r
= kvm_check_extension(env
->kvm_state
, KVM_CAP_TSC_CONTROL
);
616 if (r
&& env
->tsc_khz
) {
617 r
= kvm_vcpu_ioctl(env
, KVM_SET_TSC_KHZ
, env
->tsc_khz
);
619 fprintf(stderr
, "KVM_SET_TSC_KHZ failed\n");
624 if (kvm_has_xsave()) {
625 env
->kvm_xsave_buf
= qemu_memalign(4096, sizeof(struct kvm_xsave
));
631 void kvm_arch_reset_vcpu(CPUX86State
*env
)
633 X86CPU
*cpu
= x86_env_get_cpu(env
);
635 env
->exception_injected
= -1;
636 env
->interrupt_injected
= -1;
638 if (kvm_irqchip_in_kernel()) {
639 env
->mp_state
= cpu_is_bsp(cpu
) ? KVM_MP_STATE_RUNNABLE
:
640 KVM_MP_STATE_UNINITIALIZED
;
642 env
->mp_state
= KVM_MP_STATE_RUNNABLE
;
646 static int kvm_get_supported_msrs(KVMState
*s
)
648 static int kvm_supported_msrs
;
652 if (kvm_supported_msrs
== 0) {
653 struct kvm_msr_list msr_list
, *kvm_msr_list
;
655 kvm_supported_msrs
= -1;
657 /* Obtain MSR list from KVM. These are the MSRs that we must
660 ret
= kvm_ioctl(s
, KVM_GET_MSR_INDEX_LIST
, &msr_list
);
661 if (ret
< 0 && ret
!= -E2BIG
) {
664 /* Old kernel modules had a bug and could write beyond the provided
665 memory. Allocate at least a safe amount of 1K. */
666 kvm_msr_list
= g_malloc0(MAX(1024, sizeof(msr_list
) +
668 sizeof(msr_list
.indices
[0])));
670 kvm_msr_list
->nmsrs
= msr_list
.nmsrs
;
671 ret
= kvm_ioctl(s
, KVM_GET_MSR_INDEX_LIST
, kvm_msr_list
);
675 for (i
= 0; i
< kvm_msr_list
->nmsrs
; i
++) {
676 if (kvm_msr_list
->indices
[i
] == MSR_STAR
) {
680 if (kvm_msr_list
->indices
[i
] == MSR_VM_HSAVE_PA
) {
681 has_msr_hsave_pa
= true;
684 if (kvm_msr_list
->indices
[i
] == MSR_IA32_TSCDEADLINE
) {
685 has_msr_tsc_deadline
= true;
688 if (kvm_msr_list
->indices
[i
] == MSR_IA32_MISC_ENABLE
) {
689 has_msr_misc_enable
= true;
695 g_free(kvm_msr_list
);
701 int kvm_arch_init(KVMState
*s
)
703 QemuOptsList
*list
= qemu_find_opts("machine");
704 uint64_t identity_base
= 0xfffbc000;
707 struct utsname utsname
;
709 ret
= kvm_get_supported_msrs(s
);
715 lm_capable_kernel
= strcmp(utsname
.machine
, "x86_64") == 0;
718 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
719 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
720 * Since these must be part of guest physical memory, we need to allocate
721 * them, both by setting their start addresses in the kernel and by
722 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
724 * Older KVM versions may not support setting the identity map base. In
725 * that case we need to stick with the default, i.e. a 256K maximum BIOS
728 if (kvm_check_extension(s
, KVM_CAP_SET_IDENTITY_MAP_ADDR
)) {
729 /* Allows up to 16M BIOSes. */
730 identity_base
= 0xfeffc000;
732 ret
= kvm_vm_ioctl(s
, KVM_SET_IDENTITY_MAP_ADDR
, &identity_base
);
738 /* Set TSS base one page after EPT identity map. */
739 ret
= kvm_vm_ioctl(s
, KVM_SET_TSS_ADDR
, identity_base
+ 0x1000);
744 /* Tell fw_cfg to notify the BIOS to reserve the range. */
745 ret
= e820_add_entry(identity_base
, 0x4000, E820_RESERVED
);
747 fprintf(stderr
, "e820_add_entry() table is full\n");
750 qemu_register_reset(kvm_unpoison_all
, NULL
);
752 if (!QTAILQ_EMPTY(&list
->head
)) {
753 shadow_mem
= qemu_opt_get_size(QTAILQ_FIRST(&list
->head
),
754 "kvm_shadow_mem", -1);
755 if (shadow_mem
!= -1) {
757 ret
= kvm_vm_ioctl(s
, KVM_SET_NR_MMU_PAGES
, shadow_mem
);
766 static void set_v8086_seg(struct kvm_segment
*lhs
, const SegmentCache
*rhs
)
768 lhs
->selector
= rhs
->selector
;
769 lhs
->base
= rhs
->base
;
770 lhs
->limit
= rhs
->limit
;
782 static void set_seg(struct kvm_segment
*lhs
, const SegmentCache
*rhs
)
784 unsigned flags
= rhs
->flags
;
785 lhs
->selector
= rhs
->selector
;
786 lhs
->base
= rhs
->base
;
787 lhs
->limit
= rhs
->limit
;
788 lhs
->type
= (flags
>> DESC_TYPE_SHIFT
) & 15;
789 lhs
->present
= (flags
& DESC_P_MASK
) != 0;
790 lhs
->dpl
= (flags
>> DESC_DPL_SHIFT
) & 3;
791 lhs
->db
= (flags
>> DESC_B_SHIFT
) & 1;
792 lhs
->s
= (flags
& DESC_S_MASK
) != 0;
793 lhs
->l
= (flags
>> DESC_L_SHIFT
) & 1;
794 lhs
->g
= (flags
& DESC_G_MASK
) != 0;
795 lhs
->avl
= (flags
& DESC_AVL_MASK
) != 0;
800 static void get_seg(SegmentCache
*lhs
, const struct kvm_segment
*rhs
)
802 lhs
->selector
= rhs
->selector
;
803 lhs
->base
= rhs
->base
;
804 lhs
->limit
= rhs
->limit
;
805 lhs
->flags
= (rhs
->type
<< DESC_TYPE_SHIFT
) |
806 (rhs
->present
* DESC_P_MASK
) |
807 (rhs
->dpl
<< DESC_DPL_SHIFT
) |
808 (rhs
->db
<< DESC_B_SHIFT
) |
809 (rhs
->s
* DESC_S_MASK
) |
810 (rhs
->l
<< DESC_L_SHIFT
) |
811 (rhs
->g
* DESC_G_MASK
) |
812 (rhs
->avl
* DESC_AVL_MASK
);
815 static void kvm_getput_reg(__u64
*kvm_reg
, target_ulong
*qemu_reg
, int set
)
818 *kvm_reg
= *qemu_reg
;
820 *qemu_reg
= *kvm_reg
;
824 static int kvm_getput_regs(CPUX86State
*env
, int set
)
826 struct kvm_regs regs
;
830 ret
= kvm_vcpu_ioctl(env
, KVM_GET_REGS
, ®s
);
836 kvm_getput_reg(®s
.rax
, &env
->regs
[R_EAX
], set
);
837 kvm_getput_reg(®s
.rbx
, &env
->regs
[R_EBX
], set
);
838 kvm_getput_reg(®s
.rcx
, &env
->regs
[R_ECX
], set
);
839 kvm_getput_reg(®s
.rdx
, &env
->regs
[R_EDX
], set
);
840 kvm_getput_reg(®s
.rsi
, &env
->regs
[R_ESI
], set
);
841 kvm_getput_reg(®s
.rdi
, &env
->regs
[R_EDI
], set
);
842 kvm_getput_reg(®s
.rsp
, &env
->regs
[R_ESP
], set
);
843 kvm_getput_reg(®s
.rbp
, &env
->regs
[R_EBP
], set
);
845 kvm_getput_reg(®s
.r8
, &env
->regs
[8], set
);
846 kvm_getput_reg(®s
.r9
, &env
->regs
[9], set
);
847 kvm_getput_reg(®s
.r10
, &env
->regs
[10], set
);
848 kvm_getput_reg(®s
.r11
, &env
->regs
[11], set
);
849 kvm_getput_reg(®s
.r12
, &env
->regs
[12], set
);
850 kvm_getput_reg(®s
.r13
, &env
->regs
[13], set
);
851 kvm_getput_reg(®s
.r14
, &env
->regs
[14], set
);
852 kvm_getput_reg(®s
.r15
, &env
->regs
[15], set
);
855 kvm_getput_reg(®s
.rflags
, &env
->eflags
, set
);
856 kvm_getput_reg(®s
.rip
, &env
->eip
, set
);
859 ret
= kvm_vcpu_ioctl(env
, KVM_SET_REGS
, ®s
);
865 static int kvm_put_fpu(CPUX86State
*env
)
870 memset(&fpu
, 0, sizeof fpu
);
871 fpu
.fsw
= env
->fpus
& ~(7 << 11);
872 fpu
.fsw
|= (env
->fpstt
& 7) << 11;
874 fpu
.last_opcode
= env
->fpop
;
875 fpu
.last_ip
= env
->fpip
;
876 fpu
.last_dp
= env
->fpdp
;
877 for (i
= 0; i
< 8; ++i
) {
878 fpu
.ftwx
|= (!env
->fptags
[i
]) << i
;
880 memcpy(fpu
.fpr
, env
->fpregs
, sizeof env
->fpregs
);
881 memcpy(fpu
.xmm
, env
->xmm_regs
, sizeof env
->xmm_regs
);
882 fpu
.mxcsr
= env
->mxcsr
;
884 return kvm_vcpu_ioctl(env
, KVM_SET_FPU
, &fpu
);
887 #define XSAVE_FCW_FSW 0
888 #define XSAVE_FTW_FOP 1
889 #define XSAVE_CWD_RIP 2
890 #define XSAVE_CWD_RDP 4
891 #define XSAVE_MXCSR 6
892 #define XSAVE_ST_SPACE 8
893 #define XSAVE_XMM_SPACE 40
894 #define XSAVE_XSTATE_BV 128
895 #define XSAVE_YMMH_SPACE 144
897 static int kvm_put_xsave(CPUX86State
*env
)
899 struct kvm_xsave
* xsave
= env
->kvm_xsave_buf
;
900 uint16_t cwd
, swd
, twd
;
903 if (!kvm_has_xsave()) {
904 return kvm_put_fpu(env
);
907 memset(xsave
, 0, sizeof(struct kvm_xsave
));
909 swd
= env
->fpus
& ~(7 << 11);
910 swd
|= (env
->fpstt
& 7) << 11;
912 for (i
= 0; i
< 8; ++i
) {
913 twd
|= (!env
->fptags
[i
]) << i
;
915 xsave
->region
[XSAVE_FCW_FSW
] = (uint32_t)(swd
<< 16) + cwd
;
916 xsave
->region
[XSAVE_FTW_FOP
] = (uint32_t)(env
->fpop
<< 16) + twd
;
917 memcpy(&xsave
->region
[XSAVE_CWD_RIP
], &env
->fpip
, sizeof(env
->fpip
));
918 memcpy(&xsave
->region
[XSAVE_CWD_RDP
], &env
->fpdp
, sizeof(env
->fpdp
));
919 memcpy(&xsave
->region
[XSAVE_ST_SPACE
], env
->fpregs
,
921 memcpy(&xsave
->region
[XSAVE_XMM_SPACE
], env
->xmm_regs
,
922 sizeof env
->xmm_regs
);
923 xsave
->region
[XSAVE_MXCSR
] = env
->mxcsr
;
924 *(uint64_t *)&xsave
->region
[XSAVE_XSTATE_BV
] = env
->xstate_bv
;
925 memcpy(&xsave
->region
[XSAVE_YMMH_SPACE
], env
->ymmh_regs
,
926 sizeof env
->ymmh_regs
);
927 r
= kvm_vcpu_ioctl(env
, KVM_SET_XSAVE
, xsave
);
931 static int kvm_put_xcrs(CPUX86State
*env
)
933 struct kvm_xcrs xcrs
;
935 if (!kvm_has_xcrs()) {
941 xcrs
.xcrs
[0].xcr
= 0;
942 xcrs
.xcrs
[0].value
= env
->xcr0
;
943 return kvm_vcpu_ioctl(env
, KVM_SET_XCRS
, &xcrs
);
946 static int kvm_put_sregs(CPUX86State
*env
)
948 struct kvm_sregs sregs
;
950 memset(sregs
.interrupt_bitmap
, 0, sizeof(sregs
.interrupt_bitmap
));
951 if (env
->interrupt_injected
>= 0) {
952 sregs
.interrupt_bitmap
[env
->interrupt_injected
/ 64] |=
953 (uint64_t)1 << (env
->interrupt_injected
% 64);
956 if ((env
->eflags
& VM_MASK
)) {
957 set_v8086_seg(&sregs
.cs
, &env
->segs
[R_CS
]);
958 set_v8086_seg(&sregs
.ds
, &env
->segs
[R_DS
]);
959 set_v8086_seg(&sregs
.es
, &env
->segs
[R_ES
]);
960 set_v8086_seg(&sregs
.fs
, &env
->segs
[R_FS
]);
961 set_v8086_seg(&sregs
.gs
, &env
->segs
[R_GS
]);
962 set_v8086_seg(&sregs
.ss
, &env
->segs
[R_SS
]);
964 set_seg(&sregs
.cs
, &env
->segs
[R_CS
]);
965 set_seg(&sregs
.ds
, &env
->segs
[R_DS
]);
966 set_seg(&sregs
.es
, &env
->segs
[R_ES
]);
967 set_seg(&sregs
.fs
, &env
->segs
[R_FS
]);
968 set_seg(&sregs
.gs
, &env
->segs
[R_GS
]);
969 set_seg(&sregs
.ss
, &env
->segs
[R_SS
]);
972 set_seg(&sregs
.tr
, &env
->tr
);
973 set_seg(&sregs
.ldt
, &env
->ldt
);
975 sregs
.idt
.limit
= env
->idt
.limit
;
976 sregs
.idt
.base
= env
->idt
.base
;
977 memset(sregs
.idt
.padding
, 0, sizeof sregs
.idt
.padding
);
978 sregs
.gdt
.limit
= env
->gdt
.limit
;
979 sregs
.gdt
.base
= env
->gdt
.base
;
980 memset(sregs
.gdt
.padding
, 0, sizeof sregs
.gdt
.padding
);
982 sregs
.cr0
= env
->cr
[0];
983 sregs
.cr2
= env
->cr
[2];
984 sregs
.cr3
= env
->cr
[3];
985 sregs
.cr4
= env
->cr
[4];
987 sregs
.cr8
= cpu_get_apic_tpr(env
->apic_state
);
988 sregs
.apic_base
= cpu_get_apic_base(env
->apic_state
);
990 sregs
.efer
= env
->efer
;
992 return kvm_vcpu_ioctl(env
, KVM_SET_SREGS
, &sregs
);
995 static void kvm_msr_entry_set(struct kvm_msr_entry
*entry
,
996 uint32_t index
, uint64_t value
)
998 entry
->index
= index
;
1002 static int kvm_put_msrs(CPUX86State
*env
, int level
)
1005 struct kvm_msrs info
;
1006 struct kvm_msr_entry entries
[100];
1008 struct kvm_msr_entry
*msrs
= msr_data
.entries
;
1011 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_SYSENTER_CS
, env
->sysenter_cs
);
1012 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_SYSENTER_ESP
, env
->sysenter_esp
);
1013 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_SYSENTER_EIP
, env
->sysenter_eip
);
1014 kvm_msr_entry_set(&msrs
[n
++], MSR_PAT
, env
->pat
);
1016 kvm_msr_entry_set(&msrs
[n
++], MSR_STAR
, env
->star
);
1018 if (has_msr_hsave_pa
) {
1019 kvm_msr_entry_set(&msrs
[n
++], MSR_VM_HSAVE_PA
, env
->vm_hsave
);
1021 if (has_msr_tsc_deadline
) {
1022 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_TSCDEADLINE
, env
->tsc_deadline
);
1024 if (has_msr_misc_enable
) {
1025 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_MISC_ENABLE
,
1026 env
->msr_ia32_misc_enable
);
1028 #ifdef TARGET_X86_64
1029 if (lm_capable_kernel
) {
1030 kvm_msr_entry_set(&msrs
[n
++], MSR_CSTAR
, env
->cstar
);
1031 kvm_msr_entry_set(&msrs
[n
++], MSR_KERNELGSBASE
, env
->kernelgsbase
);
1032 kvm_msr_entry_set(&msrs
[n
++], MSR_FMASK
, env
->fmask
);
1033 kvm_msr_entry_set(&msrs
[n
++], MSR_LSTAR
, env
->lstar
);
1036 if (level
== KVM_PUT_FULL_STATE
) {
1038 * KVM is yet unable to synchronize TSC values of multiple VCPUs on
1039 * writeback. Until this is fixed, we only write the offset to SMP
1040 * guests after migration, desynchronizing the VCPUs, but avoiding
1041 * huge jump-backs that would occur without any writeback at all.
1043 if (smp_cpus
== 1 || env
->tsc
!= 0) {
1044 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_TSC
, env
->tsc
);
1048 * The following paravirtual MSRs have side effects on the guest or are
1049 * too heavy for normal writeback. Limit them to reset or full state
1052 if (level
>= KVM_PUT_RESET_STATE
) {
1053 kvm_msr_entry_set(&msrs
[n
++], MSR_KVM_SYSTEM_TIME
,
1054 env
->system_time_msr
);
1055 kvm_msr_entry_set(&msrs
[n
++], MSR_KVM_WALL_CLOCK
, env
->wall_clock_msr
);
1056 if (has_msr_async_pf_en
) {
1057 kvm_msr_entry_set(&msrs
[n
++], MSR_KVM_ASYNC_PF_EN
,
1058 env
->async_pf_en_msr
);
1060 if (has_msr_pv_eoi_en
) {
1061 kvm_msr_entry_set(&msrs
[n
++], MSR_KVM_PV_EOI_EN
,
1062 env
->pv_eoi_en_msr
);
1064 if (hyperv_hypercall_available()) {
1065 kvm_msr_entry_set(&msrs
[n
++], HV_X64_MSR_GUEST_OS_ID
, 0);
1066 kvm_msr_entry_set(&msrs
[n
++], HV_X64_MSR_HYPERCALL
, 0);
1068 if (hyperv_vapic_recommended()) {
1069 kvm_msr_entry_set(&msrs
[n
++], HV_X64_MSR_APIC_ASSIST_PAGE
, 0);
1075 kvm_msr_entry_set(&msrs
[n
++], MSR_MCG_STATUS
, env
->mcg_status
);
1076 kvm_msr_entry_set(&msrs
[n
++], MSR_MCG_CTL
, env
->mcg_ctl
);
1077 for (i
= 0; i
< (env
->mcg_cap
& 0xff) * 4; i
++) {
1078 kvm_msr_entry_set(&msrs
[n
++], MSR_MC0_CTL
+ i
, env
->mce_banks
[i
]);
1082 msr_data
.info
.nmsrs
= n
;
1084 return kvm_vcpu_ioctl(env
, KVM_SET_MSRS
, &msr_data
);
1089 static int kvm_get_fpu(CPUX86State
*env
)
1094 ret
= kvm_vcpu_ioctl(env
, KVM_GET_FPU
, &fpu
);
1099 env
->fpstt
= (fpu
.fsw
>> 11) & 7;
1100 env
->fpus
= fpu
.fsw
;
1101 env
->fpuc
= fpu
.fcw
;
1102 env
->fpop
= fpu
.last_opcode
;
1103 env
->fpip
= fpu
.last_ip
;
1104 env
->fpdp
= fpu
.last_dp
;
1105 for (i
= 0; i
< 8; ++i
) {
1106 env
->fptags
[i
] = !((fpu
.ftwx
>> i
) & 1);
1108 memcpy(env
->fpregs
, fpu
.fpr
, sizeof env
->fpregs
);
1109 memcpy(env
->xmm_regs
, fpu
.xmm
, sizeof env
->xmm_regs
);
1110 env
->mxcsr
= fpu
.mxcsr
;
1115 static int kvm_get_xsave(CPUX86State
*env
)
1117 struct kvm_xsave
* xsave
= env
->kvm_xsave_buf
;
1119 uint16_t cwd
, swd
, twd
;
1121 if (!kvm_has_xsave()) {
1122 return kvm_get_fpu(env
);
1125 ret
= kvm_vcpu_ioctl(env
, KVM_GET_XSAVE
, xsave
);
1130 cwd
= (uint16_t)xsave
->region
[XSAVE_FCW_FSW
];
1131 swd
= (uint16_t)(xsave
->region
[XSAVE_FCW_FSW
] >> 16);
1132 twd
= (uint16_t)xsave
->region
[XSAVE_FTW_FOP
];
1133 env
->fpop
= (uint16_t)(xsave
->region
[XSAVE_FTW_FOP
] >> 16);
1134 env
->fpstt
= (swd
>> 11) & 7;
1137 for (i
= 0; i
< 8; ++i
) {
1138 env
->fptags
[i
] = !((twd
>> i
) & 1);
1140 memcpy(&env
->fpip
, &xsave
->region
[XSAVE_CWD_RIP
], sizeof(env
->fpip
));
1141 memcpy(&env
->fpdp
, &xsave
->region
[XSAVE_CWD_RDP
], sizeof(env
->fpdp
));
1142 env
->mxcsr
= xsave
->region
[XSAVE_MXCSR
];
1143 memcpy(env
->fpregs
, &xsave
->region
[XSAVE_ST_SPACE
],
1144 sizeof env
->fpregs
);
1145 memcpy(env
->xmm_regs
, &xsave
->region
[XSAVE_XMM_SPACE
],
1146 sizeof env
->xmm_regs
);
1147 env
->xstate_bv
= *(uint64_t *)&xsave
->region
[XSAVE_XSTATE_BV
];
1148 memcpy(env
->ymmh_regs
, &xsave
->region
[XSAVE_YMMH_SPACE
],
1149 sizeof env
->ymmh_regs
);
1153 static int kvm_get_xcrs(CPUX86State
*env
)
1156 struct kvm_xcrs xcrs
;
1158 if (!kvm_has_xcrs()) {
1162 ret
= kvm_vcpu_ioctl(env
, KVM_GET_XCRS
, &xcrs
);
1167 for (i
= 0; i
< xcrs
.nr_xcrs
; i
++) {
1168 /* Only support xcr0 now */
1169 if (xcrs
.xcrs
[0].xcr
== 0) {
1170 env
->xcr0
= xcrs
.xcrs
[0].value
;
1177 static int kvm_get_sregs(CPUX86State
*env
)
1179 struct kvm_sregs sregs
;
1183 ret
= kvm_vcpu_ioctl(env
, KVM_GET_SREGS
, &sregs
);
1188 /* There can only be one pending IRQ set in the bitmap at a time, so try
1189 to find it and save its number instead (-1 for none). */
1190 env
->interrupt_injected
= -1;
1191 for (i
= 0; i
< ARRAY_SIZE(sregs
.interrupt_bitmap
); i
++) {
1192 if (sregs
.interrupt_bitmap
[i
]) {
1193 bit
= ctz64(sregs
.interrupt_bitmap
[i
]);
1194 env
->interrupt_injected
= i
* 64 + bit
;
1199 get_seg(&env
->segs
[R_CS
], &sregs
.cs
);
1200 get_seg(&env
->segs
[R_DS
], &sregs
.ds
);
1201 get_seg(&env
->segs
[R_ES
], &sregs
.es
);
1202 get_seg(&env
->segs
[R_FS
], &sregs
.fs
);
1203 get_seg(&env
->segs
[R_GS
], &sregs
.gs
);
1204 get_seg(&env
->segs
[R_SS
], &sregs
.ss
);
1206 get_seg(&env
->tr
, &sregs
.tr
);
1207 get_seg(&env
->ldt
, &sregs
.ldt
);
1209 env
->idt
.limit
= sregs
.idt
.limit
;
1210 env
->idt
.base
= sregs
.idt
.base
;
1211 env
->gdt
.limit
= sregs
.gdt
.limit
;
1212 env
->gdt
.base
= sregs
.gdt
.base
;
1214 env
->cr
[0] = sregs
.cr0
;
1215 env
->cr
[2] = sregs
.cr2
;
1216 env
->cr
[3] = sregs
.cr3
;
1217 env
->cr
[4] = sregs
.cr4
;
1219 env
->efer
= sregs
.efer
;
1221 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1223 #define HFLAG_COPY_MASK \
1224 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1225 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1226 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1227 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1229 hflags
= (env
->segs
[R_CS
].flags
>> DESC_DPL_SHIFT
) & HF_CPL_MASK
;
1230 hflags
|= (env
->cr
[0] & CR0_PE_MASK
) << (HF_PE_SHIFT
- CR0_PE_SHIFT
);
1231 hflags
|= (env
->cr
[0] << (HF_MP_SHIFT
- CR0_MP_SHIFT
)) &
1232 (HF_MP_MASK
| HF_EM_MASK
| HF_TS_MASK
);
1233 hflags
|= (env
->eflags
& (HF_TF_MASK
| HF_VM_MASK
| HF_IOPL_MASK
));
1234 hflags
|= (env
->cr
[4] & CR4_OSFXSR_MASK
) <<
1235 (HF_OSFXSR_SHIFT
- CR4_OSFXSR_SHIFT
);
1237 if (env
->efer
& MSR_EFER_LMA
) {
1238 hflags
|= HF_LMA_MASK
;
1241 if ((hflags
& HF_LMA_MASK
) && (env
->segs
[R_CS
].flags
& DESC_L_MASK
)) {
1242 hflags
|= HF_CS32_MASK
| HF_SS32_MASK
| HF_CS64_MASK
;
1244 hflags
|= (env
->segs
[R_CS
].flags
& DESC_B_MASK
) >>
1245 (DESC_B_SHIFT
- HF_CS32_SHIFT
);
1246 hflags
|= (env
->segs
[R_SS
].flags
& DESC_B_MASK
) >>
1247 (DESC_B_SHIFT
- HF_SS32_SHIFT
);
1248 if (!(env
->cr
[0] & CR0_PE_MASK
) || (env
->eflags
& VM_MASK
) ||
1249 !(hflags
& HF_CS32_MASK
)) {
1250 hflags
|= HF_ADDSEG_MASK
;
1252 hflags
|= ((env
->segs
[R_DS
].base
| env
->segs
[R_ES
].base
|
1253 env
->segs
[R_SS
].base
) != 0) << HF_ADDSEG_SHIFT
;
1256 env
->hflags
= (env
->hflags
& HFLAG_COPY_MASK
) | hflags
;
1261 static int kvm_get_msrs(CPUX86State
*env
)
1264 struct kvm_msrs info
;
1265 struct kvm_msr_entry entries
[100];
1267 struct kvm_msr_entry
*msrs
= msr_data
.entries
;
1271 msrs
[n
++].index
= MSR_IA32_SYSENTER_CS
;
1272 msrs
[n
++].index
= MSR_IA32_SYSENTER_ESP
;
1273 msrs
[n
++].index
= MSR_IA32_SYSENTER_EIP
;
1274 msrs
[n
++].index
= MSR_PAT
;
1276 msrs
[n
++].index
= MSR_STAR
;
1278 if (has_msr_hsave_pa
) {
1279 msrs
[n
++].index
= MSR_VM_HSAVE_PA
;
1281 if (has_msr_tsc_deadline
) {
1282 msrs
[n
++].index
= MSR_IA32_TSCDEADLINE
;
1284 if (has_msr_misc_enable
) {
1285 msrs
[n
++].index
= MSR_IA32_MISC_ENABLE
;
1288 if (!env
->tsc_valid
) {
1289 msrs
[n
++].index
= MSR_IA32_TSC
;
1290 env
->tsc_valid
= !runstate_is_running();
1293 #ifdef TARGET_X86_64
1294 if (lm_capable_kernel
) {
1295 msrs
[n
++].index
= MSR_CSTAR
;
1296 msrs
[n
++].index
= MSR_KERNELGSBASE
;
1297 msrs
[n
++].index
= MSR_FMASK
;
1298 msrs
[n
++].index
= MSR_LSTAR
;
1301 msrs
[n
++].index
= MSR_KVM_SYSTEM_TIME
;
1302 msrs
[n
++].index
= MSR_KVM_WALL_CLOCK
;
1303 if (has_msr_async_pf_en
) {
1304 msrs
[n
++].index
= MSR_KVM_ASYNC_PF_EN
;
1306 if (has_msr_pv_eoi_en
) {
1307 msrs
[n
++].index
= MSR_KVM_PV_EOI_EN
;
1311 msrs
[n
++].index
= MSR_MCG_STATUS
;
1312 msrs
[n
++].index
= MSR_MCG_CTL
;
1313 for (i
= 0; i
< (env
->mcg_cap
& 0xff) * 4; i
++) {
1314 msrs
[n
++].index
= MSR_MC0_CTL
+ i
;
1318 msr_data
.info
.nmsrs
= n
;
1319 ret
= kvm_vcpu_ioctl(env
, KVM_GET_MSRS
, &msr_data
);
1324 for (i
= 0; i
< ret
; i
++) {
1325 switch (msrs
[i
].index
) {
1326 case MSR_IA32_SYSENTER_CS
:
1327 env
->sysenter_cs
= msrs
[i
].data
;
1329 case MSR_IA32_SYSENTER_ESP
:
1330 env
->sysenter_esp
= msrs
[i
].data
;
1332 case MSR_IA32_SYSENTER_EIP
:
1333 env
->sysenter_eip
= msrs
[i
].data
;
1336 env
->pat
= msrs
[i
].data
;
1339 env
->star
= msrs
[i
].data
;
1341 #ifdef TARGET_X86_64
1343 env
->cstar
= msrs
[i
].data
;
1345 case MSR_KERNELGSBASE
:
1346 env
->kernelgsbase
= msrs
[i
].data
;
1349 env
->fmask
= msrs
[i
].data
;
1352 env
->lstar
= msrs
[i
].data
;
1356 env
->tsc
= msrs
[i
].data
;
1358 case MSR_IA32_TSCDEADLINE
:
1359 env
->tsc_deadline
= msrs
[i
].data
;
1361 case MSR_VM_HSAVE_PA
:
1362 env
->vm_hsave
= msrs
[i
].data
;
1364 case MSR_KVM_SYSTEM_TIME
:
1365 env
->system_time_msr
= msrs
[i
].data
;
1367 case MSR_KVM_WALL_CLOCK
:
1368 env
->wall_clock_msr
= msrs
[i
].data
;
1370 case MSR_MCG_STATUS
:
1371 env
->mcg_status
= msrs
[i
].data
;
1374 env
->mcg_ctl
= msrs
[i
].data
;
1376 case MSR_IA32_MISC_ENABLE
:
1377 env
->msr_ia32_misc_enable
= msrs
[i
].data
;
1380 if (msrs
[i
].index
>= MSR_MC0_CTL
&&
1381 msrs
[i
].index
< MSR_MC0_CTL
+ (env
->mcg_cap
& 0xff) * 4) {
1382 env
->mce_banks
[msrs
[i
].index
- MSR_MC0_CTL
] = msrs
[i
].data
;
1385 case MSR_KVM_ASYNC_PF_EN
:
1386 env
->async_pf_en_msr
= msrs
[i
].data
;
1388 case MSR_KVM_PV_EOI_EN
:
1389 env
->pv_eoi_en_msr
= msrs
[i
].data
;
1397 static int kvm_put_mp_state(CPUX86State
*env
)
1399 struct kvm_mp_state mp_state
= { .mp_state
= env
->mp_state
};
1401 return kvm_vcpu_ioctl(env
, KVM_SET_MP_STATE
, &mp_state
);
1404 static int kvm_get_mp_state(CPUX86State
*env
)
1406 struct kvm_mp_state mp_state
;
1409 ret
= kvm_vcpu_ioctl(env
, KVM_GET_MP_STATE
, &mp_state
);
1413 env
->mp_state
= mp_state
.mp_state
;
1414 if (kvm_irqchip_in_kernel()) {
1415 env
->halted
= (mp_state
.mp_state
== KVM_MP_STATE_HALTED
);
1420 static int kvm_get_apic(CPUX86State
*env
)
1422 DeviceState
*apic
= env
->apic_state
;
1423 struct kvm_lapic_state kapic
;
1426 if (apic
&& kvm_irqchip_in_kernel()) {
1427 ret
= kvm_vcpu_ioctl(env
, KVM_GET_LAPIC
, &kapic
);
1432 kvm_get_apic_state(apic
, &kapic
);
1437 static int kvm_put_apic(CPUX86State
*env
)
1439 DeviceState
*apic
= env
->apic_state
;
1440 struct kvm_lapic_state kapic
;
1442 if (apic
&& kvm_irqchip_in_kernel()) {
1443 kvm_put_apic_state(apic
, &kapic
);
1445 return kvm_vcpu_ioctl(env
, KVM_SET_LAPIC
, &kapic
);
1450 static int kvm_put_vcpu_events(CPUX86State
*env
, int level
)
1452 struct kvm_vcpu_events events
;
1454 if (!kvm_has_vcpu_events()) {
1458 events
.exception
.injected
= (env
->exception_injected
>= 0);
1459 events
.exception
.nr
= env
->exception_injected
;
1460 events
.exception
.has_error_code
= env
->has_error_code
;
1461 events
.exception
.error_code
= env
->error_code
;
1462 events
.exception
.pad
= 0;
1464 events
.interrupt
.injected
= (env
->interrupt_injected
>= 0);
1465 events
.interrupt
.nr
= env
->interrupt_injected
;
1466 events
.interrupt
.soft
= env
->soft_interrupt
;
1468 events
.nmi
.injected
= env
->nmi_injected
;
1469 events
.nmi
.pending
= env
->nmi_pending
;
1470 events
.nmi
.masked
= !!(env
->hflags2
& HF2_NMI_MASK
);
1473 events
.sipi_vector
= env
->sipi_vector
;
1476 if (level
>= KVM_PUT_RESET_STATE
) {
1478 KVM_VCPUEVENT_VALID_NMI_PENDING
| KVM_VCPUEVENT_VALID_SIPI_VECTOR
;
1481 return kvm_vcpu_ioctl(env
, KVM_SET_VCPU_EVENTS
, &events
);
1484 static int kvm_get_vcpu_events(CPUX86State
*env
)
1486 struct kvm_vcpu_events events
;
1489 if (!kvm_has_vcpu_events()) {
1493 ret
= kvm_vcpu_ioctl(env
, KVM_GET_VCPU_EVENTS
, &events
);
1497 env
->exception_injected
=
1498 events
.exception
.injected
? events
.exception
.nr
: -1;
1499 env
->has_error_code
= events
.exception
.has_error_code
;
1500 env
->error_code
= events
.exception
.error_code
;
1502 env
->interrupt_injected
=
1503 events
.interrupt
.injected
? events
.interrupt
.nr
: -1;
1504 env
->soft_interrupt
= events
.interrupt
.soft
;
1506 env
->nmi_injected
= events
.nmi
.injected
;
1507 env
->nmi_pending
= events
.nmi
.pending
;
1508 if (events
.nmi
.masked
) {
1509 env
->hflags2
|= HF2_NMI_MASK
;
1511 env
->hflags2
&= ~HF2_NMI_MASK
;
1514 env
->sipi_vector
= events
.sipi_vector
;
1519 static int kvm_guest_debug_workarounds(CPUX86State
*env
)
1522 unsigned long reinject_trap
= 0;
1524 if (!kvm_has_vcpu_events()) {
1525 if (env
->exception_injected
== 1) {
1526 reinject_trap
= KVM_GUESTDBG_INJECT_DB
;
1527 } else if (env
->exception_injected
== 3) {
1528 reinject_trap
= KVM_GUESTDBG_INJECT_BP
;
1530 env
->exception_injected
= -1;
1534 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1535 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1536 * by updating the debug state once again if single-stepping is on.
1537 * Another reason to call kvm_update_guest_debug here is a pending debug
1538 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1539 * reinject them via SET_GUEST_DEBUG.
1541 if (reinject_trap
||
1542 (!kvm_has_robust_singlestep() && env
->singlestep_enabled
)) {
1543 ret
= kvm_update_guest_debug(env
, reinject_trap
);
1548 static int kvm_put_debugregs(CPUX86State
*env
)
1550 struct kvm_debugregs dbgregs
;
1553 if (!kvm_has_debugregs()) {
1557 for (i
= 0; i
< 4; i
++) {
1558 dbgregs
.db
[i
] = env
->dr
[i
];
1560 dbgregs
.dr6
= env
->dr
[6];
1561 dbgregs
.dr7
= env
->dr
[7];
1564 return kvm_vcpu_ioctl(env
, KVM_SET_DEBUGREGS
, &dbgregs
);
1567 static int kvm_get_debugregs(CPUX86State
*env
)
1569 struct kvm_debugregs dbgregs
;
1572 if (!kvm_has_debugregs()) {
1576 ret
= kvm_vcpu_ioctl(env
, KVM_GET_DEBUGREGS
, &dbgregs
);
1580 for (i
= 0; i
< 4; i
++) {
1581 env
->dr
[i
] = dbgregs
.db
[i
];
1583 env
->dr
[4] = env
->dr
[6] = dbgregs
.dr6
;
1584 env
->dr
[5] = env
->dr
[7] = dbgregs
.dr7
;
1589 int kvm_arch_put_registers(CPUX86State
*env
, int level
)
1593 assert(cpu_is_stopped(env
) || qemu_cpu_is_self(env
));
1595 ret
= kvm_getput_regs(env
, 1);
1599 ret
= kvm_put_xsave(env
);
1603 ret
= kvm_put_xcrs(env
);
1607 ret
= kvm_put_sregs(env
);
1611 /* must be before kvm_put_msrs */
1612 ret
= kvm_inject_mce_oldstyle(env
);
1616 ret
= kvm_put_msrs(env
, level
);
1620 if (level
>= KVM_PUT_RESET_STATE
) {
1621 ret
= kvm_put_mp_state(env
);
1625 ret
= kvm_put_apic(env
);
1630 ret
= kvm_put_vcpu_events(env
, level
);
1634 ret
= kvm_put_debugregs(env
);
1639 ret
= kvm_guest_debug_workarounds(env
);
1646 int kvm_arch_get_registers(CPUX86State
*env
)
1650 assert(cpu_is_stopped(env
) || qemu_cpu_is_self(env
));
1652 ret
= kvm_getput_regs(env
, 0);
1656 ret
= kvm_get_xsave(env
);
1660 ret
= kvm_get_xcrs(env
);
1664 ret
= kvm_get_sregs(env
);
1668 ret
= kvm_get_msrs(env
);
1672 ret
= kvm_get_mp_state(env
);
1676 ret
= kvm_get_apic(env
);
1680 ret
= kvm_get_vcpu_events(env
);
1684 ret
= kvm_get_debugregs(env
);
1691 void kvm_arch_pre_run(CPUX86State
*env
, struct kvm_run
*run
)
1696 if (env
->interrupt_request
& CPU_INTERRUPT_NMI
) {
1697 env
->interrupt_request
&= ~CPU_INTERRUPT_NMI
;
1698 DPRINTF("injected NMI\n");
1699 ret
= kvm_vcpu_ioctl(env
, KVM_NMI
);
1701 fprintf(stderr
, "KVM: injection failed, NMI lost (%s)\n",
1706 if (!kvm_irqchip_in_kernel()) {
1707 /* Force the VCPU out of its inner loop to process any INIT requests
1708 * or pending TPR access reports. */
1709 if (env
->interrupt_request
&
1710 (CPU_INTERRUPT_INIT
| CPU_INTERRUPT_TPR
)) {
1711 env
->exit_request
= 1;
1714 /* Try to inject an interrupt if the guest can accept it */
1715 if (run
->ready_for_interrupt_injection
&&
1716 (env
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
1717 (env
->eflags
& IF_MASK
)) {
1720 env
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
1721 irq
= cpu_get_pic_interrupt(env
);
1723 struct kvm_interrupt intr
;
1726 DPRINTF("injected interrupt %d\n", irq
);
1727 ret
= kvm_vcpu_ioctl(env
, KVM_INTERRUPT
, &intr
);
1730 "KVM: injection failed, interrupt lost (%s)\n",
1736 /* If we have an interrupt but the guest is not ready to receive an
1737 * interrupt, request an interrupt window exit. This will
1738 * cause a return to userspace as soon as the guest is ready to
1739 * receive interrupts. */
1740 if ((env
->interrupt_request
& CPU_INTERRUPT_HARD
)) {
1741 run
->request_interrupt_window
= 1;
1743 run
->request_interrupt_window
= 0;
1746 DPRINTF("setting tpr\n");
1747 run
->cr8
= cpu_get_apic_tpr(env
->apic_state
);
1751 void kvm_arch_post_run(CPUX86State
*env
, struct kvm_run
*run
)
1754 env
->eflags
|= IF_MASK
;
1756 env
->eflags
&= ~IF_MASK
;
1758 cpu_set_apic_tpr(env
->apic_state
, run
->cr8
);
1759 cpu_set_apic_base(env
->apic_state
, run
->apic_base
);
1762 int kvm_arch_process_async_events(CPUX86State
*env
)
1764 X86CPU
*cpu
= x86_env_get_cpu(env
);
1766 if (env
->interrupt_request
& CPU_INTERRUPT_MCE
) {
1767 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
1768 assert(env
->mcg_cap
);
1770 env
->interrupt_request
&= ~CPU_INTERRUPT_MCE
;
1772 kvm_cpu_synchronize_state(env
);
1774 if (env
->exception_injected
== EXCP08_DBLE
) {
1775 /* this means triple fault */
1776 qemu_system_reset_request();
1777 env
->exit_request
= 1;
1780 env
->exception_injected
= EXCP12_MCHK
;
1781 env
->has_error_code
= 0;
1784 if (kvm_irqchip_in_kernel() && env
->mp_state
== KVM_MP_STATE_HALTED
) {
1785 env
->mp_state
= KVM_MP_STATE_RUNNABLE
;
1789 if (kvm_irqchip_in_kernel()) {
1793 if (env
->interrupt_request
& CPU_INTERRUPT_POLL
) {
1794 env
->interrupt_request
&= ~CPU_INTERRUPT_POLL
;
1795 apic_poll_irq(env
->apic_state
);
1797 if (((env
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
1798 (env
->eflags
& IF_MASK
)) ||
1799 (env
->interrupt_request
& CPU_INTERRUPT_NMI
)) {
1802 if (env
->interrupt_request
& CPU_INTERRUPT_INIT
) {
1803 kvm_cpu_synchronize_state(env
);
1806 if (env
->interrupt_request
& CPU_INTERRUPT_SIPI
) {
1807 kvm_cpu_synchronize_state(env
);
1810 if (env
->interrupt_request
& CPU_INTERRUPT_TPR
) {
1811 env
->interrupt_request
&= ~CPU_INTERRUPT_TPR
;
1812 kvm_cpu_synchronize_state(env
);
1813 apic_handle_tpr_access_report(env
->apic_state
, env
->eip
,
1814 env
->tpr_access_type
);
1820 static int kvm_handle_halt(CPUX86State
*env
)
1822 if (!((env
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
1823 (env
->eflags
& IF_MASK
)) &&
1824 !(env
->interrupt_request
& CPU_INTERRUPT_NMI
)) {
1832 static int kvm_handle_tpr_access(CPUX86State
*env
)
1834 struct kvm_run
*run
= env
->kvm_run
;
1836 apic_handle_tpr_access_report(env
->apic_state
, run
->tpr_access
.rip
,
1837 run
->tpr_access
.is_write
? TPR_ACCESS_WRITE
1842 int kvm_arch_insert_sw_breakpoint(CPUX86State
*env
, struct kvm_sw_breakpoint
*bp
)
1844 static const uint8_t int3
= 0xcc;
1846 if (cpu_memory_rw_debug(env
, bp
->pc
, (uint8_t *)&bp
->saved_insn
, 1, 0) ||
1847 cpu_memory_rw_debug(env
, bp
->pc
, (uint8_t *)&int3
, 1, 1)) {
1853 int kvm_arch_remove_sw_breakpoint(CPUX86State
*env
, struct kvm_sw_breakpoint
*bp
)
1857 if (cpu_memory_rw_debug(env
, bp
->pc
, &int3
, 1, 0) || int3
!= 0xcc ||
1858 cpu_memory_rw_debug(env
, bp
->pc
, (uint8_t *)&bp
->saved_insn
, 1, 1)) {
1870 static int nb_hw_breakpoint
;
1872 static int find_hw_breakpoint(target_ulong addr
, int len
, int type
)
1876 for (n
= 0; n
< nb_hw_breakpoint
; n
++) {
1877 if (hw_breakpoint
[n
].addr
== addr
&& hw_breakpoint
[n
].type
== type
&&
1878 (hw_breakpoint
[n
].len
== len
|| len
== -1)) {
1885 int kvm_arch_insert_hw_breakpoint(target_ulong addr
,
1886 target_ulong len
, int type
)
1889 case GDB_BREAKPOINT_HW
:
1892 case GDB_WATCHPOINT_WRITE
:
1893 case GDB_WATCHPOINT_ACCESS
:
1900 if (addr
& (len
- 1)) {
1912 if (nb_hw_breakpoint
== 4) {
1915 if (find_hw_breakpoint(addr
, len
, type
) >= 0) {
1918 hw_breakpoint
[nb_hw_breakpoint
].addr
= addr
;
1919 hw_breakpoint
[nb_hw_breakpoint
].len
= len
;
1920 hw_breakpoint
[nb_hw_breakpoint
].type
= type
;
1926 int kvm_arch_remove_hw_breakpoint(target_ulong addr
,
1927 target_ulong len
, int type
)
1931 n
= find_hw_breakpoint(addr
, (type
== GDB_BREAKPOINT_HW
) ? 1 : len
, type
);
1936 hw_breakpoint
[n
] = hw_breakpoint
[nb_hw_breakpoint
];
1941 void kvm_arch_remove_all_hw_breakpoints(void)
1943 nb_hw_breakpoint
= 0;
1946 static CPUWatchpoint hw_watchpoint
;
1948 static int kvm_handle_debug(struct kvm_debug_exit_arch
*arch_info
)
1953 if (arch_info
->exception
== 1) {
1954 if (arch_info
->dr6
& (1 << 14)) {
1955 if (cpu_single_env
->singlestep_enabled
) {
1959 for (n
= 0; n
< 4; n
++) {
1960 if (arch_info
->dr6
& (1 << n
)) {
1961 switch ((arch_info
->dr7
>> (16 + n
*4)) & 0x3) {
1967 cpu_single_env
->watchpoint_hit
= &hw_watchpoint
;
1968 hw_watchpoint
.vaddr
= hw_breakpoint
[n
].addr
;
1969 hw_watchpoint
.flags
= BP_MEM_WRITE
;
1973 cpu_single_env
->watchpoint_hit
= &hw_watchpoint
;
1974 hw_watchpoint
.vaddr
= hw_breakpoint
[n
].addr
;
1975 hw_watchpoint
.flags
= BP_MEM_ACCESS
;
1981 } else if (kvm_find_sw_breakpoint(cpu_single_env
, arch_info
->pc
)) {
1985 cpu_synchronize_state(cpu_single_env
);
1986 assert(cpu_single_env
->exception_injected
== -1);
1989 cpu_single_env
->exception_injected
= arch_info
->exception
;
1990 cpu_single_env
->has_error_code
= 0;
1996 void kvm_arch_update_guest_debug(CPUX86State
*env
, struct kvm_guest_debug
*dbg
)
1998 const uint8_t type_code
[] = {
1999 [GDB_BREAKPOINT_HW
] = 0x0,
2000 [GDB_WATCHPOINT_WRITE
] = 0x1,
2001 [GDB_WATCHPOINT_ACCESS
] = 0x3
2003 const uint8_t len_code
[] = {
2004 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
2008 if (kvm_sw_breakpoints_active(env
)) {
2009 dbg
->control
|= KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
;
2011 if (nb_hw_breakpoint
> 0) {
2012 dbg
->control
|= KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_HW_BP
;
2013 dbg
->arch
.debugreg
[7] = 0x0600;
2014 for (n
= 0; n
< nb_hw_breakpoint
; n
++) {
2015 dbg
->arch
.debugreg
[n
] = hw_breakpoint
[n
].addr
;
2016 dbg
->arch
.debugreg
[7] |= (2 << (n
* 2)) |
2017 (type_code
[hw_breakpoint
[n
].type
] << (16 + n
*4)) |
2018 ((uint32_t)len_code
[hw_breakpoint
[n
].len
] << (18 + n
*4));
2023 static bool host_supports_vmx(void)
2025 uint32_t ecx
, unused
;
2027 host_cpuid(1, 0, &unused
, &unused
, &ecx
, &unused
);
2028 return ecx
& CPUID_EXT_VMX
;
2031 #define VMX_INVALID_GUEST_STATE 0x80000021
2033 int kvm_arch_handle_exit(CPUX86State
*env
, struct kvm_run
*run
)
2038 switch (run
->exit_reason
) {
2040 DPRINTF("handle_hlt\n");
2041 ret
= kvm_handle_halt(env
);
2043 case KVM_EXIT_SET_TPR
:
2046 case KVM_EXIT_TPR_ACCESS
:
2047 ret
= kvm_handle_tpr_access(env
);
2049 case KVM_EXIT_FAIL_ENTRY
:
2050 code
= run
->fail_entry
.hardware_entry_failure_reason
;
2051 fprintf(stderr
, "KVM: entry failed, hardware error 0x%" PRIx64
"\n",
2053 if (host_supports_vmx() && code
== VMX_INVALID_GUEST_STATE
) {
2055 "\nIf you're running a guest on an Intel machine without "
2056 "unrestricted mode\n"
2057 "support, the failure can be most likely due to the guest "
2058 "entering an invalid\n"
2059 "state for Intel VT. For example, the guest maybe running "
2060 "in big real mode\n"
2061 "which is not supported on less recent Intel processors."
2066 case KVM_EXIT_EXCEPTION
:
2067 fprintf(stderr
, "KVM: exception %d exit (error code 0x%x)\n",
2068 run
->ex
.exception
, run
->ex
.error_code
);
2071 case KVM_EXIT_DEBUG
:
2072 DPRINTF("kvm_exit_debug\n");
2073 ret
= kvm_handle_debug(&run
->debug
.arch
);
2076 fprintf(stderr
, "KVM: unknown exit reason %d\n", run
->exit_reason
);
2084 bool kvm_arch_stop_on_emulation_error(CPUX86State
*env
)
2086 kvm_cpu_synchronize_state(env
);
2087 return !(env
->cr
[0] & CR0_PE_MASK
) ||
2088 ((env
->segs
[R_CS
].selector
& 3) != 3);
2091 void kvm_arch_init_irq_routing(KVMState
*s
)
2093 if (!kvm_check_extension(s
, KVM_CAP_IRQ_ROUTING
)) {
2094 /* If kernel can't do irq routing, interrupt source
2095 * override 0->2 cannot be set up as required by HPET.
2096 * So we have to disable it.
2100 /* We know at this point that we're using the in-kernel
2101 * irqchip, so we can use irqfds, and on x86 we know
2102 * we can use msi via irqfd and GSI routing.
2104 kvm_irqfds_allowed
= true;
2105 kvm_msi_via_irqfd_allowed
= true;
2106 kvm_gsi_routing_allowed
= true;
2109 /* Classic KVM device assignment interface. Will remain x86 only. */
2110 int kvm_device_pci_assign(KVMState
*s
, PCIHostDeviceAddress
*dev_addr
,
2111 uint32_t flags
, uint32_t *dev_id
)
2113 struct kvm_assigned_pci_dev dev_data
= {
2114 .segnr
= dev_addr
->domain
,
2115 .busnr
= dev_addr
->bus
,
2116 .devfn
= PCI_DEVFN(dev_addr
->slot
, dev_addr
->function
),
2121 dev_data
.assigned_dev_id
=
2122 (dev_addr
->domain
<< 16) | (dev_addr
->bus
<< 8) | dev_data
.devfn
;
2124 ret
= kvm_vm_ioctl(s
, KVM_ASSIGN_PCI_DEVICE
, &dev_data
);
2129 *dev_id
= dev_data
.assigned_dev_id
;
2134 int kvm_device_pci_deassign(KVMState
*s
, uint32_t dev_id
)
2136 struct kvm_assigned_pci_dev dev_data
= {
2137 .assigned_dev_id
= dev_id
,
2140 return kvm_vm_ioctl(s
, KVM_DEASSIGN_PCI_DEVICE
, &dev_data
);
2143 static int kvm_assign_irq_internal(KVMState
*s
, uint32_t dev_id
,
2144 uint32_t irq_type
, uint32_t guest_irq
)
2146 struct kvm_assigned_irq assigned_irq
= {
2147 .assigned_dev_id
= dev_id
,
2148 .guest_irq
= guest_irq
,
2152 if (kvm_check_extension(s
, KVM_CAP_ASSIGN_DEV_IRQ
)) {
2153 return kvm_vm_ioctl(s
, KVM_ASSIGN_DEV_IRQ
, &assigned_irq
);
2155 return kvm_vm_ioctl(s
, KVM_ASSIGN_IRQ
, &assigned_irq
);
2159 int kvm_device_intx_assign(KVMState
*s
, uint32_t dev_id
, bool use_host_msi
,
2162 uint32_t irq_type
= KVM_DEV_IRQ_GUEST_INTX
|
2163 (use_host_msi
? KVM_DEV_IRQ_HOST_MSI
: KVM_DEV_IRQ_HOST_INTX
);
2165 return kvm_assign_irq_internal(s
, dev_id
, irq_type
, guest_irq
);
2168 int kvm_device_intx_set_mask(KVMState
*s
, uint32_t dev_id
, bool masked
)
2170 struct kvm_assigned_pci_dev dev_data
= {
2171 .assigned_dev_id
= dev_id
,
2172 .flags
= masked
? KVM_DEV_ASSIGN_MASK_INTX
: 0,
2175 return kvm_vm_ioctl(s
, KVM_ASSIGN_SET_INTX_MASK
, &dev_data
);
2178 static int kvm_deassign_irq_internal(KVMState
*s
, uint32_t dev_id
,
2181 struct kvm_assigned_irq assigned_irq
= {
2182 .assigned_dev_id
= dev_id
,
2186 return kvm_vm_ioctl(s
, KVM_DEASSIGN_DEV_IRQ
, &assigned_irq
);
2189 int kvm_device_intx_deassign(KVMState
*s
, uint32_t dev_id
, bool use_host_msi
)
2191 return kvm_deassign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_GUEST_INTX
|
2192 (use_host_msi
? KVM_DEV_IRQ_HOST_MSI
: KVM_DEV_IRQ_HOST_INTX
));
2195 int kvm_device_msi_assign(KVMState
*s
, uint32_t dev_id
, int virq
)
2197 return kvm_assign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_HOST_MSI
|
2198 KVM_DEV_IRQ_GUEST_MSI
, virq
);
2201 int kvm_device_msi_deassign(KVMState
*s
, uint32_t dev_id
)
2203 return kvm_deassign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_GUEST_MSI
|
2204 KVM_DEV_IRQ_HOST_MSI
);
2207 bool kvm_device_msix_supported(KVMState
*s
)
2209 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
2210 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
2211 return kvm_vm_ioctl(s
, KVM_ASSIGN_SET_MSIX_NR
, NULL
) == -EFAULT
;
2214 int kvm_device_msix_init_vectors(KVMState
*s
, uint32_t dev_id
,
2215 uint32_t nr_vectors
)
2217 struct kvm_assigned_msix_nr msix_nr
= {
2218 .assigned_dev_id
= dev_id
,
2219 .entry_nr
= nr_vectors
,
2222 return kvm_vm_ioctl(s
, KVM_ASSIGN_SET_MSIX_NR
, &msix_nr
);
2225 int kvm_device_msix_set_vector(KVMState
*s
, uint32_t dev_id
, uint32_t vector
,
2228 struct kvm_assigned_msix_entry msix_entry
= {
2229 .assigned_dev_id
= dev_id
,
2234 return kvm_vm_ioctl(s
, KVM_ASSIGN_SET_MSIX_ENTRY
, &msix_entry
);
2237 int kvm_device_msix_assign(KVMState
*s
, uint32_t dev_id
)
2239 return kvm_assign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_HOST_MSIX
|
2240 KVM_DEV_IRQ_GUEST_MSIX
, 0);
2243 int kvm_device_msix_deassign(KVMState
*s
, uint32_t dev_id
)
2245 return kvm_deassign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_GUEST_MSIX
|
2246 KVM_DEV_IRQ_HOST_MSIX
);