2 * ARM virtual CPU header
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
24 #include "kvm-consts.h"
26 #if defined(TARGET_AARCH64)
27 /* AArch64 definitions */
28 # define TARGET_LONG_BITS 64
29 # define ELF_MACHINE EM_AARCH64
31 # define TARGET_LONG_BITS 32
32 # define ELF_MACHINE EM_ARM
35 #define CPUArchState struct CPUARMState
37 #include "qemu-common.h"
38 #include "exec/cpu-defs.h"
40 #include "fpu/softfloat.h"
42 #define TARGET_HAS_ICE 1
44 #define EXCP_UDEF 1 /* undefined instruction */
45 #define EXCP_SWI 2 /* software interrupt */
46 #define EXCP_PREFETCH_ABORT 3
47 #define EXCP_DATA_ABORT 4
51 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */
52 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */
55 #define ARMV7M_EXCP_RESET 1
56 #define ARMV7M_EXCP_NMI 2
57 #define ARMV7M_EXCP_HARD 3
58 #define ARMV7M_EXCP_MEM 4
59 #define ARMV7M_EXCP_BUS 5
60 #define ARMV7M_EXCP_USAGE 6
61 #define ARMV7M_EXCP_SVC 11
62 #define ARMV7M_EXCP_DEBUG 12
63 #define ARMV7M_EXCP_PENDSV 14
64 #define ARMV7M_EXCP_SYSTICK 15
66 /* ARM-specific interrupt pending bits. */
67 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
69 /* The usual mapping for an AArch64 system register to its AArch32
70 * counterpart is for the 32 bit world to have access to the lower
71 * half only (with writes leaving the upper half untouched). It's
72 * therefore useful to be able to pass TCG the offset of the least
73 * significant half of a uint64_t struct member.
75 #ifdef HOST_WORDS_BIGENDIAN
76 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t))
78 #define offsetoflow32(S, M) offsetof(S, M)
81 /* Meanings of the ARMCPU object's two inbound GPIO lines */
85 typedef void ARMWriteCPFunc(void *opaque
, int cp_info
,
86 int srcreg
, int operand
, uint32_t value
);
87 typedef uint32_t ARMReadCPFunc(void *opaque
, int cp_info
,
88 int dstreg
, int operand
);
92 #define NB_MMU_MODES 2
94 /* We currently assume float and double are IEEE single and double
95 precision respectively.
96 Doing runtime conversions is tricky because VFP registers may contain
97 integer values (eg. as the result of a FTOSI instruction).
98 s<2n> maps to the least significant half of d<n>
99 s<2n+1> maps to the most significant half of d<n>
102 /* CPU state for each instance of a generic timer (in cp15 c14) */
103 typedef struct ARMGenericTimer
{
104 uint64_t cval
; /* Timer CompareValue register */
105 uint32_t ctl
; /* Timer Control register */
108 #define GTIMER_PHYS 0
109 #define GTIMER_VIRT 1
110 #define NUM_GTIMERS 2
112 /* Scale factor for generic timers, ie number of ns per tick.
113 * This gives a 62.5MHz timer.
115 #define GTIMER_SCALE 16
117 typedef struct CPUARMState
{
118 /* Regs for current mode. */
121 /* 32/64 switch only happens when taking and returning from
122 * exceptions so the overlap semantics are taken care of then
123 * instead of having a complicated union.
125 /* Regs for A64 mode. */
128 /* PSTATE isn't an architectural register for ARMv8. However, it is
129 * convenient for us to assemble the underlying state into a 32 bit format
130 * identical to the architectural format used for the SPSR. (This is also
131 * what the Linux kernel's 'pstate' field in signal handlers and KVM's
132 * 'pstate' register are.) Of the PSTATE bits:
133 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same
134 * semantics as for AArch32, as described in the comments on each field)
135 * nRW (also known as M[4]) is kept, inverted, in env->aarch64
136 * all other bits are stored in their correct places in env->pstate
139 uint32_t aarch64
; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */
141 /* Frequently accessed CPSR bits are stored separately for efficiency.
142 This contains all the other bits. Use cpsr_{read,write} to access
144 uint32_t uncached_cpsr
;
147 /* Banked registers. */
148 uint32_t banked_spsr
[6];
149 uint32_t banked_r13
[6];
150 uint32_t banked_r14
[6];
152 /* These hold r8-r12. */
153 uint32_t usr_regs
[5];
154 uint32_t fiq_regs
[5];
156 /* cpsr flag cache for faster execution */
157 uint32_t CF
; /* 0 or 1 */
158 uint32_t VF
; /* V is the bit 31. All other bits are undefined */
159 uint32_t NF
; /* N is bit 31. All other bits are undefined. */
160 uint32_t ZF
; /* Z set if zero. */
161 uint32_t QF
; /* 0 or 1 */
162 uint32_t GE
; /* cpsr[19:16] */
163 uint32_t thumb
; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
164 uint32_t condexec_bits
; /* IT bits. cpsr[15:10,26:25]. */
166 /* System control coprocessor (cp15) */
169 uint32_t c0_cssel
; /* Cache size selection. */
170 uint32_t c1_sys
; /* System control register. */
171 uint32_t c1_coproc
; /* Coprocessor access register. */
172 uint32_t c1_xscaleauxcr
; /* XScale auxiliary control register. */
173 uint32_t c1_scr
; /* secure config register. */
174 uint32_t c2_base0
; /* MMU translation table base 0. */
175 uint32_t c2_base0_hi
; /* MMU translation table base 0, high 32 bits */
176 uint32_t c2_base1
; /* MMU translation table base 0. */
177 uint32_t c2_base1_hi
; /* MMU translation table base 1, high 32 bits */
178 uint32_t c2_control
; /* MMU translation table base control. */
179 uint32_t c2_mask
; /* MMU translation table base selection mask. */
180 uint32_t c2_base_mask
; /* MMU translation table base 0 mask. */
181 uint32_t c2_data
; /* MPU data cachable bits. */
182 uint32_t c2_insn
; /* MPU instruction cachable bits. */
183 uint32_t c3
; /* MMU domain access control register
184 MPU write buffer control. */
185 uint32_t c5_insn
; /* Fault status registers. */
187 uint32_t c6_region
[8]; /* MPU base/size registers. */
188 uint32_t c6_insn
; /* Fault address registers. */
190 uint32_t c7_par
; /* Translation result. */
191 uint32_t c7_par_hi
; /* Translation result, high 32 bits */
192 uint32_t c9_insn
; /* Cache lockdown registers. */
194 uint32_t c9_pmcr
; /* performance monitor control register */
195 uint32_t c9_pmcnten
; /* perf monitor counter enables */
196 uint32_t c9_pmovsr
; /* perf monitor overflow status */
197 uint32_t c9_pmxevtyper
; /* perf monitor event type */
198 uint32_t c9_pmuserenr
; /* perf monitor user enable */
199 uint32_t c9_pminten
; /* perf monitor interrupt enables */
200 uint32_t c12_vbar
; /* vector base address register */
201 uint32_t c13_fcse
; /* FCSE PID. */
202 uint32_t c13_context
; /* Context ID. */
203 uint64_t tpidr_el0
; /* User RW Thread register. */
204 uint64_t tpidrro_el0
; /* User RO Thread register. */
205 uint64_t tpidr_el1
; /* Privileged Thread register. */
206 uint32_t c14_cntfrq
; /* Counter Frequency register */
207 uint32_t c14_cntkctl
; /* Timer Control register */
208 ARMGenericTimer c14_timer
[NUM_GTIMERS
];
209 uint32_t c15_cpar
; /* XScale Coprocessor Access Register */
210 uint32_t c15_ticonfig
; /* TI925T configuration byte. */
211 uint32_t c15_i_max
; /* Maximum D-cache dirty line index. */
212 uint32_t c15_i_min
; /* Minimum D-cache dirty line index. */
213 uint32_t c15_threadid
; /* TI debugger thread-ID. */
214 uint32_t c15_config_base_address
; /* SCU base address. */
215 uint32_t c15_diagnostic
; /* diagnostic register */
216 uint32_t c15_power_diagnostic
;
217 uint32_t c15_power_control
; /* power control */
220 /* System registers (AArch64) */
232 int pending_exception
;
235 /* Thumb-2 EE state. */
239 /* VFP coprocessor state. */
241 /* VFP/Neon register state. Note that the mapping between S, D and Q
242 * views of the register bank differs between AArch64 and AArch32:
244 * Qn = regs[2n+1]:regs[2n]
246 * Sn = regs[n/2] bits 31..0 for even n, and bits 63..32 for odd n
247 * (and regs[32] to regs[63] are inaccessible)
249 * Qn = regs[2n+1]:regs[2n]
251 * Sn = regs[2n] bits 31..0
252 * This corresponds to the architecturally defined mapping between
253 * the two execution states, and means we do not need to explicitly
254 * map these registers when changing states.
259 /* We store these fpcsr fields separately for convenience. */
263 /* scratch space when Tn are not sufficient. */
266 /* fp_status is the "normal" fp status. standard_fp_status retains
267 * values corresponding to the ARM "Standard FPSCR Value", ie
268 * default-NaN, flush-to-zero, round-to-nearest and is used by
269 * any operations (generally Neon) which the architecture defines
270 * as controlled by the standard FPSCR value rather than the FPSCR.
272 * To avoid having to transfer exception bits around, we simply
273 * say that the FPSCR cumulative exception flags are the logical
274 * OR of the flags in the two fp statuses. This relies on the
275 * only thing which needs to read the exception flags being
276 * an explicit FPSCR read.
278 float_status fp_status
;
279 float_status standard_fp_status
;
281 uint64_t exclusive_addr
;
282 uint64_t exclusive_val
;
283 uint64_t exclusive_high
;
284 #if defined(CONFIG_USER_ONLY)
285 uint64_t exclusive_test
;
286 uint32_t exclusive_info
;
289 /* iwMMXt coprocessor state. */
297 /* For mixed endian mode. */
300 #if defined(CONFIG_USER_ONLY)
301 /* For usermode syscall translation. */
307 /* These fields after the common ones so they are preserved on reset. */
309 /* Internal CPU feature flags. */
313 const struct arm_boot_info
*boot_info
;
318 ARMCPU
*cpu_arm_init(const char *cpu_model
);
319 void arm_translate_init(void);
320 void arm_cpu_register_gdb_regs_for_features(ARMCPU
*cpu
);
321 int cpu_arm_exec(CPUARMState
*s
);
322 int bank_number(int mode
);
323 void switch_mode(CPUARMState
*, int);
324 uint32_t do_arm_semihosting(CPUARMState
*env
);
326 static inline bool is_a64(CPUARMState
*env
)
331 /* you can call this signal handler from your SIGBUS and SIGSEGV
332 signal handlers to inform the virtual CPU of exceptions. non zero
333 is returned if the signal was handled by the virtual CPU. */
334 int cpu_arm_signal_handler(int host_signum
, void *pinfo
,
336 int cpu_arm_handle_mmu_fault (CPUARMState
*env
, target_ulong address
, int rw
,
338 #define cpu_handle_mmu_fault cpu_arm_handle_mmu_fault
340 #define CPSR_M (0x1fU)
341 #define CPSR_T (1U << 5)
342 #define CPSR_F (1U << 6)
343 #define CPSR_I (1U << 7)
344 #define CPSR_A (1U << 8)
345 #define CPSR_E (1U << 9)
346 #define CPSR_IT_2_7 (0xfc00U)
347 #define CPSR_GE (0xfU << 16)
348 #define CPSR_RESERVED (0xfU << 20)
349 #define CPSR_J (1U << 24)
350 #define CPSR_IT_0_1 (3U << 25)
351 #define CPSR_Q (1U << 27)
352 #define CPSR_V (1U << 28)
353 #define CPSR_C (1U << 29)
354 #define CPSR_Z (1U << 30)
355 #define CPSR_N (1U << 31)
356 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
358 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
359 #define CACHED_CPSR_BITS (CPSR_T | CPSR_GE | CPSR_IT | CPSR_Q | CPSR_NZCV)
360 /* Bits writable in user mode. */
361 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
362 /* Execution state bits. MRS read as zero, MSR writes ignored. */
363 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J)
365 /* Bit definitions for ARMv8 SPSR (PSTATE) format.
366 * Only these are valid when in AArch64 mode; in
367 * AArch32 mode SPSRs are basically CPSR-format.
369 #define PSTATE_M (0xFU)
370 #define PSTATE_nRW (1U << 4)
371 #define PSTATE_F (1U << 6)
372 #define PSTATE_I (1U << 7)
373 #define PSTATE_A (1U << 8)
374 #define PSTATE_D (1U << 9)
375 #define PSTATE_IL (1U << 20)
376 #define PSTATE_SS (1U << 21)
377 #define PSTATE_V (1U << 28)
378 #define PSTATE_C (1U << 29)
379 #define PSTATE_Z (1U << 30)
380 #define PSTATE_N (1U << 31)
381 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V)
382 #define CACHED_PSTATE_BITS (PSTATE_NZCV)
383 /* Mode values for AArch64 */
384 #define PSTATE_MODE_EL3h 13
385 #define PSTATE_MODE_EL3t 12
386 #define PSTATE_MODE_EL2h 9
387 #define PSTATE_MODE_EL2t 8
388 #define PSTATE_MODE_EL1h 5
389 #define PSTATE_MODE_EL1t 4
390 #define PSTATE_MODE_EL0t 0
392 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit
393 * interprocessing, so we don't attempt to sync with the cpsr state used by
394 * the 32 bit decoder.
396 static inline uint32_t pstate_read(CPUARMState
*env
)
401 return (env
->NF
& 0x80000000) | (ZF
<< 30)
402 | (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3)
406 static inline void pstate_write(CPUARMState
*env
, uint32_t val
)
408 env
->ZF
= (~val
) & PSTATE_Z
;
410 env
->CF
= (val
>> 29) & 1;
411 env
->VF
= (val
<< 3) & 0x80000000;
412 env
->pstate
= val
& ~CACHED_PSTATE_BITS
;
415 /* Return the current CPSR value. */
416 uint32_t cpsr_read(CPUARMState
*env
);
417 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear. */
418 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
);
420 /* Return the current xPSR value. */
421 static inline uint32_t xpsr_read(CPUARMState
*env
)
425 return (env
->NF
& 0x80000000) | (ZF
<< 30)
426 | (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
427 | (env
->thumb
<< 24) | ((env
->condexec_bits
& 3) << 25)
428 | ((env
->condexec_bits
& 0xfc) << 8)
429 | env
->v7m
.exception
;
432 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */
433 static inline void xpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
435 if (mask
& CPSR_NZCV
) {
436 env
->ZF
= (~val
) & CPSR_Z
;
438 env
->CF
= (val
>> 29) & 1;
439 env
->VF
= (val
<< 3) & 0x80000000;
442 env
->QF
= ((val
& CPSR_Q
) != 0);
443 if (mask
& (1 << 24))
444 env
->thumb
= ((val
& (1 << 24)) != 0);
445 if (mask
& CPSR_IT_0_1
) {
446 env
->condexec_bits
&= ~3;
447 env
->condexec_bits
|= (val
>> 25) & 3;
449 if (mask
& CPSR_IT_2_7
) {
450 env
->condexec_bits
&= 3;
451 env
->condexec_bits
|= (val
>> 8) & 0xfc;
454 env
->v7m
.exception
= val
& 0x1ff;
458 /* Return the current FPSCR value. */
459 uint32_t vfp_get_fpscr(CPUARMState
*env
);
460 void vfp_set_fpscr(CPUARMState
*env
, uint32_t val
);
462 /* For A64 the FPSCR is split into two logically distinct registers,
463 * FPCR and FPSR. However since they still use non-overlapping bits
464 * we store the underlying state in fpscr and just mask on read/write.
466 #define FPSR_MASK 0xf800009f
467 #define FPCR_MASK 0x07f79f00
468 static inline uint32_t vfp_get_fpsr(CPUARMState
*env
)
470 return vfp_get_fpscr(env
) & FPSR_MASK
;
473 static inline void vfp_set_fpsr(CPUARMState
*env
, uint32_t val
)
475 uint32_t new_fpscr
= (vfp_get_fpscr(env
) & ~FPSR_MASK
) | (val
& FPSR_MASK
);
476 vfp_set_fpscr(env
, new_fpscr
);
479 static inline uint32_t vfp_get_fpcr(CPUARMState
*env
)
481 return vfp_get_fpscr(env
) & FPCR_MASK
;
484 static inline void vfp_set_fpcr(CPUARMState
*env
, uint32_t val
)
486 uint32_t new_fpscr
= (vfp_get_fpscr(env
) & ~FPCR_MASK
) | (val
& FPCR_MASK
);
487 vfp_set_fpscr(env
, new_fpscr
);
490 enum arm_fprounding
{
500 ARM_CPU_MODE_USR
= 0x10,
501 ARM_CPU_MODE_FIQ
= 0x11,
502 ARM_CPU_MODE_IRQ
= 0x12,
503 ARM_CPU_MODE_SVC
= 0x13,
504 ARM_CPU_MODE_ABT
= 0x17,
505 ARM_CPU_MODE_UND
= 0x1b,
506 ARM_CPU_MODE_SYS
= 0x1f
509 /* VFP system registers. */
510 #define ARM_VFP_FPSID 0
511 #define ARM_VFP_FPSCR 1
512 #define ARM_VFP_MVFR1 6
513 #define ARM_VFP_MVFR0 7
514 #define ARM_VFP_FPEXC 8
515 #define ARM_VFP_FPINST 9
516 #define ARM_VFP_FPINST2 10
518 /* iwMMXt coprocessor control registers. */
519 #define ARM_IWMMXT_wCID 0
520 #define ARM_IWMMXT_wCon 1
521 #define ARM_IWMMXT_wCSSF 2
522 #define ARM_IWMMXT_wCASF 3
523 #define ARM_IWMMXT_wCGR0 8
524 #define ARM_IWMMXT_wCGR1 9
525 #define ARM_IWMMXT_wCGR2 10
526 #define ARM_IWMMXT_wCGR3 11
528 /* If adding a feature bit which corresponds to a Linux ELF
529 * HWCAP bit, remember to update the feature-bit-to-hwcap
530 * mapping in linux-user/elfload.c:get_elf_hwcap().
534 ARM_FEATURE_AUXCR
, /* ARM1026 Auxiliary control register. */
535 ARM_FEATURE_XSCALE
, /* Intel XScale extensions. */
536 ARM_FEATURE_IWMMXT
, /* Intel iwMMXt extension. */
541 ARM_FEATURE_MPU
, /* Only has Memory Protection Unit, not full MMU. */
543 ARM_FEATURE_VFP_FP16
,
545 ARM_FEATURE_THUMB_DIV
, /* divide supported in Thumb encoding */
546 ARM_FEATURE_M
, /* Microcontroller profile. */
547 ARM_FEATURE_OMAPCP
, /* OMAP specific CP15 ops handling. */
548 ARM_FEATURE_THUMB2EE
,
549 ARM_FEATURE_V7MP
, /* v7 Multiprocessing Extensions */
552 ARM_FEATURE_STRONGARM
,
553 ARM_FEATURE_VAPA
, /* cp15 VA to PA lookups */
554 ARM_FEATURE_ARM_DIV
, /* divide supported in ARM encoding */
555 ARM_FEATURE_VFP4
, /* VFPv4 (implies that NEON is v2) */
556 ARM_FEATURE_GENERIC_TIMER
,
557 ARM_FEATURE_MVFR
, /* Media and VFP Feature Registers 0 and 1 */
558 ARM_FEATURE_DUMMY_C15_REGS
, /* RAZ/WI all of cp15 crn=15 */
559 ARM_FEATURE_CACHE_TEST_CLEAN
, /* 926/1026 style test-and-clean ops */
560 ARM_FEATURE_CACHE_DIRTY_REG
, /* 1136/1176 cache dirty status register */
561 ARM_FEATURE_CACHE_BLOCK_OPS
, /* v6 optional cache block operations */
562 ARM_FEATURE_MPIDR
, /* has cp15 MPIDR */
563 ARM_FEATURE_PXN
, /* has Privileged Execute Never bit */
564 ARM_FEATURE_LPAE
, /* has Large Physical Address Extension */
566 ARM_FEATURE_AARCH64
, /* supports 64 bit mode */
567 ARM_FEATURE_V8_AES
, /* implements AES part of v8 Crypto Extensions */
568 ARM_FEATURE_CBAR
, /* has cp15 CBAR */
571 static inline int arm_feature(CPUARMState
*env
, int feature
)
573 return (env
->features
& (1ULL << feature
)) != 0;
576 void arm_cpu_list(FILE *f
, fprintf_function cpu_fprintf
);
578 /* Interface between CPU and Interrupt controller. */
579 void armv7m_nvic_set_pending(void *opaque
, int irq
);
580 int armv7m_nvic_acknowledge_irq(void *opaque
);
581 void armv7m_nvic_complete_irq(void *opaque
, int irq
);
583 /* Interface for defining coprocessor registers.
584 * Registers are defined in tables of arm_cp_reginfo structs
585 * which are passed to define_arm_cp_regs().
588 /* When looking up a coprocessor register we look for it
589 * via an integer which encodes all of:
591 * Crn, Crm, opc1, opc2 fields
592 * 32 or 64 bit register (ie is it accessed via MRC/MCR
594 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
595 * (In this case crn and opc2 should be zero.)
596 * For AArch64, there is no 32/64 bit size distinction;
597 * instead all registers have a 2 bit op0, 3 bit op1 and op2,
598 * and 4 bit CRn and CRm. The encoding patterns are chosen
599 * to be easy to convert to and from the KVM encodings, and also
600 * so that the hashtable can contain both AArch32 and AArch64
601 * registers (to allow for interprocessing where we might run
602 * 32 bit code on a 64 bit core).
604 /* This bit is private to our hashtable cpreg; in KVM register
605 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64
606 * in the upper bits of the 64 bit ID.
608 #define CP_REG_AA64_SHIFT 28
609 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
611 #define ENCODE_CP_REG(cp, is64, crn, crm, opc1, opc2) \
612 (((cp) << 16) | ((is64) << 15) | ((crn) << 11) | \
613 ((crm) << 7) | ((opc1) << 3) | (opc2))
615 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
616 (CP_REG_AA64_MASK | \
617 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \
618 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \
619 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \
620 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \
621 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \
622 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
624 /* Convert a full 64 bit KVM register ID to the truncated 32 bit
625 * version used as a key for the coprocessor register hashtable
627 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid
)
629 uint32_t cpregid
= kvmid
;
630 if ((kvmid
& CP_REG_ARCH_MASK
) == CP_REG_ARM64
) {
631 cpregid
|= CP_REG_AA64_MASK
;
632 } else if ((kvmid
& CP_REG_SIZE_MASK
) == CP_REG_SIZE_U64
) {
633 cpregid
|= (1 << 15);
638 /* Convert a truncated 32 bit hashtable key into the full
639 * 64 bit KVM register ID.
641 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid
)
645 if (cpregid
& CP_REG_AA64_MASK
) {
646 kvmid
= cpregid
& ~CP_REG_AA64_MASK
;
647 kvmid
|= CP_REG_SIZE_U64
| CP_REG_ARM64
;
649 kvmid
= cpregid
& ~(1 << 15);
650 if (cpregid
& (1 << 15)) {
651 kvmid
|= CP_REG_SIZE_U64
| CP_REG_ARM
;
653 kvmid
|= CP_REG_SIZE_U32
| CP_REG_ARM
;
659 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
660 * special-behaviour cp reg and bits [15..8] indicate what behaviour
661 * it has. Otherwise it is a simple cp reg, where CONST indicates that
662 * TCG can assume the value to be constant (ie load at translate time)
663 * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
664 * indicates that the TB should not be ended after a write to this register
665 * (the default is that the TB ends after cp writes). OVERRIDE permits
666 * a register definition to override a previous definition for the
667 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
668 * old must have the OVERRIDE bit set.
669 * NO_MIGRATE indicates that this register should be ignored for migration;
670 * (eg because any state is accessed via some other coprocessor register).
671 * IO indicates that this register does I/O and therefore its accesses
672 * need to be surrounded by gen_io_start()/gen_io_end(). In particular,
673 * registers which implement clocks or timers require this.
675 #define ARM_CP_SPECIAL 1
676 #define ARM_CP_CONST 2
677 #define ARM_CP_64BIT 4
678 #define ARM_CP_SUPPRESS_TB_END 8
679 #define ARM_CP_OVERRIDE 16
680 #define ARM_CP_NO_MIGRATE 32
682 #define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8))
683 #define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8))
684 #define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 << 8))
685 #define ARM_LAST_SPECIAL ARM_CP_NZCV
686 /* Used only as a terminator for ARMCPRegInfo lists */
687 #define ARM_CP_SENTINEL 0xffff
688 /* Mask of only the flag bits in a type field */
689 #define ARM_CP_FLAG_MASK 0x7f
691 /* Valid values for ARMCPRegInfo state field, indicating which of
692 * the AArch32 and AArch64 execution states this register is visible in.
693 * If the reginfo doesn't explicitly specify then it is AArch32 only.
694 * If the reginfo is declared to be visible in both states then a second
695 * reginfo is synthesised for the AArch32 view of the AArch64 register,
696 * such that the AArch32 view is the lower 32 bits of the AArch64 one.
697 * Note that we rely on the values of these enums as we iterate through
698 * the various states in some places.
701 ARM_CP_STATE_AA32
= 0,
702 ARM_CP_STATE_AA64
= 1,
703 ARM_CP_STATE_BOTH
= 2,
706 /* Return true if cptype is a valid type field. This is used to try to
707 * catch errors where the sentinel has been accidentally left off the end
708 * of a list of registers.
710 static inline bool cptype_valid(int cptype
)
712 return ((cptype
& ~ARM_CP_FLAG_MASK
) == 0)
713 || ((cptype
& ARM_CP_SPECIAL
) &&
714 ((cptype
& ~ARM_CP_FLAG_MASK
) <= ARM_LAST_SPECIAL
));
718 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
719 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and
720 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1
721 * (ie any of the privileged modes in Secure state, or Monitor mode).
722 * If a register is accessible in one privilege level it's always accessible
723 * in higher privilege levels too. Since "Secure PL1" also follows this rule
724 * (ie anything visible in PL2 is visible in S-PL1, some things are only
725 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
726 * terminology a little and call this PL3.
727 * In AArch64 things are somewhat simpler as the PLx bits line up exactly
728 * with the ELx exception levels.
730 * If access permissions for a register are more complex than can be
731 * described with these bits, then use a laxer set of restrictions, and
732 * do the more restrictive/complex check inside a helper function.
736 #define PL2_R (0x20 | PL3_R)
737 #define PL2_W (0x10 | PL3_W)
738 #define PL1_R (0x08 | PL2_R)
739 #define PL1_W (0x04 | PL2_W)
740 #define PL0_R (0x02 | PL1_R)
741 #define PL0_W (0x01 | PL1_W)
743 #define PL3_RW (PL3_R | PL3_W)
744 #define PL2_RW (PL2_R | PL2_W)
745 #define PL1_RW (PL1_R | PL1_W)
746 #define PL0_RW (PL0_R | PL0_W)
748 static inline int arm_current_pl(CPUARMState
*env
)
751 return extract32(env
->pstate
, 2, 2);
754 if ((env
->uncached_cpsr
& 0x1f) == ARM_CPU_MODE_USR
) {
757 /* We don't currently implement the Virtualization or TrustZone
758 * extensions, so PL2 and PL3 don't exist for us.
763 typedef struct ARMCPRegInfo ARMCPRegInfo
;
765 /* Access functions for coprocessor registers. These should return
766 * 0 on success, or one of the EXCP_* constants if access should cause
767 * an exception (in which case *value is not written).
769 typedef int CPReadFn(CPUARMState
*env
, const ARMCPRegInfo
*opaque
,
771 typedef int CPWriteFn(CPUARMState
*env
, const ARMCPRegInfo
*opaque
,
773 /* Hook function for register reset */
774 typedef void CPResetFn(CPUARMState
*env
, const ARMCPRegInfo
*opaque
);
778 /* Definition of an ARM coprocessor register */
779 struct ARMCPRegInfo
{
780 /* Name of register (useful mainly for debugging, need not be unique) */
782 /* Location of register: coprocessor number and (crn,crm,opc1,opc2)
783 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a
784 * 'wildcard' field -- any value of that field in the MRC/MCR insn
785 * will be decoded to this register. The register read and write
786 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2
787 * used by the program, so it is possible to register a wildcard and
788 * then behave differently on read/write if necessary.
789 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2
791 * For AArch64-visible registers, opc0 is also used.
792 * Since there are no "coprocessors" in AArch64, cp is purely used as a
793 * way to distinguish (for KVM's benefit) guest-visible system registers
794 * from demuxed ones provided to preserve the "no side effects on
795 * KVM register read/write from QEMU" semantics. cp==0x13 is guest
796 * visible (to match KVM's encoding); cp==0 will be converted to
797 * cp==0x13 when the ARMCPRegInfo is registered, for convenience.
805 /* Execution state in which this register is visible: ARM_CP_STATE_* */
807 /* Register type: ARM_CP_* bits/values */
809 /* Access rights: PL*_[RW] */
811 /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when
812 * this register was defined: can be used to hand data through to the
813 * register read/write functions, since they are passed the ARMCPRegInfo*.
816 /* Value of this register, if it is ARM_CP_CONST. Otherwise, if
817 * fieldoffset is non-zero, the reset value of the register.
820 /* Offset of the field in CPUARMState for this register. This is not
822 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs
823 * 2. both readfn and writefn are specified
825 ptrdiff_t fieldoffset
; /* offsetof(CPUARMState, field) */
826 /* Function for handling reads of this register. If NULL, then reads
827 * will be done by loading from the offset into CPUARMState specified
831 /* Function for handling writes of this register. If NULL, then writes
832 * will be done by writing to the offset into CPUARMState specified
836 /* Function for doing a "raw" read; used when we need to copy
837 * coprocessor state to the kernel for KVM or out for
838 * migration. This only needs to be provided if there is also a
839 * readfn and it makes an access permission check.
841 CPReadFn
*raw_readfn
;
842 /* Function for doing a "raw" write; used when we need to copy KVM
843 * kernel coprocessor state into userspace, or for inbound
844 * migration. This only needs to be provided if there is also a
845 * writefn and it makes an access permission check or masks out
846 * "unwritable" bits or has write-one-to-clear or similar behaviour.
848 CPWriteFn
*raw_writefn
;
849 /* Function for resetting the register. If NULL, then reset will be done
850 * by writing resetvalue to the field specified in fieldoffset. If
851 * fieldoffset is 0 then no reset will be done.
856 /* Macros which are lvalues for the field in CPUARMState for the
859 #define CPREG_FIELD32(env, ri) \
860 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
861 #define CPREG_FIELD64(env, ri) \
862 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
864 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
866 void define_arm_cp_regs_with_opaque(ARMCPU
*cpu
,
867 const ARMCPRegInfo
*regs
, void *opaque
);
868 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
869 const ARMCPRegInfo
*regs
, void *opaque
);
870 static inline void define_arm_cp_regs(ARMCPU
*cpu
, const ARMCPRegInfo
*regs
)
872 define_arm_cp_regs_with_opaque(cpu
, regs
, 0);
874 static inline void define_one_arm_cp_reg(ARMCPU
*cpu
, const ARMCPRegInfo
*regs
)
876 define_one_arm_cp_reg_with_opaque(cpu
, regs
, 0);
878 const ARMCPRegInfo
*get_arm_cp_reginfo(GHashTable
*cpregs
, uint32_t encoded_cp
);
880 /* CPWriteFn that can be used to implement writes-ignored behaviour */
881 int arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
883 /* CPReadFn that can be used for read-as-zero behaviour */
884 int arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t *value
);
886 /* CPResetFn that does nothing, for use if no reset is required even
887 * if fieldoffset is non zero.
889 void arm_cp_reset_ignore(CPUARMState
*env
, const ARMCPRegInfo
*opaque
);
891 static inline bool cp_access_ok(int current_pl
,
892 const ARMCPRegInfo
*ri
, int isread
)
894 return (ri
->access
>> ((current_pl
* 2) + isread
)) & 1;
898 * write_list_to_cpustate
901 * For each register listed in the ARMCPU cpreg_indexes list, write
902 * its value from the cpreg_values list into the ARMCPUState structure.
903 * This updates TCG's working data structures from KVM data or
904 * from incoming migration state.
906 * Returns: true if all register values were updated correctly,
907 * false if some register was unknown or could not be written.
908 * Note that we do not stop early on failure -- we will attempt
909 * writing all registers in the list.
911 bool write_list_to_cpustate(ARMCPU
*cpu
);
914 * write_cpustate_to_list:
917 * For each register listed in the ARMCPU cpreg_indexes list, write
918 * its value from the ARMCPUState structure into the cpreg_values list.
919 * This is used to copy info from TCG's working data structures into
920 * KVM or for outbound migration.
922 * Returns: true if all register values were read correctly,
923 * false if some register was unknown or could not be read.
924 * Note that we do not stop early on failure -- we will attempt
925 * reading all registers in the list.
927 bool write_cpustate_to_list(ARMCPU
*cpu
);
929 /* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3.
930 Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
931 conventional cores (ie. Application or Realtime profile). */
933 #define IS_M(env) arm_feature(env, ARM_FEATURE_M)
935 #define ARM_CPUID_TI915T 0x54029152
936 #define ARM_CPUID_TI925T 0x54029252
938 #if defined(CONFIG_USER_ONLY)
939 #define TARGET_PAGE_BITS 12
941 /* The ARM MMU allows 1k pages. */
942 /* ??? Linux doesn't actually use these, and they're deprecated in recent
943 architecture revisions. Maybe a configure option to disable them. */
944 #define TARGET_PAGE_BITS 10
947 #if defined(TARGET_AARCH64)
948 # define TARGET_PHYS_ADDR_SPACE_BITS 48
949 # define TARGET_VIRT_ADDR_SPACE_BITS 64
951 # define TARGET_PHYS_ADDR_SPACE_BITS 40
952 # define TARGET_VIRT_ADDR_SPACE_BITS 32
955 static inline CPUARMState
*cpu_init(const char *cpu_model
)
957 ARMCPU
*cpu
= cpu_arm_init(cpu_model
);
964 #define cpu_exec cpu_arm_exec
965 #define cpu_gen_code cpu_arm_gen_code
966 #define cpu_signal_handler cpu_arm_signal_handler
967 #define cpu_list arm_cpu_list
969 /* MMU modes definitions */
970 #define MMU_MODE0_SUFFIX _kernel
971 #define MMU_MODE1_SUFFIX _user
972 #define MMU_USER_IDX 1
973 static inline int cpu_mmu_index (CPUARMState
*env
)
975 return (env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_USR
? 1 : 0;
978 #include "exec/cpu-all.h"
980 /* Bit usage in the TB flags field: bit 31 indicates whether we are
981 * in 32 or 64 bit mode. The meaning of the other bits depends on that.
983 #define ARM_TBFLAG_AARCH64_STATE_SHIFT 31
984 #define ARM_TBFLAG_AARCH64_STATE_MASK (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT)
986 /* Bit usage when in AArch32 state: */
987 #define ARM_TBFLAG_THUMB_SHIFT 0
988 #define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT)
989 #define ARM_TBFLAG_VECLEN_SHIFT 1
990 #define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT)
991 #define ARM_TBFLAG_VECSTRIDE_SHIFT 4
992 #define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT)
993 #define ARM_TBFLAG_PRIV_SHIFT 6
994 #define ARM_TBFLAG_PRIV_MASK (1 << ARM_TBFLAG_PRIV_SHIFT)
995 #define ARM_TBFLAG_VFPEN_SHIFT 7
996 #define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT)
997 #define ARM_TBFLAG_CONDEXEC_SHIFT 8
998 #define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT)
999 #define ARM_TBFLAG_BSWAP_CODE_SHIFT 16
1000 #define ARM_TBFLAG_BSWAP_CODE_MASK (1 << ARM_TBFLAG_BSWAP_CODE_SHIFT)
1002 /* Bit usage when in AArch64 state: currently no bits defined */
1004 /* some convenience accessor macros */
1005 #define ARM_TBFLAG_AARCH64_STATE(F) \
1006 (((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT)
1007 #define ARM_TBFLAG_THUMB(F) \
1008 (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT)
1009 #define ARM_TBFLAG_VECLEN(F) \
1010 (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT)
1011 #define ARM_TBFLAG_VECSTRIDE(F) \
1012 (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT)
1013 #define ARM_TBFLAG_PRIV(F) \
1014 (((F) & ARM_TBFLAG_PRIV_MASK) >> ARM_TBFLAG_PRIV_SHIFT)
1015 #define ARM_TBFLAG_VFPEN(F) \
1016 (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT)
1017 #define ARM_TBFLAG_CONDEXEC(F) \
1018 (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)
1019 #define ARM_TBFLAG_BSWAP_CODE(F) \
1020 (((F) & ARM_TBFLAG_BSWAP_CODE_MASK) >> ARM_TBFLAG_BSWAP_CODE_SHIFT)
1022 static inline void cpu_get_tb_cpu_state(CPUARMState
*env
, target_ulong
*pc
,
1023 target_ulong
*cs_base
, int *flags
)
1027 *flags
= ARM_TBFLAG_AARCH64_STATE_MASK
;
1030 *pc
= env
->regs
[15];
1031 *flags
= (env
->thumb
<< ARM_TBFLAG_THUMB_SHIFT
)
1032 | (env
->vfp
.vec_len
<< ARM_TBFLAG_VECLEN_SHIFT
)
1033 | (env
->vfp
.vec_stride
<< ARM_TBFLAG_VECSTRIDE_SHIFT
)
1034 | (env
->condexec_bits
<< ARM_TBFLAG_CONDEXEC_SHIFT
)
1035 | (env
->bswap_code
<< ARM_TBFLAG_BSWAP_CODE_SHIFT
);
1036 if (arm_feature(env
, ARM_FEATURE_M
)) {
1037 privmode
= !((env
->v7m
.exception
== 0) && (env
->v7m
.control
& 1));
1039 privmode
= (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
;
1042 *flags
|= ARM_TBFLAG_PRIV_MASK
;
1044 if (env
->vfp
.xregs
[ARM_VFP_FPEXC
] & (1 << 30)) {
1045 *flags
|= ARM_TBFLAG_VFPEN_MASK
;
1052 static inline bool cpu_has_work(CPUState
*cpu
)
1054 return cpu
->interrupt_request
&
1055 (CPU_INTERRUPT_FIQ
| CPU_INTERRUPT_HARD
| CPU_INTERRUPT_EXITTB
);
1058 #include "exec/exec-all.h"
1060 static inline void cpu_pc_from_tb(CPUARMState
*env
, TranslationBlock
*tb
)
1062 if (ARM_TBFLAG_AARCH64_STATE(tb
->flags
)) {
1065 env
->regs
[15] = tb
->pc
;
1069 /* Load an instruction and return it in the standard little-endian order */
1070 static inline uint32_t arm_ldl_code(CPUARMState
*env
, target_ulong addr
,
1073 uint32_t insn
= cpu_ldl_code(env
, addr
);
1075 return bswap32(insn
);
1080 /* Ditto, for a halfword (Thumb) instruction */
1081 static inline uint16_t arm_lduw_code(CPUARMState
*env
, target_ulong addr
,
1084 uint16_t insn
= cpu_lduw_code(env
, addr
);
1086 return bswap16(insn
);