| commit | cc33ae437975416a1b78f99e2715e91ab643526a | |
| author | David Daney <ddaney@caviumnetworks.com> | |
| Mon, 20 Dec 2010 23:54:50 +0000 (20 15:54 -0800) | ||
| committer | Ralf Baechle <ralf@linux-mips.org> | |
| Tue, 18 Jan 2011 18:30:23 +0000 (18 19:30 +0100) | ||
| tree | 958e4165ddcd45bf6ba9c498fa8f736dcbcbe770 | treesnapshot (tar.gz zip) |
| parent | afc7c9864a2d1b0c398425aac84b8a095c8dfa7c | commitdiff |
MIPS: Use BBIT instructions in TLB handlers
If the CPU supports BBIT0 and BBIT1, use them in TLB handlers as they
are more efficient than an AND followed by an branch and then
restoring the clobbered register.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1873/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
If the CPU supports BBIT0 and BBIT1, use them in TLB handlers as they
are more efficient than an AND followed by an branch and then
restoring the clobbered register.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1873/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| arch/mips/mm/tlbex.c | diffblobblamehistory |