arch/ppc/kernel/traps.c

   1 /*
   2  *  arch/ppc/kernel/traps.c
   3  *
   4  *  Copyright (C) 1995-1996  Gary Thomas (gdt@linuxppc.org)
   5  *
   6  *  This program is free software; you can redistribute it and/or
   7  *  modify it under the terms of the GNU General Public License
   8  *  as published by the Free Software Foundation; either version
   9  *  2 of the License, or (at your option) any later version.
  10  *
  11  *  Modified by Cort Dougan (cort@cs.nmt.edu)
  12  *  and Paul Mackerras (paulus@cs.anu.edu.au)
  13  */
  14
  15 /*
  16  * This file handles the architecture-dependent parts of hardware exceptions
  17  */
  18
  19 #include <linux/errno.h>
  20 #include <linux/sched.h>
  21 #include <linux/kernel.h>
  22 #include <linux/mm.h>
  23 #include <linux/stddef.h>
  24 #include <linux/unistd.h>
  25 #include <linux/ptrace.h>
  26 #include <linux/slab.h>
  27 #include <linux/user.h>
  28 #include <linux/a.out.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/config.h>
  31 #include <linux/init.h>
  32 #include <linux/module.h>
  33 #include <linux/prctl.h>
  34
  35 #include <asm/pgtable.h>
  36 #include <asm/uaccess.h>
  37 #include <asm/system.h>
  38 #include <asm/io.h>
  39 #include <asm/reg.h>
  40 #include <asm/xmon.h>
  41 #ifdef CONFIG_PMAC_BACKLIGHT
  42 #include <asm/backlight.h>
  43 #endif
  44 #include <asm/pmc.h>
  45
  46 #ifdef CONFIG_XMON
  47 extern int xmon_bpt(struct pt_regs *regs);
  48 extern int xmon_sstep(struct pt_regs *regs);
  49 extern int xmon_iabr_match(struct pt_regs *regs);
  50 extern int xmon_dabr_match(struct pt_regs *regs);
  51
  52 int (*debugger)(struct pt_regs *regs) = xmon;
  53 int (*debugger_bpt)(struct pt_regs *regs) = xmon_bpt;
  54 int (*debugger_sstep)(struct pt_regs *regs) = xmon_sstep;
  55 int (*debugger_iabr_match)(struct pt_regs *regs) = xmon_iabr_match;
  56 int (*debugger_dabr_match)(struct pt_regs *regs) = xmon_dabr_match;
  57 void (*debugger_fault_handler)(struct pt_regs *regs);
  58 #else
  59 #ifdef CONFIG_KGDB
  60 int (*debugger)(struct pt_regs *regs);
  61 int (*debugger_bpt)(struct pt_regs *regs);
  62 int (*debugger_sstep)(struct pt_regs *regs);
  63 int (*debugger_iabr_match)(struct pt_regs *regs);
  64 int (*debugger_dabr_match)(struct pt_regs *regs);
  65 void (*debugger_fault_handler)(struct pt_regs *regs);
  66 #else
  67 #define debugger(regs)                  do { } while (0)
  68 #define debugger_bpt(regs)              0
  69 #define debugger_sstep(regs)            0
  70 #define debugger_iabr_match(regs)       0
  71 #define debugger_dabr_match(regs)       0
  72 #define debugger_fault_handler          ((void (*)(struct pt_regs *))0)
  73 #endif
  74 #endif
  75
  76 /*
  77  * Trap & Exception support
  78  */
  79
  80 DEFINE_SPINLOCK(die_lock);
  81
  82 int die(const char * str, struct pt_regs * fp, long err)
  83 {
  84         static int die_counter;
  85         int nl = 0;
  86         console_verbose();
  87         spin_lock_irq(&die_lock);
  88 #ifdef CONFIG_PMAC_BACKLIGHT
  89         if (_machine == _MACH_Pmac) {
  90                 set_backlight_enable(1);
  91                 set_backlight_level(BACKLIGHT_MAX);
  92         }
  93 #endif
  94         printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
  95 #ifdef CONFIG_PREEMPT
  96         printk("PREEMPT ");
  97         nl = 1;
  98 #endif
  99 #ifdef CONFIG_SMP
 100         printk("SMP NR_CPUS=%d ", NR_CPUS);
 101         nl = 1;
 102 #endif
 103         if (nl)
 104                 printk("\n");
 105         show_regs(fp);
 106         spin_unlock_irq(&die_lock);
 107         /* do_exit() should take care of panic'ing from an interrupt
 108          * context so we don't handle it here
 109          */
 110         do_exit(err);
 111 }
 112
 113 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
 114 {
 115         siginfo_t info;
 116
 117         if (!user_mode(regs)) {
 118                 debugger(regs);
 119                 die("Exception in kernel mode", regs, signr);
 120         }
 121         info.si_signo = signr;
 122         info.si_errno = 0;
 123         info.si_code = code;
 124         info.si_addr = (void __user *) addr;
 125         force_sig_info(signr, &info, current);
 126
 127         /*
 128          * Init gets no signals that it doesn't have a handler for.
 129          * That's all very well, but if it has caused a synchronous
 130          * exception and we ignore the resulting signal, it will just
 131          * generate the same exception over and over again and we get
 132          * nowhere.  Better to kill it and let the kernel panic.
 133          */
 134         if (current->pid == 1) {
 135                 __sighandler_t handler;
 136
 137                 spin_lock_irq(&current->sighand->siglock);
 138                 handler = current->sighand->action[signr-1].sa.sa_handler;
 139                 spin_unlock_irq(&current->sighand->siglock);
 140                 if (handler == SIG_DFL) {
 141                         /* init has generated a synchronous exception
 142                            and it doesn't have a handler for the signal */
 143                         printk(KERN_CRIT "init has generated signal %d "
 144                                "but has no handler for it\n", signr);
 145                         do_exit(signr);
 146                 }
 147         }
 148 }
 149
 150 /*
 151  * I/O accesses can cause machine checks on powermacs.
 152  * Check if the NIP corresponds to the address of a sync
 153  * instruction for which there is an entry in the exception
 154  * table.
 155  * Note that the 601 only takes a machine check on TEA
 156  * (transfer error ack) signal assertion, and does not
 157  * set any of the top 16 bits of SRR1.
 158  *  -- paulus.
 159  */
 160 static inline int check_io_access(struct pt_regs *regs)
 161 {
 162 #if defined CONFIG_PPC_PMAC || defined CONFIG_8xx
 163         unsigned long msr = regs->msr;
 164         const struct exception_table_entry *entry;
 165         unsigned int *nip = (unsigned int *)regs->nip;
 166
 167         if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000)))
 168             && (entry = search_exception_tables(regs->nip)) != NULL) {
 169                 /*
 170                  * Check that it's a sync instruction, or somewhere
 171                  * in the twi; isync; nop sequence that inb/inw/inl uses.
 172                  * As the address is in the exception table
 173                  * we should be able to read the instr there.
 174                  * For the debug message, we look at the preceding
 175                  * load or store.
 176                  */
 177                 if (*nip == 0x60000000)         /* nop */
 178                         nip -= 2;
 179                 else if (*nip == 0x4c00012c)    /* isync */
 180                         --nip;
 181                 /* eieio from I/O string functions */
 182                 else if ((*nip) == 0x7c0006ac || *(nip+1) == 0x7c0006ac)
 183                         nip += 2;
 184                 if (*nip == 0x7c0004ac || (*nip >> 26) == 3 ||
 185                         (*(nip+1) >> 26) == 3) {
 186                         /* sync or twi */
 187                         unsigned int rb;
 188
 189                         --nip;
 190                         rb = (*nip >> 11) & 0x1f;
 191                         printk(KERN_DEBUG "%s bad port %lx at %p\n",
 192                                (*nip & 0x100)? "OUT to": "IN from",
 193                                regs->gpr[rb] - _IO_BASE, nip);
 194                         regs->msr |= MSR_RI;
 195                         regs->nip = entry->fixup;
 196                         return 1;
 197                 }
 198         }
 199 #endif /* CONFIG_PPC_PMAC */
 200         return 0;
 201 }
 202
 203 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
 204 /* On 4xx, the reason for the machine check or program exception
 205    is in the ESR. */
 206 #define get_reason(regs)        ((regs)->dsisr)
 207 #ifndef CONFIG_FSL_BOOKE
 208 #define get_mc_reason(regs)     ((regs)->dsisr)
 209 #else
 210 #define get_mc_reason(regs)     (mfspr(SPRN_MCSR))
 211 #endif
 212 #define REASON_FP               ESR_FP
 213 #define REASON_ILLEGAL          (ESR_PIL | ESR_PUO)
 214 #define REASON_PRIVILEGED       ESR_PPR
 215 #define REASON_TRAP             ESR_PTR
 216
 217 /* single-step stuff */
 218 #define single_stepping(regs)   (current->thread.dbcr0 & DBCR0_IC)
 219 #define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC)
 220
 221 #else
 222 /* On non-4xx, the reason for the machine check or program
 223    exception is in the MSR. */
 224 #define get_reason(regs)        ((regs)->msr)
 225 #define get_mc_reason(regs)     ((regs)->msr)
 226 #define REASON_FP               0x100000
 227 #define REASON_ILLEGAL          0x80000
 228 #define REASON_PRIVILEGED       0x40000
 229 #define REASON_TRAP             0x20000
 230
 231 #define single_stepping(regs)   ((regs)->msr & MSR_SE)
 232 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE)
 233 #endif
 234
 235 /*
 236  * This is "fall-back" implementation for configurations
 237  * which don't provide platform-specific machine check info
 238  */
 239 void __attribute__ ((weak))
 240 platform_machine_check(struct pt_regs *regs)
 241 {
 242 }
 243
 244 void machine_check_exception(struct pt_regs *regs)
 245 {
 246         unsigned long reason = get_mc_reason(regs);
 247
 248         if (user_mode(regs)) {
 249                 regs->msr |= MSR_RI;
 250                 _exception(SIGBUS, regs, BUS_ADRERR, regs->nip);
 251                 return;
 252         }
 253
 254 #if defined(CONFIG_8xx) && defined(CONFIG_PCI)
 255         /* the qspan pci read routines can cause machine checks -- Cort */
 256         bad_page_fault(regs, regs->dar, SIGBUS);
 257         return;
 258 #endif
 259
 260         if (debugger_fault_handler) {
 261                 debugger_fault_handler(regs);
 262                 regs->msr |= MSR_RI;
 263                 return;
 264         }
 265
 266         if (check_io_access(regs))
 267                 return;
 268
 269 #if defined(CONFIG_4xx) && !defined(CONFIG_440A)
 270         if (reason & ESR_IMCP) {
 271                 printk("Instruction");
 272                 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
 273         } else
 274                 printk("Data");
 275         printk(" machine check in kernel mode.\n");
 276 #elif defined(CONFIG_440A)
 277         printk("Machine check in kernel mode.\n");
 278         if (reason & ESR_IMCP){
 279                 printk("Instruction Synchronous Machine Check exception\n");
 280                 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
 281         }
 282         else {
 283                 u32 mcsr = mfspr(SPRN_MCSR);
 284                 if (mcsr & MCSR_IB)
 285                         printk("Instruction Read PLB Error\n");
 286                 if (mcsr & MCSR_DRB)
 287                         printk("Data Read PLB Error\n");
 288                 if (mcsr & MCSR_DWB)
 289                         printk("Data Write PLB Error\n");
 290                 if (mcsr & MCSR_TLBP)
 291                         printk("TLB Parity Error\n");
 292                 if (mcsr & MCSR_ICP){
 293                         flush_instruction_cache();
 294                         printk("I-Cache Parity Error\n");
 295                 }
 296                 if (mcsr & MCSR_DCSP)
 297                         printk("D-Cache Search Parity Error\n");
 298                 if (mcsr & MCSR_DCFP)
 299                         printk("D-Cache Flush Parity Error\n");
 300                 if (mcsr & MCSR_IMPE)
 301                         printk("Machine Check exception is imprecise\n");
 302
 303                 /* Clear MCSR */
 304                 mtspr(SPRN_MCSR, mcsr);
 305         }
 306 #elif defined (CONFIG_E500)
 307         printk("Machine check in kernel mode.\n");
 308         printk("Caused by (from MCSR=%lx): ", reason);
 309
 310         if (reason & MCSR_MCP)
 311                 printk("Machine Check Signal\n");
 312         if (reason & MCSR_ICPERR)
 313                 printk("Instruction Cache Parity Error\n");
 314         if (reason & MCSR_DCP_PERR)
 315                 printk("Data Cache Push Parity Error\n");
 316         if (reason & MCSR_DCPERR)
 317                 printk("Data Cache Parity Error\n");
 318         if (reason & MCSR_GL_CI)
 319                 printk("Guarded Load or Cache-Inhibited stwcx.\n");
 320         if (reason & MCSR_BUS_IAERR)
 321                 printk("Bus - Instruction Address Error\n");
 322         if (reason & MCSR_BUS_RAERR)
 323                 printk("Bus - Read Address Error\n");
 324         if (reason & MCSR_BUS_WAERR)
 325                 printk("Bus - Write Address Error\n");
 326         if (reason & MCSR_BUS_IBERR)
 327                 printk("Bus - Instruction Data Error\n");
 328         if (reason & MCSR_BUS_RBERR)
 329                 printk("Bus - Read Data Bus Error\n");
 330         if (reason & MCSR_BUS_WBERR)
 331                 printk("Bus - Read Data Bus Error\n");
 332         if (reason & MCSR_BUS_IPERR)
 333                 printk("Bus - Instruction Parity Error\n");
 334         if (reason & MCSR_BUS_RPERR)
 335                 printk("Bus - Read Parity Error\n");
 336 #elif defined (CONFIG_E200)
 337         printk("Machine check in kernel mode.\n");
 338         printk("Caused by (from MCSR=%lx): ", reason);
 339
 340         if (reason & MCSR_MCP)
 341                 printk("Machine Check Signal\n");
 342         if (reason & MCSR_CP_PERR)
 343                 printk("Cache Push Parity Error\n");
 344         if (reason & MCSR_CPERR)
 345                 printk("Cache Parity Error\n");
 346         if (reason & MCSR_EXCP_ERR)
 347                 printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
 348         if (reason & MCSR_BUS_IRERR)
 349                 printk("Bus - Read Bus Error on instruction fetch\n");
 350         if (reason & MCSR_BUS_DRERR)
 351                 printk("Bus - Read Bus Error on data load\n");
 352         if (reason & MCSR_BUS_WRERR)
 353                 printk("Bus - Write Bus Error on buffered store or cache line push\n");
 354 #else /* !CONFIG_4xx && !CONFIG_E500 && !CONFIG_E200 */
 355         printk("Machine check in kernel mode.\n");
 356         printk("Caused by (from SRR1=%lx): ", reason);
 357         switch (reason & 0x601F0000) {
 358         case 0x80000:
 359                 printk("Machine check signal\n");
 360                 break;
 361         case 0:         /* for 601 */
 362         case 0x40000:
 363         case 0x140000:  /* 7450 MSS error and TEA */
 364                 printk("Transfer error ack signal\n");
 365                 break;
 366         case 0x20000:
 367                 printk("Data parity error signal\n");
 368                 break;
 369         case 0x10000:
 370                 printk("Address parity error signal\n");
 371                 break;
 372         case 0x20000000:
 373                 printk("L1 Data Cache error\n");
 374                 break;
 375         case 0x40000000:
 376                 printk("L1 Instruction Cache error\n");
 377                 break;
 378         case 0x00100000:
 379                 printk("L2 data cache parity error\n");
 380                 break;
 381         default:
 382                 printk("Unknown values in msr\n");
 383         }
 384 #endif /* CONFIG_4xx */
 385
 386         /*
 387          * Optional platform-provided routine to print out
 388          * additional info, e.g. bus error registers.
 389          */
 390         platform_machine_check(regs);
 391
 392         debugger(regs);
 393         die("machine check", regs, SIGBUS);
 394 }
 395
 396 void SMIException(struct pt_regs *regs)
 397 {
 398         debugger(regs);
 399 #if !(defined(CONFIG_XMON) || defined(CONFIG_KGDB))
 400         show_regs(regs);
 401         panic("System Management Interrupt");
 402 #endif
 403 }
 404
 405 void unknown_exception(struct pt_regs *regs)
 406 {
 407         printk("Bad trap at PC: %lx, MSR: %lx, vector=%lx    %s\n",
 408                regs->nip, regs->msr, regs->trap, print_tainted());
 409         _exception(SIGTRAP, regs, 0, 0);
 410 }
 411
 412 void instruction_breakpoint_exception(struct pt_regs *regs)
 413 {
 414         if (debugger_iabr_match(regs))
 415                 return;
 416         _exception(SIGTRAP, regs, TRAP_BRKPT, 0);
 417 }
 418
 419 void RunModeException(struct pt_regs *regs)
 420 {
 421         _exception(SIGTRAP, regs, 0, 0);
 422 }
 423
 424 /* Illegal instruction emulation support.  Originally written to
 425  * provide the PVR to user applications using the mfspr rd, PVR.
 426  * Return non-zero if we can't emulate, or -EFAULT if the associated
 427  * memory access caused an access fault.  Return zero on success.
 428  *
 429  * There are a couple of ways to do this, either "decode" the instruction
 430  * or directly match lots of bits.  In this case, matching lots of
 431  * bits is faster and easier.
 432  *
 433  */
 434 #define INST_MFSPR_PVR          0x7c1f42a6
 435 #define INST_MFSPR_PVR_MASK     0xfc1fffff
 436
 437 #define INST_DCBA               0x7c0005ec
 438 #define INST_DCBA_MASK          0x7c0007fe
 439
 440 #define INST_MCRXR              0x7c000400
 441 #define INST_MCRXR_MASK         0x7c0007fe
 442
 443 #define INST_STRING             0x7c00042a
 444 #define INST_STRING_MASK        0x7c0007fe
 445 #define INST_STRING_GEN_MASK    0x7c00067e
 446 #define INST_LSWI               0x7c0004aa
 447 #define INST_LSWX               0x7c00042a
 448 #define INST_STSWI              0x7c0005aa
 449 #define INST_STSWX              0x7c00052a
 450
 451 static int emulate_string_inst(struct pt_regs *regs, u32 instword)
 452 {
 453         u8 rT = (instword >> 21) & 0x1f;
 454         u8 rA = (instword >> 16) & 0x1f;
 455         u8 NB_RB = (instword >> 11) & 0x1f;
 456         u32 num_bytes;
 457         unsigned long EA;
 458         int pos = 0;
 459
 460         /* Early out if we are an invalid form of lswx */
 461         if ((instword & INST_STRING_MASK) == INST_LSWX)
 462                 if ((rT == rA) || (rT == NB_RB))
 463                         return -EINVAL;
 464
 465         EA = (rA == 0) ? 0 : regs->gpr[rA];
 466
 467         switch (instword & INST_STRING_MASK) {
 468                 case INST_LSWX:
 469                 case INST_STSWX:
 470                         EA += NB_RB;
 471                         num_bytes = regs->xer & 0x7f;
 472                         break;
 473                 case INST_LSWI:
 474                 case INST_STSWI:
 475                         num_bytes = (NB_RB == 0) ? 32 : NB_RB;
 476                         break;
 477                 default:
 478                         return -EINVAL;
 479         }
 480
 481         while (num_bytes != 0)
 482         {
 483                 u8 val;
 484                 u32 shift = 8 * (3 - (pos & 0x3));
 485
 486                 switch ((instword & INST_STRING_MASK)) {
 487                         case INST_LSWX:
 488                         case INST_LSWI:
 489                                 if (get_user(val, (u8 __user *)EA))
 490                                         return -EFAULT;
 491                                 /* first time updating this reg,
 492                                  * zero it out */
 493                                 if (pos == 0)
 494                                         regs->gpr[rT] = 0;
 495                                 regs->gpr[rT] |= val << shift;
 496                                 break;
 497                         case INST_STSWI:
 498                         case INST_STSWX:
 499                                 val = regs->gpr[rT] >> shift;
 500                                 if (put_user(val, (u8 __user *)EA))
 501                                         return -EFAULT;
 502                                 break;
 503                 }
 504                 /* move EA to next address */
 505                 EA += 1;
 506                 num_bytes--;
 507
 508                 /* manage our position within the register */
 509                 if (++pos == 4) {
 510                         pos = 0;
 511                         if (++rT == 32)
 512                                 rT = 0;
 513                 }
 514         }
 515
 516         return 0;
 517 }
 518
 519 static int emulate_instruction(struct pt_regs *regs)
 520 {
 521         u32 instword;
 522         u32 rd;
 523
 524         if (!user_mode(regs))
 525                 return -EINVAL;
 526         CHECK_FULL_REGS(regs);
 527
 528         if (get_user(instword, (u32 __user *)(regs->nip)))
 529                 return -EFAULT;
 530
 531         /* Emulate the mfspr rD, PVR.
 532          */
 533         if ((instword & INST_MFSPR_PVR_MASK) == INST_MFSPR_PVR) {
 534                 rd = (instword >> 21) & 0x1f;
 535                 regs->gpr[rd] = mfspr(SPRN_PVR);
 536                 return 0;
 537         }
 538
 539         /* Emulating the dcba insn is just a no-op.  */
 540         if ((instword & INST_DCBA_MASK) == INST_DCBA)
 541                 return 0;
 542
 543         /* Emulate the mcrxr insn.  */
 544         if ((instword & INST_MCRXR_MASK) == INST_MCRXR) {
 545                 int shift = (instword >> 21) & 0x1c;
 546                 unsigned long msk = 0xf0000000UL >> shift;
 547
 548                 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk);
 549                 regs->xer &= ~0xf0000000UL;
 550                 return 0;
 551         }
 552
 553         /* Emulate load/store string insn. */
 554         if ((instword & INST_STRING_GEN_MASK) == INST_STRING)
 555                 return emulate_string_inst(regs, instword);
 556
 557         return -EINVAL;
 558 }
 559
 560 /*
 561  * After we have successfully emulated an instruction, we have to
 562  * check if the instruction was being single-stepped, and if so,
 563  * pretend we got a single-step exception.  This was pointed out
 564  * by Kumar Gala.  -- paulus
 565  */
 566 static void emulate_single_step(struct pt_regs *regs)
 567 {
 568         if (single_stepping(regs)) {
 569                 clear_single_step(regs);
 570                 _exception(SIGTRAP, regs, TRAP_TRACE, 0);
 571         }
 572 }
 573
 574 /*
 575  * Look through the list of trap instructions that are used for BUG(),
 576  * BUG_ON() and WARN_ON() and see if we hit one.  At this point we know
 577  * that the exception was caused by a trap instruction of some kind.
 578  * Returns 1 if we should continue (i.e. it was a WARN_ON) or 0
 579  * otherwise.
 580  */
 581 extern struct bug_entry __start___bug_table[], __stop___bug_table[];
 582
 583 #ifndef CONFIG_MODULES
 584 #define module_find_bug(x)      NULL
 585 #endif
 586
 587 struct bug_entry *find_bug(unsigned long bugaddr)
 588 {
 589         struct bug_entry *bug;
 590
 591         for (bug = __start___bug_table; bug < __stop___bug_table; ++bug)
 592                 if (bugaddr == bug->bug_addr)
 593                         return bug;
 594         return module_find_bug(bugaddr);
 595 }
 596
 597 int check_bug_trap(struct pt_regs *regs)
 598 {
 599         struct bug_entry *bug;
 600         unsigned long addr;
 601
 602         if (regs->msr & MSR_PR)
 603                 return 0;       /* not in kernel */
 604         addr = regs->nip;       /* address of trap instruction */
 605         if (addr < PAGE_OFFSET)
 606                 return 0;
 607         bug = find_bug(regs->nip);
 608         if (bug == NULL)
 609                 return 0;
 610         if (bug->line & BUG_WARNING_TRAP) {
 611                 /* this is a WARN_ON rather than BUG/BUG_ON */
 612 #ifdef CONFIG_XMON
 613                 xmon_printf(KERN_ERR "Badness in %s at %s:%ld\n",
 614                        bug->function, bug->file,
 615                        bug->line & ~BUG_WARNING_TRAP);
 616 #endif /* CONFIG_XMON */
 617                 printk(KERN_ERR "Badness in %s at %s:%ld\n",
 618                        bug->function, bug->file,
 619                        bug->line & ~BUG_WARNING_TRAP);
 620                 dump_stack();
 621                 return 1;
 622         }
 623 #ifdef CONFIG_XMON
 624         xmon_printf(KERN_CRIT "kernel BUG in %s at %s:%ld!\n",
 625                bug->function, bug->file, bug->line);
 626         xmon(regs);
 627 #endif /* CONFIG_XMON */
 628         printk(KERN_CRIT "kernel BUG in %s at %s:%ld!\n",
 629                bug->function, bug->file, bug->line);
 630
 631         return 0;
 632 }
 633
 634 void program_check_exception(struct pt_regs *regs)
 635 {
 636         unsigned int reason = get_reason(regs);
 637         extern int do_mathemu(struct pt_regs *regs);
 638
 639 #ifdef CONFIG_MATH_EMULATION
 640         /* (reason & REASON_ILLEGAL) would be the obvious thing here,
 641          * but there seems to be a hardware bug on the 405GP (RevD)
 642          * that means ESR is sometimes set incorrectly - either to
 643          * ESR_DST (!?) or 0.  In the process of chasing this with the
 644          * hardware people - not sure if it can happen on any illegal
 645          * instruction or only on FP instructions, whether there is a
 646          * pattern to occurences etc. -dgibson 31/Mar/2003 */
 647         if (!(reason & REASON_TRAP) && do_mathemu(regs) == 0) {
 648                 emulate_single_step(regs);
 649                 return;
 650         }
 651 #endif /* CONFIG_MATH_EMULATION */
 652
 653         if (reason & REASON_FP) {
 654                 /* IEEE FP exception */
 655                 int code = 0;
 656                 u32 fpscr;
 657
 658                 /* We must make sure the FP state is consistent with
 659                  * our MSR_FP in regs
 660                  */
 661                 preempt_disable();
 662                 if (regs->msr & MSR_FP)
 663                         giveup_fpu(current);
 664                 preempt_enable();
 665
 666                 fpscr = current->thread.fpscr.val;
 667                 fpscr &= fpscr << 22;   /* mask summary bits with enables */
 668                 if (fpscr & FPSCR_VX)
 669                         code = FPE_FLTINV;
 670                 else if (fpscr & FPSCR_OX)
 671                         code = FPE_FLTOVF;
 672                 else if (fpscr & FPSCR_UX)
 673                         code = FPE_FLTUND;
 674                 else if (fpscr & FPSCR_ZX)
 675                         code = FPE_FLTDIV;
 676                 else if (fpscr & FPSCR_XX)
 677                         code = FPE_FLTRES;
 678                 _exception(SIGFPE, regs, code, regs->nip);
 679                 return;
 680         }
 681
 682         if (reason & REASON_TRAP) {
 683                 /* trap exception */
 684                 if (debugger_bpt(regs))
 685                         return;
 686                 if (check_bug_trap(regs)) {
 687                         regs->nip += 4;
 688                         return;
 689                 }
 690                 _exception(SIGTRAP, regs, TRAP_BRKPT, 0);
 691                 return;
 692         }
 693
 694         /* Try to emulate it if we should. */
 695         if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) {
 696                 switch (emulate_instruction(regs)) {
 697                 case 0:
 698                         regs->nip += 4;
 699                         emulate_single_step(regs);
 700                         return;
 701                 case -EFAULT:
 702                         _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
 703                         return;
 704                 }
 705         }
 706
 707         if (reason & REASON_PRIVILEGED)
 708                 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
 709         else
 710                 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
 711 }
 712
 713 void single_step_exception(struct pt_regs *regs)
 714 {
 715         regs->msr &= ~(MSR_SE | MSR_BE);  /* Turn off 'trace' bits */
 716         if (debugger_sstep(regs))
 717                 return;
 718         _exception(SIGTRAP, regs, TRAP_TRACE, 0);
 719 }
 720
 721 void alignment_exception(struct pt_regs *regs)
 722 {
 723         int fixed;
 724
 725         fixed = fix_alignment(regs);
 726         if (fixed == 1) {
 727                 regs->nip += 4; /* skip over emulated instruction */
 728                 emulate_single_step(regs);
 729                 return;
 730         }
 731         if (fixed == -EFAULT) {
 732                 /* fixed == -EFAULT means the operand address was bad */
 733                 if (user_mode(regs))
 734                         _exception(SIGSEGV, regs, SEGV_ACCERR, regs->dar);
 735                 else
 736                         bad_page_fault(regs, regs->dar, SIGSEGV);
 737                 return;
 738         }
 739         _exception(SIGBUS, regs, BUS_ADRALN, regs->dar);
 740 }
 741
 742 void StackOverflow(struct pt_regs *regs)
 743 {
 744         printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n",
 745                current, regs->gpr[1]);
 746         debugger(regs);
 747         show_regs(regs);
 748         panic("kernel stack overflow");
 749 }
 750
 751 void nonrecoverable_exception(struct pt_regs *regs)
 752 {
 753         printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n",
 754                regs->nip, regs->msr);
 755         debugger(regs);
 756         die("nonrecoverable exception", regs, SIGKILL);
 757 }
 758
 759 void trace_syscall(struct pt_regs *regs)
 760 {
 761         printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld    %s\n",
 762                current, current->pid, regs->nip, regs->link, regs->gpr[0],
 763                regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted());
 764 }
 765
 766 #ifdef CONFIG_8xx
 767 void SoftwareEmulation(struct pt_regs *regs)
 768 {
 769         extern int do_mathemu(struct pt_regs *);
 770         extern int Soft_emulate_8xx(struct pt_regs *);
 771         int errcode;
 772
 773         CHECK_FULL_REGS(regs);
 774
 775         if (!user_mode(regs)) {
 776                 debugger(regs);
 777                 die("Kernel Mode Software FPU Emulation", regs, SIGFPE);
 778         }
 779
 780 #ifdef CONFIG_MATH_EMULATION
 781         errcode = do_mathemu(regs);
 782 #else
 783         errcode = Soft_emulate_8xx(regs);
 784 #endif
 785         if (errcode) {
 786                 if (errcode > 0)
 787                         _exception(SIGFPE, regs, 0, 0);
 788                 else if (errcode == -EFAULT)
 789                         _exception(SIGSEGV, regs, 0, 0);
 790                 else
 791                         _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
 792         } else
 793                 emulate_single_step(regs);
 794 }
 795 #endif /* CONFIG_8xx */
 796
 797 #if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
 798
 799 void DebugException(struct pt_regs *regs, unsigned long debug_status)
 800 {
 801         if (debug_status & DBSR_IC) {   /* instruction completion */
 802                 regs->msr &= ~MSR_DE;
 803                 if (user_mode(regs)) {
 804                         current->thread.dbcr0 &= ~DBCR0_IC;
 805                 } else {
 806                         /* Disable instruction completion */
 807                         mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC);
 808                         /* Clear the instruction completion event */
 809                         mtspr(SPRN_DBSR, DBSR_IC);
 810                         if (debugger_sstep(regs))
 811                                 return;
 812                 }
 813                 _exception(SIGTRAP, regs, TRAP_TRACE, 0);
 814         }
 815 }
 816 #endif /* CONFIG_4xx || CONFIG_BOOKE */
 817
 818 #if !defined(CONFIG_TAU_INT)
 819 void TAUException(struct pt_regs *regs)
 820 {
 821         printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx    %s\n",
 822                regs->nip, regs->msr, regs->trap, print_tainted());
 823 }
 824 #endif /* CONFIG_INT_TAU */
 825
 826 /*
 827  * FP unavailable trap from kernel - print a message, but let
 828  * the task use FP in the kernel until it returns to user mode.
 829  */
 830 void kernel_fp_unavailable_exception(struct pt_regs *regs)
 831 {
 832         regs->msr |= MSR_FP;
 833         printk(KERN_ERR "floating point used in kernel (task=%p, pc=%lx)\n",
 834                current, regs->nip);
 835 }
 836
 837 void altivec_unavailable_exception(struct pt_regs *regs)
 838 {
 839         static int kernel_altivec_count;
 840
 841 #ifndef CONFIG_ALTIVEC
 842         if (user_mode(regs)) {
 843                 /* A user program has executed an altivec instruction,
 844                    but this kernel doesn't support altivec. */
 845                 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
 846                 return;
 847         }
 848 #endif
 849         /* The kernel has executed an altivec instruction without
 850            first enabling altivec.  Whinge but let it do it. */
 851         if (++kernel_altivec_count < 10)
 852                 printk(KERN_ERR "AltiVec used in kernel (task=%p, pc=%lx)\n",
 853                        current, regs->nip);
 854         regs->msr |= MSR_VEC;
 855 }
 856
 857 #ifdef CONFIG_ALTIVEC
 858 void altivec_assist_exception(struct pt_regs *regs)
 859 {
 860         int err;
 861
 862         preempt_disable();
 863         if (regs->msr & MSR_VEC)
 864                 giveup_altivec(current);
 865         preempt_enable();
 866         if (!user_mode(regs)) {
 867                 printk(KERN_ERR "altivec assist exception in kernel mode"
 868                        " at %lx\n", regs->nip);
 869                 debugger(regs);
 870                 die("altivec assist exception", regs, SIGFPE);
 871                 return;
 872         }
 873
 874         err = emulate_altivec(regs);
 875         if (err == 0) {
 876                 regs->nip += 4;         /* skip emulated instruction */
 877                 emulate_single_step(regs);
 878                 return;
 879         }
 880
 881         if (err == -EFAULT) {
 882                 /* got an error reading the instruction */
 883                 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
 884         } else {
 885                 /* didn't recognize the instruction */
 886                 /* XXX quick hack for now: set the non-Java bit in the VSCR */
 887                 printk(KERN_ERR "unrecognized altivec instruction "
 888                        "in %s at %lx\n", current->comm, regs->nip);
 889                 current->thread.vscr.u[3] |= 0x10000;
 890         }
 891 }
 892 #endif /* CONFIG_ALTIVEC */
 893
 894 #ifdef CONFIG_E500
 895 void performance_monitor_exception(struct pt_regs *regs)
 896 {
 897         perf_irq(regs);
 898 }
 899 #endif
 900
 901 #ifdef CONFIG_FSL_BOOKE
 902 void CacheLockingException(struct pt_regs *regs, unsigned long address,
 903                            unsigned long error_code)
 904 {
 905         /* We treat cache locking instructions from the user
 906          * as priv ops, in the future we could try to do
 907          * something smarter
 908          */
 909         if (error_code & (ESR_DLK|ESR_ILK))
 910                 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
 911         return;
 912 }
 913 #endif /* CONFIG_FSL_BOOKE */
 914
 915 #ifdef CONFIG_SPE
 916 void SPEFloatingPointException(struct pt_regs *regs)
 917 {
 918         unsigned long spefscr;
 919         int fpexc_mode;
 920         int code = 0;
 921
 922         spefscr = current->thread.spefscr;
 923         fpexc_mode = current->thread.fpexc_mode;
 924
 925         /* Hardware does not neccessarily set sticky
 926          * underflow/overflow/invalid flags */
 927         if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) {
 928                 code = FPE_FLTOVF;
 929                 spefscr |= SPEFSCR_FOVFS;
 930         }
 931         else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) {
 932                 code = FPE_FLTUND;
 933                 spefscr |= SPEFSCR_FUNFS;
 934         }
 935         else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV))
 936                 code = FPE_FLTDIV;
 937         else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) {
 938                 code = FPE_FLTINV;
 939                 spefscr |= SPEFSCR_FINVS;
 940         }
 941         else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES))
 942                 code = FPE_FLTRES;
 943
 944         current->thread.spefscr = spefscr;
 945
 946         _exception(SIGFPE, regs, code, regs->nip);
 947         return;
 948 }
 949 #endif
 950
 951 #ifdef CONFIG_BOOKE_WDT
 952 /*
 953  * Default handler for a Watchdog exception,
 954  * spins until a reboot occurs
 955  */
 956 void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs)
 957 {
 958         /* Generic WatchdogHandler, implement your own */
 959         mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE));
 960         return;
 961 }
 962
 963 void WatchdogException(struct pt_regs *regs)
 964 {
 965         printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n");
 966         WatchdogHandler(regs);
 967 }
 968 #endif
 969
 970 void __init trap_init(void)
 971 {
 972 }