1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
27 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
29 ***************************************************************************/
34 #include "breakpoints.h"
35 #include "cortex_m3.h"
36 #include "target_request.h"
37 #include "target_type.h"
38 #include "arm_disassembler.h"
41 /* NOTE: most of this should work fine for the Cortex-M1 and
42 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
45 #define ARRAY_SIZE(x) ((int)(sizeof(x)/sizeof((x)[0])))
48 /* forward declarations */
49 static int cortex_m3_set_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
);
50 static int cortex_m3_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
);
51 static void cortex_m3_enable_watchpoints(struct target
*target
);
52 static int cortex_m3_store_core_reg_u32(struct target
*target
,
53 enum armv7m_regtype type
, uint32_t num
, uint32_t value
);
55 #ifdef ARMV7_GDB_HACKS
56 extern uint8_t armv7m_gdb_dummy_cpsr_value
[];
57 extern struct reg armv7m_gdb_dummy_cpsr_reg
;
60 static int cortexm3_dap_read_coreregister_u32(struct swjdp_common
*swjdp
,
61 uint32_t *value
, int regnum
)
66 /* because the DCB_DCRDR is used for the emulated dcc channel
67 * we have to save/restore the DCB_DCRDR when used */
69 mem_ap_read_u32(swjdp
, DCB_DCRDR
, &dcrdr
);
71 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
73 /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
74 dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRSR
& 0xFFFFFFF0);
75 dap_ap_write_reg_u32(swjdp
, AP_REG_BD0
| (DCB_DCRSR
& 0xC), regnum
);
77 /* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */
78 dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRDR
& 0xFFFFFFF0);
79 dap_ap_read_reg_u32(swjdp
, AP_REG_BD0
| (DCB_DCRDR
& 0xC), value
);
81 retval
= swjdp_transaction_endcheck(swjdp
);
83 /* restore DCB_DCRDR - this needs to be in a seperate
84 * transaction otherwise the emulated DCC channel breaks */
85 if (retval
== ERROR_OK
)
86 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DCRDR
, dcrdr
);
91 static int cortexm3_dap_write_coreregister_u32(struct swjdp_common
*swjdp
,
92 uint32_t value
, int regnum
)
97 /* because the DCB_DCRDR is used for the emulated dcc channel
98 * we have to save/restore the DCB_DCRDR when used */
100 mem_ap_read_u32(swjdp
, DCB_DCRDR
, &dcrdr
);
102 swjdp
->trans_mode
= TRANS_MODE_COMPOSITE
;
104 /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
105 dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRDR
& 0xFFFFFFF0);
106 dap_ap_write_reg_u32(swjdp
, AP_REG_BD0
| (DCB_DCRDR
& 0xC), value
);
108 /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */
109 dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRSR
& 0xFFFFFFF0);
110 dap_ap_write_reg_u32(swjdp
, AP_REG_BD0
| (DCB_DCRSR
& 0xC), regnum
| DCRSR_WnR
);
112 retval
= swjdp_transaction_endcheck(swjdp
);
114 /* restore DCB_DCRDR - this needs to be in a seperate
115 * transaction otherwise the emulated DCC channel breaks */
116 if (retval
== ERROR_OK
)
117 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DCRDR
, dcrdr
);
122 static int cortex_m3_write_debug_halt_mask(struct target
*target
,
123 uint32_t mask_on
, uint32_t mask_off
)
125 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
126 struct swjdp_common
*swjdp
= &cortex_m3
->armv7m
.swjdp_info
;
128 /* mask off status bits */
129 cortex_m3
->dcb_dhcsr
&= ~((0xFFFF << 16) | mask_off
);
130 /* create new register mask */
131 cortex_m3
->dcb_dhcsr
|= DBGKEY
| C_DEBUGEN
| mask_on
;
133 return mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
, cortex_m3
->dcb_dhcsr
);
136 static int cortex_m3_clear_halt(struct target
*target
)
138 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
139 struct swjdp_common
*swjdp
= &cortex_m3
->armv7m
.swjdp_info
;
141 /* clear step if any */
142 cortex_m3_write_debug_halt_mask(target
, C_HALT
, C_STEP
);
144 /* Read Debug Fault Status Register */
145 mem_ap_read_atomic_u32(swjdp
, NVIC_DFSR
, &cortex_m3
->nvic_dfsr
);
146 /* Clear Debug Fault Status */
147 mem_ap_write_atomic_u32(swjdp
, NVIC_DFSR
, cortex_m3
->nvic_dfsr
);
148 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32
"", cortex_m3
->nvic_dfsr
);
153 static int cortex_m3_single_step_core(struct target
*target
)
155 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
156 struct swjdp_common
*swjdp
= &cortex_m3
->armv7m
.swjdp_info
;
159 /* backup dhcsr reg */
160 dhcsr_save
= cortex_m3
->dcb_dhcsr
;
162 /* mask interrupts if not done already */
163 if (!(cortex_m3
->dcb_dhcsr
& C_MASKINTS
))
164 mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
, DBGKEY
| C_MASKINTS
| C_HALT
| C_DEBUGEN
);
165 mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
, DBGKEY
| C_MASKINTS
| C_STEP
| C_DEBUGEN
);
168 /* restore dhcsr reg */
169 cortex_m3
->dcb_dhcsr
= dhcsr_save
;
170 cortex_m3_clear_halt(target
);
175 static int cortex_m3_endreset_event(struct target
*target
)
179 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
180 struct swjdp_common
*swjdp
= &cortex_m3
->armv7m
.swjdp_info
;
181 struct cortex_m3_fp_comparator
*fp_list
= cortex_m3
->fp_comparator_list
;
182 struct cortex_m3_dwt_comparator
*dwt_list
= cortex_m3
->dwt_comparator_list
;
184 mem_ap_read_atomic_u32(swjdp
, DCB_DEMCR
, &dcb_demcr
);
185 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32
"",dcb_demcr
);
187 /* this regsiter is used for emulated dcc channel */
188 mem_ap_write_u32(swjdp
, DCB_DCRDR
, 0);
190 /* Enable debug requests */
191 mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
192 if (!(cortex_m3
->dcb_dhcsr
& C_DEBUGEN
))
193 mem_ap_write_u32(swjdp
, DCB_DHCSR
, DBGKEY
| C_DEBUGEN
);
195 /* clear any interrupt masking */
196 cortex_m3_write_debug_halt_mask(target
, 0, C_MASKINTS
);
198 /* Enable trace and dwt */
199 mem_ap_write_u32(swjdp
, DCB_DEMCR
, TRCENA
| VC_HARDERR
| VC_BUSERR
);
200 /* Monitor bus faults */
201 mem_ap_write_u32(swjdp
, NVIC_SHCSR
, SHCSR_BUSFAULTENA
);
204 target_write_u32(target
, FP_CTRL
, 3);
205 cortex_m3
->fpb_enabled
= 1;
207 /* Restore FPB registers */
208 for (i
= 0; i
< cortex_m3
->fp_num_code
+ cortex_m3
->fp_num_lit
; i
++)
210 target_write_u32(target
, fp_list
[i
].fpcr_address
, fp_list
[i
].fpcr_value
);
213 /* Restore DWT registers */
214 for (i
= 0; i
< cortex_m3
->dwt_num_comp
; i
++)
216 target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 0,
218 target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 4,
220 target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 8,
221 dwt_list
[i
].function
);
223 swjdp_transaction_endcheck(swjdp
);
225 armv7m_invalidate_core_regs(target
);
227 /* make sure we have latest dhcsr flags */
228 mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
233 static int cortex_m3_examine_debug_reason(struct target
*target
)
235 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
237 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason */
238 /* only check the debug reason if we don't know it already */
240 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
241 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
))
243 if (cortex_m3
->nvic_dfsr
& DFSR_BKPT
)
245 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
246 if (cortex_m3
->nvic_dfsr
& DFSR_DWTTRAP
)
247 target
->debug_reason
= DBG_REASON_WPTANDBKPT
;
249 else if (cortex_m3
->nvic_dfsr
& DFSR_DWTTRAP
)
250 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
251 else if (cortex_m3
->nvic_dfsr
& DFSR_VCATCH
)
252 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
253 else /* EXTERNAL, HALTED */
254 target
->debug_reason
= DBG_REASON_UNDEFINED
;
260 static int cortex_m3_examine_exception_reason(struct target
*target
)
262 uint32_t shcsr
, except_sr
, cfsr
= -1, except_ar
= -1;
263 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
264 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
266 mem_ap_read_u32(swjdp
, NVIC_SHCSR
, &shcsr
);
267 switch (armv7m
->exception_number
)
271 case 3: /* Hard Fault */
272 mem_ap_read_atomic_u32(swjdp
, NVIC_HFSR
, &except_sr
);
273 if (except_sr
& 0x40000000)
275 mem_ap_read_u32(swjdp
, NVIC_CFSR
, &cfsr
);
278 case 4: /* Memory Management */
279 mem_ap_read_u32(swjdp
, NVIC_CFSR
, &except_sr
);
280 mem_ap_read_u32(swjdp
, NVIC_MMFAR
, &except_ar
);
282 case 5: /* Bus Fault */
283 mem_ap_read_u32(swjdp
, NVIC_CFSR
, &except_sr
);
284 mem_ap_read_u32(swjdp
, NVIC_BFAR
, &except_ar
);
286 case 6: /* Usage Fault */
287 mem_ap_read_u32(swjdp
, NVIC_CFSR
, &except_sr
);
289 case 11: /* SVCall */
291 case 12: /* Debug Monitor */
292 mem_ap_read_u32(swjdp
, NVIC_DFSR
, &except_sr
);
294 case 14: /* PendSV */
296 case 15: /* SysTick */
302 swjdp_transaction_endcheck(swjdp
);
303 LOG_DEBUG("%s SHCSR 0x%" PRIx32
", SR 0x%" PRIx32
", CFSR 0x%" PRIx32
", AR 0x%" PRIx32
"", armv7m_exception_string(armv7m
->exception_number
), \
304 shcsr
, except_sr
, cfsr
, except_ar
);
308 static int cortex_m3_debug_entry(struct target
*target
)
313 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
314 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
315 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
319 cortex_m3_clear_halt(target
);
320 mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
322 if ((retval
= armv7m
->examine_debug_reason(target
)) != ERROR_OK
)
325 /* Examine target state and mode */
326 /* First load register acessible through core debug port*/
327 int num_regs
= armv7m
->core_cache
->num_regs
;
329 for (i
= 0; i
< num_regs
; i
++)
331 if (!armv7m
->core_cache
->reg_list
[i
].valid
)
332 armv7m
->read_core_reg(target
, i
);
335 xPSR
= buf_get_u32(armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].value
, 0, 32);
337 #ifdef ARMV7_GDB_HACKS
338 /* copy real xpsr reg for gdb, setting thumb bit */
339 buf_set_u32(armv7m_gdb_dummy_cpsr_value
, 0, 32, xPSR
);
340 buf_set_u32(armv7m_gdb_dummy_cpsr_value
, 5, 1, 1);
341 armv7m_gdb_dummy_cpsr_reg
.valid
= armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].valid
;
342 armv7m_gdb_dummy_cpsr_reg
.dirty
= armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].dirty
;
345 /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
348 armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].dirty
= armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].valid
;
349 cortex_m3_store_core_reg_u32(target
, ARMV7M_REGISTER_CORE_GP
, 16, xPSR
&~ 0xff);
352 /* Are we in an exception handler */
355 armv7m
->core_mode
= ARMV7M_MODE_HANDLER
;
356 armv7m
->exception_number
= (xPSR
& 0x1FF);
360 armv7m
->core_mode
= buf_get_u32(armv7m
->core_cache
->reg_list
[ARMV7M_CONTROL
].value
, 0, 1);
361 armv7m
->exception_number
= 0;
364 if (armv7m
->exception_number
)
366 cortex_m3_examine_exception_reason(target
);
369 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32
", target->state: %s",
370 armv7m_mode_strings
[armv7m
->core_mode
],
371 *(uint32_t*)(armv7m
->core_cache
->reg_list
[15].value
),
372 target_state_name(target
));
374 if (armv7m
->post_debug_entry
)
375 armv7m
->post_debug_entry(target
);
380 static int cortex_m3_poll(struct target
*target
)
383 enum target_state prev_target_state
= target
->state
;
384 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
385 struct swjdp_common
*swjdp
= &cortex_m3
->armv7m
.swjdp_info
;
387 /* Read from Debug Halting Control and Status Register */
388 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
389 if (retval
!= ERROR_OK
)
391 target
->state
= TARGET_UNKNOWN
;
395 if (cortex_m3
->dcb_dhcsr
& S_RESET_ST
)
397 /* check if still in reset */
398 mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
400 if (cortex_m3
->dcb_dhcsr
& S_RESET_ST
)
402 target
->state
= TARGET_RESET
;
407 if (target
->state
== TARGET_RESET
)
409 /* Cannot switch context while running so endreset is called with target->state == TARGET_RESET */
410 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32
"", cortex_m3
->dcb_dhcsr
);
411 cortex_m3_endreset_event(target
);
412 target
->state
= TARGET_RUNNING
;
413 prev_target_state
= TARGET_RUNNING
;
416 if (cortex_m3
->dcb_dhcsr
& S_HALT
)
418 target
->state
= TARGET_HALTED
;
420 if ((prev_target_state
== TARGET_RUNNING
) || (prev_target_state
== TARGET_RESET
))
422 if ((retval
= cortex_m3_debug_entry(target
)) != ERROR_OK
)
425 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
427 if (prev_target_state
== TARGET_DEBUG_RUNNING
)
430 if ((retval
= cortex_m3_debug_entry(target
)) != ERROR_OK
)
433 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
437 /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
438 * How best to model low power modes?
441 if (target
->state
== TARGET_UNKNOWN
)
443 /* check if processor is retiring instructions */
444 if (cortex_m3
->dcb_dhcsr
& S_RETIRE_ST
)
446 target
->state
= TARGET_RUNNING
;
454 static int cortex_m3_halt(struct target
*target
)
456 LOG_DEBUG("target->state: %s",
457 target_state_name(target
));
459 if (target
->state
== TARGET_HALTED
)
461 LOG_DEBUG("target was already halted");
465 if (target
->state
== TARGET_UNKNOWN
)
467 LOG_WARNING("target was in unknown state when halt was requested");
470 if (target
->state
== TARGET_RESET
)
472 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST
) && jtag_get_srst())
474 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
475 return ERROR_TARGET_FAILURE
;
479 /* we came here in a reset_halt or reset_init sequence
480 * debug entry was already prepared in cortex_m3_prepare_reset_halt()
482 target
->debug_reason
= DBG_REASON_DBGRQ
;
488 /* Write to Debug Halting Control and Status Register */
489 cortex_m3_write_debug_halt_mask(target
, C_HALT
, 0);
491 target
->debug_reason
= DBG_REASON_DBGRQ
;
496 static int cortex_m3_soft_reset_halt(struct target
*target
)
498 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
499 struct swjdp_common
*swjdp
= &cortex_m3
->armv7m
.swjdp_info
;
500 uint32_t dcb_dhcsr
= 0;
501 int retval
, timeout
= 0;
503 /* Enter debug state on reset, cf. end_reset_event() */
504 mem_ap_write_u32(swjdp
, DCB_DEMCR
, TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
506 /* Request a reset */
507 mem_ap_write_atomic_u32(swjdp
, NVIC_AIRCR
, AIRCR_VECTKEY
| AIRCR_VECTRESET
);
508 target
->state
= TARGET_RESET
;
510 /* registers are now invalid */
511 armv7m_invalidate_core_regs(target
);
513 while (timeout
< 100)
515 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &dcb_dhcsr
);
516 if (retval
== ERROR_OK
)
518 mem_ap_read_atomic_u32(swjdp
, NVIC_DFSR
, &cortex_m3
->nvic_dfsr
);
519 if ((dcb_dhcsr
& S_HALT
) && (cortex_m3
->nvic_dfsr
& DFSR_VCATCH
))
521 LOG_DEBUG("system reset-halted, dcb_dhcsr 0x%" PRIx32
", nvic_dfsr 0x%" PRIx32
"", dcb_dhcsr
, cortex_m3
->nvic_dfsr
);
522 cortex_m3_poll(target
);
526 LOG_DEBUG("waiting for system reset-halt, dcb_dhcsr 0x%" PRIx32
", %i ms", dcb_dhcsr
, timeout
);
535 static void cortex_m3_enable_breakpoints(struct target
*target
)
537 struct breakpoint
*breakpoint
= target
->breakpoints
;
539 /* set any pending breakpoints */
542 if (breakpoint
->set
== 0)
543 cortex_m3_set_breakpoint(target
, breakpoint
);
544 breakpoint
= breakpoint
->next
;
548 static int cortex_m3_resume(struct target
*target
, int current
,
549 uint32_t address
, int handle_breakpoints
, int debug_execution
)
551 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
552 struct breakpoint
*breakpoint
= NULL
;
555 if (target
->state
!= TARGET_HALTED
)
557 LOG_WARNING("target not halted");
558 return ERROR_TARGET_NOT_HALTED
;
561 if (!debug_execution
)
563 target_free_all_working_areas(target
);
564 cortex_m3_enable_breakpoints(target
);
565 cortex_m3_enable_watchpoints(target
);
570 /* Disable interrupts */
571 /* We disable interrupts in the PRIMASK register instead of masking with C_MASKINTS,
572 * This is probably the same issue as Cortex-M3 Errata 377493:
573 * C_MASKINTS in parallel with disabled interrupts can cause local faults to not be taken. */
574 buf_set_u32(armv7m
->core_cache
->reg_list
[ARMV7M_PRIMASK
].value
, 0, 32, 1);
575 armv7m
->core_cache
->reg_list
[ARMV7M_PRIMASK
].dirty
= 1;
576 armv7m
->core_cache
->reg_list
[ARMV7M_PRIMASK
].valid
= 1;
578 /* Make sure we are in Thumb mode */
579 buf_set_u32(armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].value
, 0, 32,
580 buf_get_u32(armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].value
, 0, 32) | (1 << 24));
581 armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].dirty
= 1;
582 armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].valid
= 1;
585 /* current = 1: continue on current pc, otherwise continue at <address> */
588 buf_set_u32(armv7m
->core_cache
->reg_list
[15].value
, 0, 32, address
);
589 armv7m
->core_cache
->reg_list
[15].dirty
= 1;
590 armv7m
->core_cache
->reg_list
[15].valid
= 1;
593 resume_pc
= buf_get_u32(armv7m
->core_cache
->reg_list
[15].value
, 0, 32);
595 armv7m_restore_context(target
);
597 /* the front-end may request us not to handle breakpoints */
598 if (handle_breakpoints
)
600 /* Single step past breakpoint at current address */
601 if ((breakpoint
= breakpoint_find(target
, resume_pc
)))
603 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32
" (ID: %d)",
605 breakpoint
->unique_id
);
606 cortex_m3_unset_breakpoint(target
, breakpoint
);
607 cortex_m3_single_step_core(target
);
608 cortex_m3_set_breakpoint(target
, breakpoint
);
613 cortex_m3_write_debug_halt_mask(target
, 0, C_HALT
);
615 target
->debug_reason
= DBG_REASON_NOTHALTED
;
617 /* registers are now invalid */
618 armv7m_invalidate_core_regs(target
);
619 if (!debug_execution
)
621 target
->state
= TARGET_RUNNING
;
622 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
623 LOG_DEBUG("target resumed at 0x%" PRIx32
"", resume_pc
);
627 target
->state
= TARGET_DEBUG_RUNNING
;
628 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
629 LOG_DEBUG("target debug resumed at 0x%" PRIx32
"", resume_pc
);
635 /* int irqstepcount = 0; */
636 static int cortex_m3_step(struct target
*target
, int current
,
637 uint32_t address
, int handle_breakpoints
)
639 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
640 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
641 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
642 struct breakpoint
*breakpoint
= NULL
;
644 if (target
->state
!= TARGET_HALTED
)
646 LOG_WARNING("target not halted");
647 return ERROR_TARGET_NOT_HALTED
;
650 /* current = 1: continue on current pc, otherwise continue at <address> */
652 buf_set_u32(cortex_m3
->armv7m
.core_cache
->reg_list
[15].value
,
655 /* the front-end may request us not to handle breakpoints */
656 if (handle_breakpoints
) {
657 breakpoint
= breakpoint_find(target
, buf_get_u32(armv7m
658 ->core_cache
->reg_list
[15].value
, 0, 32));
660 cortex_m3_unset_breakpoint(target
, breakpoint
);
663 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
665 armv7m_restore_context(target
);
667 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
669 /* set step and clear halt */
670 cortex_m3_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
671 mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
673 /* registers are now invalid */
674 armv7m_invalidate_core_regs(target
);
677 cortex_m3_set_breakpoint(target
, breakpoint
);
679 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
" nvic_icsr = 0x%" PRIx32
"", cortex_m3
->dcb_dhcsr
, cortex_m3
->nvic_icsr
);
681 cortex_m3_debug_entry(target
);
682 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
684 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
" nvic_icsr = 0x%" PRIx32
"", cortex_m3
->dcb_dhcsr
, cortex_m3
->nvic_icsr
);
688 static int cortex_m3_assert_reset(struct target
*target
)
690 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
691 struct swjdp_common
*swjdp
= &cortex_m3
->armv7m
.swjdp_info
;
694 LOG_DEBUG("target->state: %s",
695 target_state_name(target
));
697 enum reset_types jtag_reset_config
= jtag_get_reset_config();
700 * We can reset Cortex-M3 targets using just the NVIC without
701 * requiring SRST, getting a SoC reset (or a core-only reset)
702 * instead of a system reset.
704 if (!(jtag_reset_config
& RESET_HAS_SRST
))
707 /* Enable debug requests */
708 mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m3
->dcb_dhcsr
);
709 if (!(cortex_m3
->dcb_dhcsr
& C_DEBUGEN
))
710 mem_ap_write_u32(swjdp
, DCB_DHCSR
, DBGKEY
| C_DEBUGEN
);
712 mem_ap_write_u32(swjdp
, DCB_DCRDR
, 0);
714 if (!target
->reset_halt
)
716 /* Set/Clear C_MASKINTS in a separate operation */
717 if (cortex_m3
->dcb_dhcsr
& C_MASKINTS
)
718 mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
, DBGKEY
| C_DEBUGEN
| C_HALT
);
720 /* clear any debug flags before resuming */
721 cortex_m3_clear_halt(target
);
723 /* clear C_HALT in dhcsr reg */
724 cortex_m3_write_debug_halt_mask(target
, 0, C_HALT
);
726 /* Enter debug state on reset, cf. end_reset_event() */
727 mem_ap_write_u32(swjdp
, DCB_DEMCR
, TRCENA
| VC_HARDERR
| VC_BUSERR
);
731 /* Enter debug state on reset, cf. end_reset_event() */
732 mem_ap_write_atomic_u32(swjdp
, DCB_DEMCR
, TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
736 * When nRST is asserted on most Stellaris devices, it clears some of
737 * the debug state. The ARMv7M and Cortex-M3 TRMs say that's wrong;
738 * and OpenOCD depends on those TRMs. So we won't use SRST on those
739 * chips. (Only power-on reset should affect debug state, beyond a
740 * few specified bits; not the chip's nRST input, wired to SRST.)
742 * REVISIT current errata specs don't seem to cover this issue.
743 * Do we have more details than this email?
744 * https://lists.berlios.de/pipermail
745 * /openocd-development/2008-August/003065.html
747 if (strcmp(target
->variant
, "lm3s") == 0)
749 /* Check for silicon revisions with the issue. */
752 if (target_read_u32(target
, 0x400fe000, &did0
) == ERROR_OK
)
754 switch ((did0
>> 16) & 0xff)
757 /* all Sandstorm suffer issue */
763 /* Fury and DustDevil rev A have
764 * this nRST problem. It should
765 * be fixed in rev B silicon.
767 if (((did0
>> 8) & 0xff) == 0)
771 /* Tempest should be fine. */
779 /* default to asserting srst */
780 if (jtag_reset_config
& RESET_SRST_PULLS_TRST
)
782 jtag_add_reset(1, 1);
786 jtag_add_reset(0, 1);
791 /* Use a standard Cortex-M3 software reset mechanism.
792 * SYSRESETREQ will reset SoC peripherals outside the
793 * core, like watchdog timers, if the SoC wires it up
794 * correctly. Else VECRESET can reset just the core.
796 mem_ap_write_atomic_u32(swjdp
, NVIC_AIRCR
,
797 AIRCR_VECTKEY
| AIRCR_SYSRESETREQ
);
798 LOG_DEBUG("Using Cortex-M3 SYSRESETREQ");
801 /* I do not know why this is necessary, but it
802 * fixes strange effects (step/resume cause NMI
803 * after reset) on LM3S6918 -- Michael Schwingen
806 mem_ap_read_atomic_u32(swjdp
, NVIC_AIRCR
, &tmp
);
810 target
->state
= TARGET_RESET
;
811 jtag_add_sleep(50000);
813 armv7m_invalidate_core_regs(target
);
815 if (target
->reset_halt
)
818 if ((retval
= target_halt(target
)) != ERROR_OK
)
825 static int cortex_m3_deassert_reset(struct target
*target
)
827 LOG_DEBUG("target->state: %s",
828 target_state_name(target
));
830 /* deassert reset lines */
831 jtag_add_reset(0, 0);
837 cortex_m3_set_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
842 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
843 struct cortex_m3_fp_comparator
*comparator_list
= cortex_m3
->fp_comparator_list
;
847 LOG_WARNING("breakpoint (BPID: %d) already set", breakpoint
->unique_id
);
851 if (cortex_m3
->auto_bp_type
)
853 breakpoint
->type
= (breakpoint
->address
< 0x20000000) ? BKPT_HARD
: BKPT_SOFT
;
856 if (breakpoint
->type
== BKPT_HARD
)
858 while (comparator_list
[fp_num
].used
&& (fp_num
< cortex_m3
->fp_num_code
))
860 if (fp_num
>= cortex_m3
->fp_num_code
)
862 LOG_DEBUG("ERROR Can not find free FP Comparator");
863 LOG_WARNING("ERROR Can not find free FP Comparator");
866 breakpoint
->set
= fp_num
+ 1;
867 hilo
= (breakpoint
->address
& 0x2) ? FPCR_REPLACE_BKPT_HIGH
: FPCR_REPLACE_BKPT_LOW
;
868 comparator_list
[fp_num
].used
= 1;
869 comparator_list
[fp_num
].fpcr_value
= (breakpoint
->address
& 0x1FFFFFFC) | hilo
| 1;
870 target_write_u32(target
, comparator_list
[fp_num
].fpcr_address
, comparator_list
[fp_num
].fpcr_value
);
871 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32
"", fp_num
, comparator_list
[fp_num
].fpcr_value
);
872 if (!cortex_m3
->fpb_enabled
)
874 LOG_DEBUG("FPB wasn't enabled, do it now");
875 target_write_u32(target
, FP_CTRL
, 3);
878 else if (breakpoint
->type
== BKPT_SOFT
)
881 buf_set_u32(code
, 0, 32, ARMV7M_T_BKPT(0x11));
882 if ((retval
= target_read_memory(target
, breakpoint
->address
& 0xFFFFFFFE, breakpoint
->length
, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
886 if ((retval
= target_write_memory(target
, breakpoint
->address
& 0xFFFFFFFE, breakpoint
->length
, 1, code
)) != ERROR_OK
)
890 breakpoint
->set
= 0x11; /* Any nice value but 0 */
893 LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32
" Length: %d (set=%d)",
894 breakpoint
->unique_id
,
895 (int)(breakpoint
->type
),
904 cortex_m3_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
907 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
908 struct cortex_m3_fp_comparator
* comparator_list
= cortex_m3
->fp_comparator_list
;
910 if (!breakpoint
->set
)
912 LOG_WARNING("breakpoint not set");
916 LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32
" Length: %d (set=%d)",
917 breakpoint
->unique_id
,
918 (int)(breakpoint
->type
),
923 if (breakpoint
->type
== BKPT_HARD
)
925 int fp_num
= breakpoint
->set
- 1;
926 if ((fp_num
< 0) || (fp_num
>= cortex_m3
->fp_num_code
))
928 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
931 comparator_list
[fp_num
].used
= 0;
932 comparator_list
[fp_num
].fpcr_value
= 0;
933 target_write_u32(target
, comparator_list
[fp_num
].fpcr_address
, comparator_list
[fp_num
].fpcr_value
);
937 /* restore original instruction (kept in target endianness) */
938 if (breakpoint
->length
== 4)
940 if ((retval
= target_write_memory(target
, breakpoint
->address
& 0xFFFFFFFE, 4, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
947 if ((retval
= target_write_memory(target
, breakpoint
->address
& 0xFFFFFFFE, 2, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
959 cortex_m3_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
961 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
963 if (cortex_m3
->auto_bp_type
)
965 breakpoint
->type
= (breakpoint
->address
< 0x20000000) ? BKPT_HARD
: BKPT_SOFT
;
966 #ifdef ARMV7_GDB_HACKS
967 if (breakpoint
->length
!= 2) {
968 /* XXX Hack: Replace all breakpoints with length != 2 with
969 * a hardware breakpoint. */
970 breakpoint
->type
= BKPT_HARD
;
971 breakpoint
->length
= 2;
976 if ((breakpoint
->type
== BKPT_HARD
) && (breakpoint
->address
>= 0x20000000))
978 LOG_INFO("flash patch comparator requested outside code memory region");
979 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
982 if ((breakpoint
->type
== BKPT_SOFT
) && (breakpoint
->address
< 0x20000000))
984 LOG_INFO("soft breakpoint requested in code (flash) memory region");
985 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
988 if ((breakpoint
->type
== BKPT_HARD
) && (cortex_m3
->fp_code_available
< 1))
990 LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
991 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
994 if ((breakpoint
->length
!= 2))
996 LOG_INFO("only breakpoints of two bytes length supported");
997 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1000 if (breakpoint
->type
== BKPT_HARD
)
1001 cortex_m3
->fp_code_available
--;
1002 cortex_m3_set_breakpoint(target
, breakpoint
);
1008 cortex_m3_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1010 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1012 /* REVISIT why check? FBP can be updated with core running ... */
1013 if (target
->state
!= TARGET_HALTED
)
1015 LOG_WARNING("target not halted");
1016 return ERROR_TARGET_NOT_HALTED
;
1019 if (cortex_m3
->auto_bp_type
)
1021 breakpoint
->type
= (breakpoint
->address
< 0x20000000) ? BKPT_HARD
: BKPT_SOFT
;
1024 if (breakpoint
->set
)
1026 cortex_m3_unset_breakpoint(target
, breakpoint
);
1029 if (breakpoint
->type
== BKPT_HARD
)
1030 cortex_m3
->fp_code_available
++;
1036 cortex_m3_set_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1039 uint32_t mask
, temp
;
1040 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1042 /* watchpoint params were validated earlier */
1044 temp
= watchpoint
->length
;
1051 /* REVISIT Don't fully trust these "not used" records ... users
1052 * may set up breakpoints by hand, e.g. dual-address data value
1053 * watchpoint using comparator #1; comparator #0 matching cycle
1054 * count; send data trace info through ITM and TPIU; etc
1056 struct cortex_m3_dwt_comparator
*comparator
;
1058 for (comparator
= cortex_m3
->dwt_comparator_list
;
1059 comparator
->used
&& dwt_num
< cortex_m3
->dwt_num_comp
;
1060 comparator
++, dwt_num
++)
1062 if (dwt_num
>= cortex_m3
->dwt_num_comp
)
1064 LOG_ERROR("Can not find free DWT Comparator");
1067 comparator
->used
= 1;
1068 watchpoint
->set
= dwt_num
+ 1;
1070 comparator
->comp
= watchpoint
->address
;
1071 target_write_u32(target
, comparator
->dwt_comparator_address
+ 0,
1074 comparator
->mask
= mask
;
1075 target_write_u32(target
, comparator
->dwt_comparator_address
+ 4,
1078 switch (watchpoint
->rw
) {
1080 comparator
->function
= 5;
1083 comparator
->function
= 6;
1086 comparator
->function
= 7;
1089 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8,
1090 comparator
->function
);
1092 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1093 watchpoint
->unique_id
, dwt_num
,
1094 (unsigned) comparator
->comp
,
1095 (unsigned) comparator
->mask
,
1096 (unsigned) comparator
->function
);
1101 cortex_m3_unset_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1103 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1104 struct cortex_m3_dwt_comparator
*comparator
;
1107 if (!watchpoint
->set
)
1109 LOG_WARNING("watchpoint (wpid: %d) not set",
1110 watchpoint
->unique_id
);
1114 dwt_num
= watchpoint
->set
- 1;
1116 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1117 watchpoint
->unique_id
, dwt_num
,
1118 (unsigned) watchpoint
->address
);
1120 if ((dwt_num
< 0) || (dwt_num
>= cortex_m3
->dwt_num_comp
))
1122 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1126 comparator
= cortex_m3
->dwt_comparator_list
+ dwt_num
;
1127 comparator
->used
= 0;
1128 comparator
->function
= 0;
1129 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8,
1130 comparator
->function
);
1132 watchpoint
->set
= 0;
1138 cortex_m3_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1140 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1142 /* REVISIT why check? DWT can be updated with core running ... */
1143 if (target
->state
!= TARGET_HALTED
)
1145 LOG_WARNING("target not halted");
1146 return ERROR_TARGET_NOT_HALTED
;
1149 if (cortex_m3
->dwt_comp_available
< 1)
1151 LOG_DEBUG("no comparators?");
1152 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1155 /* hardware doesn't support data value masking */
1156 if (watchpoint
->mask
!= ~(uint32_t)0) {
1157 LOG_DEBUG("watchpoint value masks not supported");
1158 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1161 /* hardware allows address masks of up to 32K */
1164 for (mask
= 0; mask
< 16; mask
++) {
1165 if ((1u << mask
) == watchpoint
->length
)
1169 LOG_DEBUG("unsupported watchpoint length");
1170 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1172 if (watchpoint
->address
& ((1 << mask
) - 1)) {
1173 LOG_DEBUG("watchpoint address is unaligned");
1174 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1177 /* Caller doesn't seem to be able to describe watching for data
1178 * values of zero; that flags "no value".
1180 * REVISIT This DWT may well be able to watch for specific data
1181 * values. Requires comparator #1 to set DATAVMATCH and match
1182 * the data, and another comparator (DATAVADDR0) matching addr.
1184 if (watchpoint
->value
) {
1185 LOG_DEBUG("data value watchpoint not YET supported");
1186 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1189 cortex_m3
->dwt_comp_available
--;
1190 LOG_DEBUG("dwt_comp_available: %d", cortex_m3
->dwt_comp_available
);
1196 cortex_m3_remove_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1198 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1200 /* REVISIT why check? DWT can be updated with core running ... */
1201 if (target
->state
!= TARGET_HALTED
)
1203 LOG_WARNING("target not halted");
1204 return ERROR_TARGET_NOT_HALTED
;
1207 if (watchpoint
->set
)
1209 cortex_m3_unset_watchpoint(target
, watchpoint
);
1212 cortex_m3
->dwt_comp_available
++;
1213 LOG_DEBUG("dwt_comp_available: %d", cortex_m3
->dwt_comp_available
);
1218 static void cortex_m3_enable_watchpoints(struct target
*target
)
1220 struct watchpoint
*watchpoint
= target
->watchpoints
;
1222 /* set any pending watchpoints */
1225 if (watchpoint
->set
== 0)
1226 cortex_m3_set_watchpoint(target
, watchpoint
);
1227 watchpoint
= watchpoint
->next
;
1231 static int cortex_m3_load_core_reg_u32(struct target
*target
,
1232 enum armv7m_regtype type
, uint32_t num
, uint32_t * value
)
1235 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1236 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
1238 /* NOTE: we "know" here that the register identifiers used
1239 * in the v7m header match the Cortex-M3 Debug Core Register
1240 * Selector values for R0..R15, xPSR, MSP, and PSP.
1244 /* read a normal core register */
1245 retval
= cortexm3_dap_read_coreregister_u32(swjdp
, value
, num
);
1247 if (retval
!= ERROR_OK
)
1249 LOG_ERROR("JTAG failure %i",retval
);
1250 return ERROR_JTAG_DEVICE_ERROR
;
1252 LOG_DEBUG("load from core reg %i value 0x%" PRIx32
"",(int)num
,*value
);
1255 case ARMV7M_PRIMASK
:
1256 case ARMV7M_BASEPRI
:
1257 case ARMV7M_FAULTMASK
:
1258 case ARMV7M_CONTROL
:
1259 /* Cortex-M3 packages these four registers as bitfields
1260 * in one Debug Core register. So say r0 and r2 docs;
1261 * it was removed from r1 docs, but still works.
1263 cortexm3_dap_read_coreregister_u32(swjdp
, value
, 20);
1267 case ARMV7M_PRIMASK
:
1268 *value
= buf_get_u32((uint8_t*)value
, 0, 1);
1271 case ARMV7M_BASEPRI
:
1272 *value
= buf_get_u32((uint8_t*)value
, 8, 8);
1275 case ARMV7M_FAULTMASK
:
1276 *value
= buf_get_u32((uint8_t*)value
, 16, 1);
1279 case ARMV7M_CONTROL
:
1280 *value
= buf_get_u32((uint8_t*)value
, 24, 2);
1284 LOG_DEBUG("load from special reg %i value 0x%" PRIx32
"", (int)num
, *value
);
1288 return ERROR_INVALID_ARGUMENTS
;
1294 static int cortex_m3_store_core_reg_u32(struct target
*target
,
1295 enum armv7m_regtype type
, uint32_t num
, uint32_t value
)
1299 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1300 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
1302 #ifdef ARMV7_GDB_HACKS
1303 /* If the LR register is being modified, make sure it will put us
1304 * in "thumb" mode, or an INVSTATE exception will occur. This is a
1305 * hack to deal with the fact that gdb will sometimes "forge"
1306 * return addresses, and doesn't set the LSB correctly (i.e., when
1307 * printing expressions containing function calls, it sets LR = 0.)
1308 * Valid exception return codes have bit 0 set too.
1310 if (num
== ARMV7M_R14
)
1314 /* NOTE: we "know" here that the register identifiers used
1315 * in the v7m header match the Cortex-M3 Debug Core Register
1316 * Selector values for R0..R15, xPSR, MSP, and PSP.
1320 retval
= cortexm3_dap_write_coreregister_u32(swjdp
, value
, num
);
1321 if (retval
!= ERROR_OK
)
1323 LOG_ERROR("JTAG failure %i", retval
);
1324 armv7m
->core_cache
->reg_list
[num
].dirty
= armv7m
->core_cache
->reg_list
[num
].valid
;
1325 return ERROR_JTAG_DEVICE_ERROR
;
1327 LOG_DEBUG("write core reg %i value 0x%" PRIx32
"", (int)num
, value
);
1330 case ARMV7M_PRIMASK
:
1331 case ARMV7M_BASEPRI
:
1332 case ARMV7M_FAULTMASK
:
1333 case ARMV7M_CONTROL
:
1334 /* Cortex-M3 packages these four registers as bitfields
1335 * in one Debug Core register. So say r0 and r2 docs;
1336 * it was removed from r1 docs, but still works.
1338 cortexm3_dap_read_coreregister_u32(swjdp
, ®
, 20);
1342 case ARMV7M_PRIMASK
:
1343 buf_set_u32((uint8_t*)®
, 0, 1, value
);
1346 case ARMV7M_BASEPRI
:
1347 buf_set_u32((uint8_t*)®
, 8, 8, value
);
1350 case ARMV7M_FAULTMASK
:
1351 buf_set_u32((uint8_t*)®
, 16, 1, value
);
1354 case ARMV7M_CONTROL
:
1355 buf_set_u32((uint8_t*)®
, 24, 2, value
);
1359 cortexm3_dap_write_coreregister_u32(swjdp
, reg
, 20);
1361 LOG_DEBUG("write special reg %i value 0x%" PRIx32
" ", (int)num
, value
);
1365 return ERROR_INVALID_ARGUMENTS
;
1371 static int cortex_m3_read_memory(struct target
*target
, uint32_t address
,
1372 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1374 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1375 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
1378 /* sanitize arguments */
1379 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
1380 return ERROR_INVALID_ARGUMENTS
;
1382 /* cortex_m3 handles unaligned memory access */
1387 retval
= mem_ap_read_buf_u32(swjdp
, buffer
, 4 * count
, address
);
1390 retval
= mem_ap_read_buf_u16(swjdp
, buffer
, 2 * count
, address
);
1393 retval
= mem_ap_read_buf_u8(swjdp
, buffer
, count
, address
);
1396 LOG_ERROR("BUG: we shouldn't get here");
1403 static int cortex_m3_write_memory(struct target
*target
, uint32_t address
,
1404 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1406 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1407 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
1410 /* sanitize arguments */
1411 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
1412 return ERROR_INVALID_ARGUMENTS
;
1417 retval
= mem_ap_write_buf_u32(swjdp
, buffer
, 4 * count
, address
);
1420 retval
= mem_ap_write_buf_u16(swjdp
, buffer
, 2 * count
, address
);
1423 retval
= mem_ap_write_buf_u8(swjdp
, buffer
, count
, address
);
1426 LOG_ERROR("BUG: we shouldn't get here");
1433 static int cortex_m3_bulk_write_memory(struct target
*target
, uint32_t address
,
1434 uint32_t count
, uint8_t *buffer
)
1436 return cortex_m3_write_memory(target
, address
, 4, count
, buffer
);
1439 static int cortex_m3_init_target(struct command_context
*cmd_ctx
,
1440 struct target
*target
)
1442 armv7m_build_reg_cache(target
);
1446 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1447 * on r/w if the core is not running, and clear on resume or reset ... or
1448 * at least, in a post_restore_context() method.
1451 struct dwt_reg_state
{
1452 struct target
*target
;
1454 uint32_t value
; /* scratch/cache */
1457 static int cortex_m3_dwt_get_reg(struct reg
*reg
)
1459 struct dwt_reg_state
*state
= reg
->arch_info
;
1461 return target_read_u32(state
->target
, state
->addr
, &state
->value
);
1464 static int cortex_m3_dwt_set_reg(struct reg
*reg
, uint8_t *buf
)
1466 struct dwt_reg_state
*state
= reg
->arch_info
;
1468 return target_write_u32(state
->target
, state
->addr
,
1469 buf_get_u32(buf
, 0, reg
->size
));
1478 static struct dwt_reg dwt_base_regs
[] = {
1479 { DWT_CTRL
, "dwt_ctrl", 32, },
1480 { DWT_CYCCNT
, "dwt_cyccnt", 32, },
1481 /* plus some 8 bit counters, useful for profiling with TPIU */
1484 static struct dwt_reg dwt_comp
[] = {
1485 #define DWT_COMPARATOR(i) \
1486 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1487 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1488 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1493 #undef DWT_COMPARATOR
1496 static int dwt_reg_type
= -1;
1499 cortex_m3_dwt_addreg(struct target
*t
, struct reg
*r
, struct dwt_reg
*d
)
1501 struct dwt_reg_state
*state
;
1503 state
= calloc(1, sizeof *state
);
1506 state
->addr
= d
->addr
;
1511 r
->value
= &state
->value
;
1512 r
->arch_info
= state
;
1513 r
->arch_type
= dwt_reg_type
;
1517 cortex_m3_dwt_setup(struct cortex_m3_common
*cm3
, struct target
*target
)
1520 struct reg_cache
*cache
;
1521 struct cortex_m3_dwt_comparator
*comparator
;
1524 target_read_u32(target
, DWT_CTRL
, &dwtcr
);
1526 LOG_DEBUG("no DWT");
1530 if (dwt_reg_type
< 0)
1531 dwt_reg_type
= register_reg_arch_type(cortex_m3_dwt_get_reg
,
1532 cortex_m3_dwt_set_reg
);
1534 cm3
->dwt_num_comp
= (dwtcr
>> 28) & 0xF;
1535 cm3
->dwt_comp_available
= cm3
->dwt_num_comp
;
1536 cm3
->dwt_comparator_list
= calloc(cm3
->dwt_num_comp
,
1537 sizeof(struct cortex_m3_dwt_comparator
));
1538 if (!cm3
->dwt_comparator_list
) {
1540 cm3
->dwt_num_comp
= 0;
1541 LOG_ERROR("out of mem");
1545 cache
= calloc(1, sizeof *cache
);
1548 free(cm3
->dwt_comparator_list
);
1551 cache
->name
= "cortex-m3 dwt registers";
1552 cache
->num_regs
= 2 + cm3
->dwt_num_comp
* 3;
1553 cache
->reg_list
= calloc(cache
->num_regs
, sizeof *cache
->reg_list
);
1554 if (!cache
->reg_list
) {
1559 for (reg
= 0; reg
< 2; reg
++)
1560 cortex_m3_dwt_addreg(target
, cache
->reg_list
+ reg
,
1561 dwt_base_regs
+ reg
);
1563 comparator
= cm3
->dwt_comparator_list
;
1564 for (i
= 0; i
< cm3
->dwt_num_comp
; i
++, comparator
++) {
1567 comparator
->dwt_comparator_address
= DWT_COMP0
+ 0x10 * i
;
1568 for (j
= 0; j
< 3; j
++, reg
++)
1569 cortex_m3_dwt_addreg(target
, cache
->reg_list
+ reg
,
1570 dwt_comp
+ 3 * i
+ j
);
1573 *register_get_last_cache_p(&target
->reg_cache
) = cache
;
1574 cm3
->dwt_cache
= cache
;
1576 LOG_DEBUG("DWT dwtcr 0x%" PRIx32
", comp %d, watch%s",
1577 dwtcr
, cm3
->dwt_num_comp
,
1578 (dwtcr
& (0xf << 24)) ? " only" : "/trigger");
1580 /* REVISIT: if num_comp > 1, check whether comparator #1 can
1581 * implement single-address data value watchpoints ... so we
1582 * won't need to check it later, when asked to set one up.
1586 static int cortex_m3_examine(struct target
*target
)
1589 uint32_t cpuid
, fpcr
;
1591 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1592 struct swjdp_common
*swjdp
= &cortex_m3
->armv7m
.swjdp_info
;
1594 if ((retval
= ahbap_debugport_init(swjdp
)) != ERROR_OK
)
1597 if (!target_was_examined(target
))
1599 target_set_examined(target
);
1601 /* Read from Device Identification Registers */
1602 retval
= target_read_u32(target
, CPUID
, &cpuid
);
1603 if (retval
!= ERROR_OK
)
1606 if (((cpuid
>> 4) & 0xc3f) == 0xc23)
1607 LOG_DEBUG("CORTEX-M3 processor detected");
1608 LOG_DEBUG("cpuid: 0x%8.8" PRIx32
"", cpuid
);
1610 /* NOTE: FPB and DWT are both optional. */
1613 target_read_u32(target
, FP_CTRL
, &fpcr
);
1614 cortex_m3
->auto_bp_type
= 1;
1615 cortex_m3
->fp_num_code
= ((fpcr
>> 8) & 0x70) | ((fpcr
>> 4) & 0xF); /* bits [14:12] and [7:4] */
1616 cortex_m3
->fp_num_lit
= (fpcr
>> 8) & 0xF;
1617 cortex_m3
->fp_code_available
= cortex_m3
->fp_num_code
;
1618 cortex_m3
->fp_comparator_list
= calloc(cortex_m3
->fp_num_code
+ cortex_m3
->fp_num_lit
, sizeof(struct cortex_m3_fp_comparator
));
1619 cortex_m3
->fpb_enabled
= fpcr
& 1;
1620 for (i
= 0; i
< cortex_m3
->fp_num_code
+ cortex_m3
->fp_num_lit
; i
++)
1622 cortex_m3
->fp_comparator_list
[i
].type
= (i
< cortex_m3
->fp_num_code
) ? FPCR_CODE
: FPCR_LITERAL
;
1623 cortex_m3
->fp_comparator_list
[i
].fpcr_address
= FP_COMP0
+ 4 * i
;
1625 LOG_DEBUG("FPB fpcr 0x%" PRIx32
", numcode %i, numlit %i", fpcr
, cortex_m3
->fp_num_code
, cortex_m3
->fp_num_lit
);
1628 cortex_m3_dwt_setup(cortex_m3
, target
);
1634 static int cortex_m3_dcc_read(struct swjdp_common
*swjdp
, uint8_t *value
, uint8_t *ctrl
)
1638 mem_ap_read_buf_u16(swjdp
, (uint8_t*)&dcrdr
, 1, DCB_DCRDR
);
1639 *ctrl
= (uint8_t)dcrdr
;
1640 *value
= (uint8_t)(dcrdr
>> 8);
1642 LOG_DEBUG("data 0x%x ctrl 0x%x", *value
, *ctrl
);
1644 /* write ack back to software dcc register
1645 * signify we have read data */
1646 if (dcrdr
& (1 << 0))
1649 mem_ap_write_buf_u16(swjdp
, (uint8_t*)&dcrdr
, 1, DCB_DCRDR
);
1655 static int cortex_m3_target_request_data(struct target
*target
,
1656 uint32_t size
, uint8_t *buffer
)
1658 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1659 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
1664 for (i
= 0; i
< (size
* 4); i
++)
1666 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1673 static int cortex_m3_handle_target_request(void *priv
)
1675 struct target
*target
= priv
;
1676 if (!target_was_examined(target
))
1678 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1679 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
1681 if (!target
->dbg_msg_enabled
)
1684 if (target
->state
== TARGET_RUNNING
)
1689 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1691 /* check if we have data */
1692 if (ctrl
& (1 << 0))
1696 /* we assume target is quick enough */
1698 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1699 request
|= (data
<< 8);
1700 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1701 request
|= (data
<< 16);
1702 cortex_m3_dcc_read(swjdp
, &data
, &ctrl
);
1703 request
|= (data
<< 24);
1704 target_request(target
, request
);
1711 static int cortex_m3_init_arch_info(struct target
*target
,
1712 struct cortex_m3_common
*cortex_m3
, struct jtag_tap
*tap
)
1715 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
1717 armv7m_init_arch_info(target
, armv7m
);
1719 /* prepare JTAG information for the new target */
1720 cortex_m3
->jtag_info
.tap
= tap
;
1721 cortex_m3
->jtag_info
.scann_size
= 4;
1723 armv7m
->swjdp_info
.dp_select_value
= -1;
1724 armv7m
->swjdp_info
.ap_csw_value
= -1;
1725 armv7m
->swjdp_info
.ap_tar_value
= -1;
1726 armv7m
->swjdp_info
.jtag_info
= &cortex_m3
->jtag_info
;
1727 armv7m
->swjdp_info
.memaccess_tck
= 8;
1728 armv7m
->swjdp_info
.tar_autoincr_block
= (1 << 12); /* Cortex-M3 has 4096 bytes autoincrement range */
1730 /* register arch-specific functions */
1731 armv7m
->examine_debug_reason
= cortex_m3_examine_debug_reason
;
1733 armv7m
->post_debug_entry
= NULL
;
1735 armv7m
->pre_restore_context
= NULL
;
1736 armv7m
->post_restore_context
= NULL
;
1738 armv7m
->load_core_reg_u32
= cortex_m3_load_core_reg_u32
;
1739 armv7m
->store_core_reg_u32
= cortex_m3_store_core_reg_u32
;
1741 target_register_timer_callback(cortex_m3_handle_target_request
, 1, 1, target
);
1743 if ((retval
= arm_jtag_setup_connection(&cortex_m3
->jtag_info
)) != ERROR_OK
)
1751 static int cortex_m3_target_create(struct target
*target
, Jim_Interp
*interp
)
1753 struct cortex_m3_common
*cortex_m3
= calloc(1,sizeof(struct cortex_m3_common
));
1755 cortex_m3
->common_magic
= CORTEX_M3_COMMON_MAGIC
;
1756 cortex_m3_init_arch_info(target
, cortex_m3
, target
->tap
);
1761 /*--------------------------------------------------------------------------*/
1763 static int cortex_m3_verify_pointer(struct command_context
*cmd_ctx
,
1764 struct cortex_m3_common
*cm3
)
1766 if (cm3
->common_magic
!= CORTEX_M3_COMMON_MAGIC
) {
1767 command_print(cmd_ctx
, "target is not a Cortex-M3");
1768 return ERROR_TARGET_INVALID
;
1774 * Only stuff below this line should need to verify that its target
1775 * is a Cortex-M3. Everything else should have indirected through the
1776 * cortexm3_target structure, which is only used with CM3 targets.
1780 * REVISIT Thumb2 disassembly should work for all ARMv7 cores, as well
1781 * as at least ARM-1156T2. The interesting thing about Cortex-M is
1782 * that *only* Thumb2 disassembly matters. There are also some small
1783 * additions to Thumb2 that are specific to ARMv7-M.
1785 COMMAND_HANDLER(handle_cortex_m3_disassemble_command
)
1788 struct target
*target
= get_current_target(cmd_ctx
);
1789 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1791 unsigned long count
= 1;
1792 struct arm_instruction cur_instruction
;
1794 retval
= cortex_m3_verify_pointer(cmd_ctx
, cortex_m3
);
1795 if (retval
!= ERROR_OK
)
1801 COMMAND_PARSE_NUMBER(ulong
, args
[1], count
);
1804 COMMAND_PARSE_NUMBER(u32
, args
[0], address
);
1807 command_print(cmd_ctx
,
1808 "usage: cortex_m3 disassemble <address> [<count>]");
1813 retval
= thumb2_opcode(target
, address
, &cur_instruction
);
1814 if (retval
!= ERROR_OK
)
1816 command_print(cmd_ctx
, "%s", cur_instruction
.text
);
1817 address
+= cur_instruction
.instruction_size
;
1823 static const struct {
1827 { "hard_err", VC_HARDERR
, },
1828 { "int_err", VC_INTERR
, },
1829 { "bus_err", VC_BUSERR
, },
1830 { "state_err", VC_STATERR
, },
1831 { "chk_err", VC_CHKERR
, },
1832 { "nocp_err", VC_NOCPERR
, },
1833 { "mm_err", VC_MMERR
, },
1834 { "reset", VC_CORERESET
, },
1837 COMMAND_HANDLER(handle_cortex_m3_vector_catch_command
)
1839 struct target
*target
= get_current_target(cmd_ctx
);
1840 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1841 struct armv7m_common
*armv7m
= &cortex_m3
->armv7m
;
1842 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
1847 retval
= cortex_m3_verify_pointer(cmd_ctx
, cortex_m3
);
1848 if (retval
!= ERROR_OK
)
1851 mem_ap_read_atomic_u32(swjdp
, DCB_DEMCR
, &demcr
);
1857 if (strcmp(args
[0], "all") == 0) {
1858 catch = VC_HARDERR
| VC_INTERR
| VC_BUSERR
1859 | VC_STATERR
| VC_CHKERR
| VC_NOCPERR
1860 | VC_MMERR
| VC_CORERESET
;
1862 } else if (strcmp(args
[0], "none") == 0) {
1866 while (argc
-- > 0) {
1867 for (i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++) {
1868 if (strcmp(args
[argc
], vec_ids
[i
].name
) != 0)
1870 catch |= vec_ids
[i
].mask
;
1873 if (i
== ARRAY_SIZE(vec_ids
)) {
1874 LOG_ERROR("No CM3 vector '%s'", args
[argc
]);
1875 return ERROR_INVALID_ARGUMENTS
;
1882 /* write, but don't assume it stuck */
1883 mem_ap_write_u32(swjdp
, DCB_DEMCR
, demcr
);
1884 mem_ap_read_atomic_u32(swjdp
, DCB_DEMCR
, &demcr
);
1887 for (i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++)
1888 command_print(cmd_ctx
, "%9s: %s", vec_ids
[i
].name
,
1889 (demcr
& vec_ids
[i
].mask
) ? "catch" : "ignore");
1894 COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command
)
1896 struct target
*target
= get_current_target(cmd_ctx
);
1897 struct cortex_m3_common
*cortex_m3
= target_to_cm3(target
);
1900 retval
= cortex_m3_verify_pointer(cmd_ctx
, cortex_m3
);
1901 if (retval
!= ERROR_OK
)
1904 if (target
->state
!= TARGET_HALTED
)
1906 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", CMD_NAME
);
1912 if (!strcmp(args
[0], "on"))
1914 cortex_m3_write_debug_halt_mask(target
, C_HALT
| C_MASKINTS
, 0);
1916 else if (!strcmp(args
[0], "off"))
1918 cortex_m3_write_debug_halt_mask(target
, C_HALT
, C_MASKINTS
);
1922 command_print(cmd_ctx
, "usage: cortex_m3 maskisr ['on'|'off']");
1926 command_print(cmd_ctx
, "cortex_m3 interrupt mask %s",
1927 (cortex_m3
->dcb_dhcsr
& C_MASKINTS
) ? "on" : "off");
1932 static int cortex_m3_register_commands(struct command_context
*cmd_ctx
)
1935 struct command
*cortex_m3_cmd
;
1937 retval
= armv7m_register_commands(cmd_ctx
);
1939 cortex_m3_cmd
= register_command(cmd_ctx
, NULL
, "cortex_m3",
1940 NULL
, COMMAND_ANY
, "cortex_m3 specific commands");
1942 register_command(cmd_ctx
, cortex_m3_cmd
, "disassemble",
1943 handle_cortex_m3_disassemble_command
, COMMAND_EXEC
,
1944 "disassemble Thumb2 instructions <address> [<count>]");
1945 register_command(cmd_ctx
, cortex_m3_cmd
, "maskisr",
1946 handle_cortex_m3_mask_interrupts_command
, COMMAND_EXEC
,
1947 "mask cortex_m3 interrupts ['on'|'off']");
1948 register_command(cmd_ctx
, cortex_m3_cmd
, "vector_catch",
1949 handle_cortex_m3_vector_catch_command
, COMMAND_EXEC
,
1950 "catch hardware vectors ['all'|'none'|<list>]");
1955 struct target_type cortexm3_target
=
1957 .name
= "cortex_m3",
1959 .poll
= cortex_m3_poll
,
1960 .arch_state
= armv7m_arch_state
,
1962 .target_request_data
= cortex_m3_target_request_data
,
1964 .halt
= cortex_m3_halt
,
1965 .resume
= cortex_m3_resume
,
1966 .step
= cortex_m3_step
,
1968 .assert_reset
= cortex_m3_assert_reset
,
1969 .deassert_reset
= cortex_m3_deassert_reset
,
1970 .soft_reset_halt
= cortex_m3_soft_reset_halt
,
1972 .get_gdb_reg_list
= armv7m_get_gdb_reg_list
,
1974 .read_memory
= cortex_m3_read_memory
,
1975 .write_memory
= cortex_m3_write_memory
,
1976 .bulk_write_memory
= cortex_m3_bulk_write_memory
,
1977 .checksum_memory
= armv7m_checksum_memory
,
1978 .blank_check_memory
= armv7m_blank_check_memory
,
1980 .run_algorithm
= armv7m_run_algorithm
,
1982 .add_breakpoint
= cortex_m3_add_breakpoint
,
1983 .remove_breakpoint
= cortex_m3_remove_breakpoint
,
1984 .add_watchpoint
= cortex_m3_add_watchpoint
,
1985 .remove_watchpoint
= cortex_m3_remove_watchpoint
,
1987 .register_commands
= cortex_m3_register_commands
,
1988 .target_create
= cortex_m3_target_create
,
1989 .init_target
= cortex_m3_init_target
,
1990 .examine
= cortex_m3_examine
,