1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
5 * Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
27 #include "arm11_dbgtap.h"
29 #include "time_support.h"
32 #define JTAG_DEBUG(expr ...) DEBUG(expr)
34 #define JTAG_DEBUG(expr ...) do {} while (0)
38 This pathmove goes from Pause-IR to Shift-IR while avoiding RTI. The
39 behavior of the FTDI driver IIRC was to go via RTI.
41 Conversely there may be other places in this code where the ARM11 code relies
42 on the driver to hit through RTI when coming from Update-?R.
44 static const tap_state_t arm11_move_pi_to_si_via_ci
[] =
46 TAP_IREXIT2
, TAP_IRUPDATE
, TAP_DRSELECT
, TAP_IRSELECT
, TAP_IRCAPTURE
, TAP_IRSHIFT
50 int arm11_add_ir_scan_vc(int num_fields
, struct scan_field
*fields
, tap_state_t state
)
52 if (cmd_queue_cur_state
== TAP_IRPAUSE
)
53 jtag_add_pathmove(asizeof(arm11_move_pi_to_si_via_ci
), arm11_move_pi_to_si_via_ci
);
55 jtag_add_ir_scan(num_fields
, fields
, state
);
59 static const tap_state_t arm11_move_pd_to_sd_via_cd
[] =
61 TAP_DREXIT2
, TAP_DRUPDATE
, TAP_DRSELECT
, TAP_DRCAPTURE
, TAP_DRSHIFT
64 int arm11_add_dr_scan_vc(int num_fields
, struct scan_field
*fields
, tap_state_t state
)
66 if (cmd_queue_cur_state
== TAP_DRPAUSE
)
67 jtag_add_pathmove(asizeof(arm11_move_pd_to_sd_via_cd
), arm11_move_pd_to_sd_via_cd
);
69 jtag_add_dr_scan(num_fields
, fields
, state
);
74 /** Code de-clutter: Construct struct scan_field to write out a value
76 * \param arm11 Target state variable.
77 * \param num_bits Length of the data field
78 * \param out_data pointer to the data that will be sent out
79 * <em > (data is read when it is added to the JTAG queue)</em>
80 * \param in_data pointer to the memory that will receive data that was clocked in
81 * <em > (data is written when the JTAG queue is executed)</em>
82 * \param field target data structure that will be initialized
84 void arm11_setup_field(struct arm11_common
* arm11
, int num_bits
, void * out_data
, void * in_data
, struct scan_field
* field
)
86 field
->tap
= arm11
->target
->tap
;
87 field
->num_bits
= num_bits
;
88 field
->out_value
= out_data
;
89 field
->in_value
= in_data
;
93 /** Write JTAG instruction register
95 * \param arm11 Target state variable.
96 * \param instr An ARM11 DBGTAP instruction. Use enum #arm11_instructions.
97 * \param state Pass the final TAP state or ARM11_TAP_DEFAULT for the default value (Pause-IR).
99 * \remarks This adds to the JTAG command queue but does \em not execute it.
101 void arm11_add_IR(struct arm11_common
* arm11
, uint8_t instr
, tap_state_t state
)
103 struct jtag_tap
*tap
;
104 tap
= arm11
->target
->tap
;
106 if (buf_get_u32(tap
->cur_instr
, 0, 5) == instr
)
108 JTAG_DEBUG("IR <= 0x%02x SKIPPED", instr
);
112 JTAG_DEBUG("IR <= 0x%02x", instr
);
114 struct scan_field field
;
116 arm11_setup_field(arm11
, 5, &instr
, NULL
, &field
);
118 arm11_add_ir_scan_vc(1, &field
, state
== ARM11_TAP_DEFAULT
? TAP_IRPAUSE
: state
);
121 /** Verify shifted out data from Scan Chain Register (SCREG)
122 * Used as parameter to struct scan_field::in_handler in
123 * arm11_add_debug_SCAN_N().
126 static void arm11_in_handler_SCAN_N(uint8_t *in_value
)
128 /** \todo TODO: clarify why this isnt properly masked in core.c jtag_read_buffer() */
129 uint8_t v
= *in_value
& 0x1F;
133 LOG_ERROR("'arm11 target' JTAG communication error SCREG SCAN OUT 0x%02x (expected 0x10)", v
);
134 jtag_set_error(ERROR_FAIL
);
137 JTAG_DEBUG("SCREG SCAN OUT 0x%02x", v
);
140 /** Select and write to Scan Chain Register (SCREG)
142 * This function sets the instruction register to SCAN_N and writes
143 * the data register with the selected chain number.
145 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/Cacbjhfg.html
147 * \param arm11 Target state variable.
148 * \param chain Scan chain that will be selected.
149 * \param state Pass the final TAP state or ARM11_TAP_DEFAULT for the default
152 * The chain takes effect when Update-DR is passed (usually when subsequently
153 * the INTEXT/EXTEST instructions are written).
155 * \warning (Obsolete) Using this twice in a row will \em fail. The first
156 * call will end in Pause-DR. The second call, due to the IR
157 * caching, will not go through Capture-DR when shifting in the
158 * new scan chain number. As a result the verification in
159 * arm11_in_handler_SCAN_N() must fail.
161 * \remarks This adds to the JTAG command queue but does \em not execute it.
164 int arm11_add_debug_SCAN_N(struct arm11_common
* arm11
, uint8_t chain
, tap_state_t state
)
166 JTAG_DEBUG("SCREG <= 0x%02x", chain
);
168 arm11_add_IR(arm11
, ARM11_SCAN_N
, ARM11_TAP_DEFAULT
);
170 struct scan_field field
;
173 arm11_setup_field(arm11
, 5, &chain
, &tmp
, &field
);
175 arm11_add_dr_scan_vc(1, &field
, state
== ARM11_TAP_DEFAULT
? TAP_DRPAUSE
: state
);
177 jtag_execute_queue_noclear();
179 arm11_in_handler_SCAN_N(tmp
);
181 arm11
->jtag_info
.cur_scan_chain
= chain
;
183 return jtag_execute_queue();
186 /** Write an instruction into the ITR register
188 * \param arm11 Target state variable.
189 * \param inst An ARM11 processor instruction/opcode.
190 * \param flag Optional parameter to retrieve the InstCompl flag
191 * (this will be written when the JTAG chain is executed).
192 * \param state Pass the final TAP state or ARM11_TAP_DEFAULT for the default
193 * value (Run-Test/Idle).
195 * \remarks By default this ends with Run-Test/Idle state
196 * and causes the instruction to be executed. If
197 * a subsequent write to DTR is needed before
198 * executing the instruction then TAP_DRPAUSE should be
199 * passed to \p state.
201 * \remarks This adds to the JTAG command queue but does \em not execute it.
203 void arm11_add_debug_INST(struct arm11_common
* arm11
, uint32_t inst
, uint8_t * flag
, tap_state_t state
)
205 JTAG_DEBUG("INST <= 0x%08x", inst
);
207 struct scan_field itr
[2];
209 arm11_setup_field(arm11
, 32, &inst
, NULL
, itr
+ 0);
210 arm11_setup_field(arm11
, 1, NULL
, flag
, itr
+ 1);
212 arm11_add_dr_scan_vc(asizeof(itr
), itr
, state
== ARM11_TAP_DEFAULT
? TAP_IDLE
: state
);
215 /** Read the Debug Status and Control Register (DSCR)
219 * \param arm11 Target state variable.
220 * \param value DSCR content
221 * \return Error status
223 * \remarks This is a stand-alone function that executes the JTAG command queue.
225 int arm11_read_DSCR(struct arm11_common
* arm11
, uint32_t *value
)
228 retval
= arm11_add_debug_SCAN_N(arm11
, 0x01, ARM11_TAP_DEFAULT
);
229 if (retval
!= ERROR_OK
)
232 arm11_add_IR(arm11
, ARM11_INTEST
, ARM11_TAP_DEFAULT
);
235 struct scan_field chain1_field
;
237 arm11_setup_field(arm11
, 32, NULL
, &dscr
, &chain1_field
);
239 arm11_add_dr_scan_vc(1, &chain1_field
, TAP_DRPAUSE
);
241 CHECK_RETVAL(jtag_execute_queue());
243 if (arm11
->last_dscr
!= dscr
)
244 JTAG_DEBUG("DSCR = %08x (OLD %08x)", dscr
, arm11
->last_dscr
);
246 arm11
->last_dscr
= dscr
;
253 /** Write the Debug Status and Control Register (DSCR)
257 * \param arm11 Target state variable.
258 * \param dscr DSCR content
260 * \remarks This is a stand-alone function that executes the JTAG command queue.
262 int arm11_write_DSCR(struct arm11_common
* arm11
, uint32_t dscr
)
265 retval
= arm11_add_debug_SCAN_N(arm11
, 0x01, ARM11_TAP_DEFAULT
);
266 if (retval
!= ERROR_OK
)
269 arm11_add_IR(arm11
, ARM11_EXTEST
, ARM11_TAP_DEFAULT
);
271 struct scan_field chain1_field
;
273 arm11_setup_field(arm11
, 32, &dscr
, NULL
, &chain1_field
);
275 arm11_add_dr_scan_vc(1, &chain1_field
, TAP_DRPAUSE
);
277 CHECK_RETVAL(jtag_execute_queue());
279 JTAG_DEBUG("DSCR <= %08x (OLD %08x)", dscr
, arm11
->last_dscr
);
281 arm11
->last_dscr
= dscr
;
288 /** Get the debug reason from Debug Status and Control Register (DSCR)
290 * \param dscr DSCR value to analyze
291 * \return Debug reason
294 enum target_debug_reason
arm11_get_DSCR_debug_reason(uint32_t dscr
)
296 switch (dscr
& ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK
)
298 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT
:
299 LOG_INFO("Debug entry: JTAG HALT");
300 return DBG_REASON_DBGRQ
;
302 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT
:
303 LOG_INFO("Debug entry: breakpoint");
304 return DBG_REASON_BREAKPOINT
;
306 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT
:
307 LOG_INFO("Debug entry: watchpoint");
308 return DBG_REASON_WATCHPOINT
;
310 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION
:
311 LOG_INFO("Debug entry: BKPT instruction");
312 return DBG_REASON_BREAKPOINT
;
314 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ
:
315 LOG_INFO("Debug entry: EDBGRQ signal");
316 return DBG_REASON_DBGRQ
;
318 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH
:
319 LOG_INFO("Debug entry: VCR vector catch");
320 return DBG_REASON_BREAKPOINT
;
323 LOG_INFO("Debug entry: unknown");
324 return DBG_REASON_DBGRQ
;
330 /** Prepare the stage for ITR/DTR operations
331 * from the arm11_run_instr... group of functions.
333 * Put arm11_run_instr_data_prepare() and arm11_run_instr_data_finish()
334 * around a block of arm11_run_instr_... calls.
336 * Select scan chain 5 to allow quick access to DTR. When scan
337 * chain 4 is needed to put in a register the ITRSel instruction
338 * shortcut is used instead of actually changing the Scan_N
341 * \param arm11 Target state variable.
344 int arm11_run_instr_data_prepare(struct arm11_common
* arm11
)
346 return arm11_add_debug_SCAN_N(arm11
, 0x05, ARM11_TAP_DEFAULT
);
349 /** Cleanup after ITR/DTR operations
350 * from the arm11_run_instr... group of functions
352 * Put arm11_run_instr_data_prepare() and arm11_run_instr_data_finish()
353 * around a block of arm11_run_instr_... calls.
355 * Any IDLE can lead to an instruction execution when
356 * scan chains 4 or 5 are selected and the IR holds
357 * INTEST or EXTEST. So we must disable that before
358 * any following activities lead to an IDLE.
360 * \param arm11 Target state variable.
363 int arm11_run_instr_data_finish(struct arm11_common
* arm11
)
365 return arm11_add_debug_SCAN_N(arm11
, 0x00, ARM11_TAP_DEFAULT
);
370 /** Execute one or multiple instructions via ITR
372 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
374 * \param arm11 Target state variable.
375 * \param opcode Pointer to sequence of ARM opcodes
376 * \param count Number of opcodes to execute
379 int arm11_run_instr_no_data(struct arm11_common
* arm11
, uint32_t * opcode
, size_t count
)
381 arm11_add_IR(arm11
, ARM11_ITRSEL
, ARM11_TAP_DEFAULT
);
385 arm11_add_debug_INST(arm11
, *opcode
++, NULL
, TAP_IDLE
);
392 arm11_add_debug_INST(arm11
, 0, &flag
, count
? TAP_IDLE
: TAP_DRPAUSE
);
394 CHECK_RETVAL(jtag_execute_queue());
407 if ((timeval_ms()-then
) > 1000)
409 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
421 /** Execute one instruction via ITR
423 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
425 * \param arm11 Target state variable.
426 * \param opcode ARM opcode
429 int arm11_run_instr_no_data1(struct arm11_common
* arm11
, uint32_t opcode
)
431 return arm11_run_instr_no_data(arm11
, &opcode
, 1);
435 /** Execute one instruction via ITR repeatedly while
436 * passing data to the core via DTR on each execution.
438 * The executed instruction \em must read data from DTR.
440 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
442 * \param arm11 Target state variable.
443 * \param opcode ARM opcode
444 * \param data Pointer to the data words to be passed to the core
445 * \param count Number of data words and instruction repetitions
448 int arm11_run_instr_data_to_core(struct arm11_common
* arm11
, uint32_t opcode
, uint32_t * data
, size_t count
)
450 arm11_add_IR(arm11
, ARM11_ITRSEL
, ARM11_TAP_DEFAULT
);
452 arm11_add_debug_INST(arm11
, opcode
, NULL
, TAP_DRPAUSE
);
454 arm11_add_IR(arm11
, ARM11_EXTEST
, ARM11_TAP_DEFAULT
);
456 struct scan_field chain5_fields
[3];
462 arm11_setup_field(arm11
, 32, &Data
, NULL
, chain5_fields
+ 0);
463 arm11_setup_field(arm11
, 1, NULL
, &Ready
, chain5_fields
+ 1);
464 arm11_setup_field(arm11
, 1, NULL
, &nRetry
, chain5_fields
+ 2);
473 arm11_add_dr_scan_vc(asizeof(chain5_fields
), chain5_fields
, jtag_set_end_state(TAP_IDLE
));
475 CHECK_RETVAL(jtag_execute_queue());
477 JTAG_DEBUG("DTR Ready %d nRetry %d", Ready
, nRetry
);
487 if ((timeval_ms()-then
) > 1000)
489 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
501 arm11_add_IR(arm11
, ARM11_INTEST
, ARM11_TAP_DEFAULT
);
508 arm11_add_dr_scan_vc(asizeof(chain5_fields
), chain5_fields
, TAP_DRPAUSE
);
510 CHECK_RETVAL(jtag_execute_queue());
512 JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data
, Ready
, nRetry
);
522 if ((timeval_ms()-then
) > 1000)
524 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
536 /** JTAG path for arm11_run_instr_data_to_core_noack
538 * The repeated TAP_IDLE's do not cause a repeated execution
539 * if passed without leaving the state.
541 * Since this is more than 7 bits (adjustable via adding more
542 * TAP_IDLE's) it produces an artificial delay in the lower
543 * layer (FT2232) that is long enough to finish execution on
544 * the core but still shorter than any manually inducible delays.
546 * To disable this code, try "memwrite burst false"
548 * FIX!!! should we use multiple TAP_IDLE here or not???
550 * https://lists.berlios.de/pipermail/openocd-development/2009-July/009698.html
551 * https://lists.berlios.de/pipermail/openocd-development/2009-August/009865.html
553 static const tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay
[] =
555 TAP_DREXIT2
, TAP_DRUPDATE
, TAP_IDLE
, TAP_IDLE
, TAP_IDLE
, TAP_DRSELECT
, TAP_DRCAPTURE
, TAP_DRSHIFT
560 /** Execute one instruction via ITR repeatedly while
561 * passing data to the core via DTR on each execution.
563 * No Ready check during transmission.
565 * The executed instruction \em must read data from DTR.
567 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
569 * \param arm11 Target state variable.
570 * \param opcode ARM opcode
571 * \param data Pointer to the data words to be passed to the core
572 * \param count Number of data words and instruction repetitions
575 int arm11_run_instr_data_to_core_noack(struct arm11_common
* arm11
, uint32_t opcode
, uint32_t * data
, size_t count
)
577 arm11_add_IR(arm11
, ARM11_ITRSEL
, ARM11_TAP_DEFAULT
);
579 arm11_add_debug_INST(arm11
, opcode
, NULL
, TAP_DRPAUSE
);
581 arm11_add_IR(arm11
, ARM11_EXTEST
, ARM11_TAP_DEFAULT
);
583 struct scan_field chain5_fields
[3];
585 arm11_setup_field(arm11
, 32, NULL
/*&Data*/, NULL
, chain5_fields
+ 0);
586 arm11_setup_field(arm11
, 1, NULL
, NULL
/*&Ready*/, chain5_fields
+ 1);
587 arm11_setup_field(arm11
, 1, NULL
, NULL
, chain5_fields
+ 2);
590 size_t readiesNum
= (count
+ 1);
591 size_t bytes
= sizeof(*Readies
)*readiesNum
;
592 Readies
= (uint8_t *) malloc(bytes
);
595 LOG_ERROR("Out of memory allocating " ZU
" bytes", bytes
);
599 uint8_t * ReadyPos
= Readies
;
603 chain5_fields
[0].out_value
= (void *)(data
++);
604 chain5_fields
[1].in_value
= ReadyPos
++;
608 jtag_add_dr_scan(asizeof(chain5_fields
), chain5_fields
, jtag_set_end_state(TAP_DRPAUSE
));
609 jtag_add_pathmove(asizeof(arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay
),
610 arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay
);
614 jtag_add_dr_scan(asizeof(chain5_fields
), chain5_fields
, jtag_set_end_state(TAP_IDLE
));
618 arm11_add_IR(arm11
, ARM11_INTEST
, ARM11_TAP_DEFAULT
);
620 chain5_fields
[0].out_value
= 0;
621 chain5_fields
[1].in_value
= ReadyPos
++;
623 arm11_add_dr_scan_vc(asizeof(chain5_fields
), chain5_fields
, TAP_DRPAUSE
);
625 int retval
= jtag_execute_queue();
626 if (retval
== ERROR_OK
)
628 size_t error_count
= 0;
630 for (size_t i
= 0; i
< readiesNum
; i
++)
638 if (error_count
> 0 )
639 LOG_ERROR(ZU
" words out of " ZU
" not transferred", error_count
, readiesNum
);
649 /** Execute an instruction via ITR while handing data into the core via DTR.
651 * The executed instruction \em must read data from DTR.
653 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
655 * \param arm11 Target state variable.
656 * \param opcode ARM opcode
657 * \param data Data word to be passed to the core via DTR
660 int arm11_run_instr_data_to_core1(struct arm11_common
* arm11
, uint32_t opcode
, uint32_t data
)
662 return arm11_run_instr_data_to_core(arm11
, opcode
, &data
, 1);
666 /** Execute one instruction via ITR repeatedly while
667 * reading data from the core via DTR on each execution.
669 * The executed instruction \em must write data to DTR.
671 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
673 * \param arm11 Target state variable.
674 * \param opcode ARM opcode
675 * \param data Pointer to an array that receives the data words from the core
676 * \param count Number of data words and instruction repetitions
679 int arm11_run_instr_data_from_core(struct arm11_common
* arm11
, uint32_t opcode
, uint32_t * data
, size_t count
)
681 arm11_add_IR(arm11
, ARM11_ITRSEL
, ARM11_TAP_DEFAULT
);
683 arm11_add_debug_INST(arm11
, opcode
, NULL
, TAP_IDLE
);
685 arm11_add_IR(arm11
, ARM11_INTEST
, ARM11_TAP_DEFAULT
);
687 struct scan_field chain5_fields
[3];
693 arm11_setup_field(arm11
, 32, NULL
, &Data
, chain5_fields
+ 0);
694 arm11_setup_field(arm11
, 1, NULL
, &Ready
, chain5_fields
+ 1);
695 arm11_setup_field(arm11
, 1, NULL
, &nRetry
, chain5_fields
+ 2);
702 arm11_add_dr_scan_vc(asizeof(chain5_fields
), chain5_fields
, count
? TAP_IDLE
: TAP_DRPAUSE
);
704 CHECK_RETVAL(jtag_execute_queue());
706 JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data
, Ready
, nRetry
);
716 if ((timeval_ms()-then
) > 1000)
718 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
733 /** Execute one instruction via ITR
734 * then load r0 into DTR and read DTR from core.
736 * The first executed instruction (\p opcode) should write data to r0.
738 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
740 * \param arm11 Target state variable.
741 * \param opcode ARM opcode to write r0 with the value of interest
742 * \param data Pointer to a data word that receives the value from r0 after \p opcode was executed.
745 int arm11_run_instr_data_from_core_via_r0(struct arm11_common
* arm11
, uint32_t opcode
, uint32_t * data
)
748 retval
= arm11_run_instr_no_data1(arm11
, opcode
);
749 if (retval
!= ERROR_OK
)
752 /* MCR p14,0,R0,c0,c5,0 (move r0 -> wDTR -> local var) */
753 arm11_run_instr_data_from_core(arm11
, 0xEE000E15, data
, 1);
758 /** Load data into core via DTR then move it to r0 then
759 * execute one instruction via ITR
761 * The final executed instruction (\p opcode) should read data from r0.
763 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
765 * \param arm11 Target state variable.
766 * \param opcode ARM opcode to read r0 act upon it
767 * \param data Data word that will be written to r0 before \p opcode is executed
770 int arm11_run_instr_data_to_core_via_r0(struct arm11_common
* arm11
, uint32_t opcode
, uint32_t data
)
773 /* MRC p14,0,r0,c0,c5,0 */
774 retval
= arm11_run_instr_data_to_core1(arm11
, 0xEE100E15, data
);
775 if (retval
!= ERROR_OK
)
778 retval
= arm11_run_instr_no_data1(arm11
, opcode
);
779 if (retval
!= ERROR_OK
)
785 /** Apply reads and writes to scan chain 7
787 * \see struct arm11_sc7_action
789 * \param arm11 Target state variable.
790 * \param actions A list of read and/or write instructions
791 * \param count Number of instructions in the list.
794 int arm11_sc7_run(struct arm11_common
* arm11
, struct arm11_sc7_action
* actions
, size_t count
)
798 retval
= arm11_add_debug_SCAN_N(arm11
, 0x07, ARM11_TAP_DEFAULT
);
799 if (retval
!= ERROR_OK
)
802 arm11_add_IR(arm11
, ARM11_EXTEST
, ARM11_TAP_DEFAULT
);
804 struct scan_field chain7_fields
[3];
813 arm11_setup_field(arm11
, 1, &nRW
, &Ready
, chain7_fields
+ 0);
814 arm11_setup_field(arm11
, 32, &DataOut
, &DataIn
, chain7_fields
+ 1);
815 arm11_setup_field(arm11
, 7, &AddressOut
, &AddressIn
, chain7_fields
+ 2);
817 for (size_t i
= 0; i
< count
+ 1; i
++)
821 nRW
= actions
[i
].write
? 1 : 0;
822 DataOut
= actions
[i
].value
;
823 AddressOut
= actions
[i
].address
;
834 JTAG_DEBUG("SC7 <= Address %02x Data %08x nRW %d", AddressOut
, DataOut
, nRW
);
836 arm11_add_dr_scan_vc(asizeof(chain7_fields
), chain7_fields
, TAP_DRPAUSE
);
838 CHECK_RETVAL(jtag_execute_queue());
840 JTAG_DEBUG("SC7 => Address %02x Data %08x Ready %d", AddressIn
, DataIn
, Ready
);
842 while (!Ready
); /* 'nRW' is 'Ready' on read out */
846 if (actions
[i
- 1].address
!= AddressIn
)
848 LOG_WARNING("Scan chain 7 shifted out unexpected address");
851 if (!actions
[i
- 1].write
)
853 actions
[i
- 1].value
= DataIn
;
857 if (actions
[i
- 1].value
!= DataIn
)
859 LOG_WARNING("Scan chain 7 shifted out unexpected data");
865 for (size_t i
= 0; i
< count
; i
++)
867 JTAG_DEBUG("SC7 %02d: %02x %s %08x", i
, actions
[i
].address
, actions
[i
].write
? "<=" : "=>", actions
[i
].value
);
873 /** Clear VCR and all breakpoints and watchpoints via scan chain 7
875 * \param arm11 Target state variable.
878 void arm11_sc7_clear_vbw(struct arm11_common
* arm11
)
880 struct arm11_sc7_action clear_bw
[arm11
->brp
+ arm11
->wrp
+ 1];
881 struct arm11_sc7_action
* pos
= clear_bw
;
883 for (size_t i
= 0; i
< asizeof(clear_bw
); i
++)
885 clear_bw
[i
].write
= true;
886 clear_bw
[i
].value
= 0;
889 for (size_t i
= 0; i
< arm11
->brp
; i
++)
890 (pos
++)->address
= ARM11_SC7_BCR0
+ i
;
893 for (size_t i
= 0; i
< arm11
->wrp
; i
++)
894 (pos
++)->address
= ARM11_SC7_WCR0
+ i
;
897 (pos
++)->address
= ARM11_SC7_VCR
;
899 arm11_sc7_run(arm11
, clear_bw
, asizeof(clear_bw
));
902 /** Write VCR register
904 * \param arm11 Target state variable.
905 * \param value Value to be written
907 void arm11_sc7_set_vcr(struct arm11_common
* arm11
, uint32_t value
)
909 struct arm11_sc7_action set_vcr
;
911 set_vcr
.write
= true;
912 set_vcr
.address
= ARM11_SC7_VCR
;
913 set_vcr
.value
= value
;
916 arm11_sc7_run(arm11
, &set_vcr
, 1);
921 /** Read word from address
923 * \param arm11 Target state variable.
924 * \param address Memory address to be read
925 * \param result Pointer where to store result
928 int arm11_read_memory_word(struct arm11_common
* arm11
, uint32_t address
, uint32_t * result
)
931 retval
= arm11_run_instr_data_prepare(arm11
);
932 if (retval
!= ERROR_OK
)
935 /* MRC p14,0,r0,c0,c5,0 (r0 = address) */
936 CHECK_RETVAL(arm11_run_instr_data_to_core1(arm11
, 0xee100e15, address
));
938 /* LDC p14,c5,[R0],#4 (DTR = [r0]) */
939 CHECK_RETVAL(arm11_run_instr_data_from_core(arm11
, 0xecb05e01, result
, 1));
941 return arm11_run_instr_data_finish(arm11
);