1 /***************************************************************************
2 * Copyright (C) 2007-2008 by unsik Kim <donari75@gmail.com> *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
18 ***************************************************************************/
25 #include <target/target.h>
26 #include <helper/time_support.h>
27 #include <helper/fileio.h>
28 #include <helper/log.h>
31 static int s3c2440_set_gpio_to_output (struct mflash_gpio_num gpio
);
32 static int s3c2440_set_gpio_output_val (struct mflash_gpio_num gpio
, uint8_t val
);
33 static int pxa270_set_gpio_to_output (struct mflash_gpio_num gpio
);
34 static int pxa270_set_gpio_output_val (struct mflash_gpio_num gpio
, uint8_t val
);
36 static struct mflash_bank
*mflash_bank
;
38 static struct mflash_gpio_drv pxa270_gpio
= {
40 .set_gpio_to_output
= pxa270_set_gpio_to_output
,
41 .set_gpio_output_val
= pxa270_set_gpio_output_val
44 static struct mflash_gpio_drv s3c2440_gpio
= {
46 .set_gpio_to_output
= s3c2440_set_gpio_to_output
,
47 .set_gpio_output_val
= s3c2440_set_gpio_output_val
50 static struct mflash_gpio_drv
*mflash_gpio
[] =
57 #define PXA270_GAFR0_L 0x40E00054
58 #define PXA270_GAFR3_U 0x40E00070
59 #define PXA270_GAFR3_U_RESERVED_BITS 0xfffc0000u
60 #define PXA270_GPDR0 0x40E0000C
61 #define PXA270_GPDR3 0x40E0010C
62 #define PXA270_GPDR3_RESERVED_BITS 0xfe000000u
63 #define PXA270_GPSR0 0x40E00018
64 #define PXA270_GPCR0 0x40E00024
66 static int pxa270_set_gpio_to_output (struct mflash_gpio_num gpio
)
68 uint32_t addr
, value
, mask
;
69 struct target
*target
= mflash_bank
->target
;
72 /* remove alternate function. */
73 mask
= 0x3u
<< (gpio
.num
& 0xF)*2;
75 addr
= PXA270_GAFR0_L
+ (gpio
.num
>> 4) * 4;
77 if ((ret
= target_read_u32(target
, addr
, &value
)) != ERROR_OK
)
81 if (addr
== PXA270_GAFR3_U
)
82 value
&= ~PXA270_GAFR3_U_RESERVED_BITS
;
84 if ((ret
= target_write_u32(target
, addr
, value
)) != ERROR_OK
)
87 /* set direction to output */
88 mask
= 0x1u
<< (gpio
.num
& 0x1F);
90 addr
= PXA270_GPDR0
+ (gpio
.num
>> 5) * 4;
92 if ((ret
= target_read_u32(target
, addr
, &value
)) != ERROR_OK
)
96 if (addr
== PXA270_GPDR3
)
97 value
&= ~PXA270_GPDR3_RESERVED_BITS
;
99 ret
= target_write_u32(target
, addr
, value
);
103 static int pxa270_set_gpio_output_val (struct mflash_gpio_num gpio
, uint8_t val
)
105 uint32_t addr
, value
, mask
;
106 struct target
*target
= mflash_bank
->target
;
109 mask
= 0x1u
<< (gpio
.num
& 0x1F);
112 addr
= PXA270_GPSR0
+ (gpio
.num
>> 5) * 4;
114 addr
= PXA270_GPCR0
+ (gpio
.num
>> 5) * 4;
117 if ((ret
= target_read_u32(target
, addr
, &value
)) != ERROR_OK
)
122 ret
= target_write_u32(target
, addr
, value
);
127 #define S3C2440_GPACON 0x56000000
128 #define S3C2440_GPADAT 0x56000004
129 #define S3C2440_GPJCON 0x560000d0
130 #define S3C2440_GPJDAT 0x560000d4
132 static int s3c2440_set_gpio_to_output (struct mflash_gpio_num gpio
)
134 uint32_t data
, mask
, gpio_con
;
135 struct target
*target
= mflash_bank
->target
;
138 if (gpio
.port
[0] >= 'a' && gpio
.port
[0] <= 'h') {
139 gpio_con
= S3C2440_GPACON
+ (gpio
.port
[0] - 'a') * 0x10;
140 } else if (gpio
.port
[0] == 'j') {
141 gpio_con
= S3C2440_GPJCON
;
143 LOG_ERROR("mflash: invalid port %d%s", gpio
.num
, gpio
.port
);
144 return ERROR_INVALID_ARGUMENTS
;
147 ret
= target_read_u32(target
, gpio_con
, &data
);
149 if (ret
== ERROR_OK
) {
150 if (gpio
.port
[0] == 'a') {
151 mask
= 1 << gpio
.num
;
154 mask
= 3 << gpio
.num
* 2;
156 data
|= (1 << gpio
.num
* 2);
159 ret
= target_write_u32(target
, gpio_con
, data
);
164 static int s3c2440_set_gpio_output_val (struct mflash_gpio_num gpio
, uint8_t val
)
166 uint32_t data
, mask
, gpio_dat
;
167 struct target
*target
= mflash_bank
->target
;
170 if (gpio
.port
[0] >= 'a' && gpio
.port
[0] <= 'h') {
171 gpio_dat
= S3C2440_GPADAT
+ (gpio
.port
[0] - 'a') * 0x10;
172 } else if (gpio
.port
[0] == 'j') {
173 gpio_dat
= S3C2440_GPJDAT
;
175 LOG_ERROR("mflash: invalid port %d%s", gpio
.num
, gpio
.port
);
176 return ERROR_INVALID_ARGUMENTS
;
179 ret
= target_read_u32(target
, gpio_dat
, &data
);
181 if (ret
== ERROR_OK
) {
182 mask
= 1 << gpio
.num
;
188 ret
= target_write_u32(target
, gpio_dat
, data
);
193 static int mg_hdrst(uint8_t level
)
195 return mflash_bank
->gpio_drv
->set_gpio_output_val(mflash_bank
->rst_pin
, level
);
198 static int mg_init_gpio (void)
201 struct mflash_gpio_drv
*gpio_drv
= mflash_bank
->gpio_drv
;
203 ret
= gpio_drv
->set_gpio_to_output(mflash_bank
->rst_pin
);
207 ret
= gpio_drv
->set_gpio_output_val(mflash_bank
->rst_pin
, 1);
212 static int mg_dsk_wait(mg_io_type_wait wait_local
, uint32_t time_var
)
214 uint8_t status
, error
;
215 struct target
*target
= mflash_bank
->target
;
216 uint32_t mg_task_reg
= mflash_bank
->base
+ MG_REG_OFFSET
;
220 struct duration bench
;
221 duration_start(&bench
);
225 ret
= target_read_u8(target
, mg_task_reg
+ MG_REG_STATUS
, &status
);
229 if (status
& mg_io_rbit_status_busy
)
231 if (wait_local
== mg_io_wait_bsy
)
236 case mg_io_wait_not_bsy
:
238 case mg_io_wait_rdy_noerr
:
239 if (status
& mg_io_rbit_status_ready
)
242 case mg_io_wait_drq_noerr
:
243 if (status
& mg_io_rbit_status_data_req
)
250 /* Now we check the error condition! */
251 if (status
& mg_io_rbit_status_error
)
253 ret
= target_read_u8(target
, mg_task_reg
+ MG_REG_ERROR
, &error
);
257 LOG_ERROR("mflash: io error 0x%02x", error
);
265 if (status
& mg_io_rbit_status_ready
)
269 if (status
& mg_io_rbit_status_data_req
)
277 ret
= duration_measure(&bench
);
279 t
= duration_elapsed(&bench
) * 1000.0;
281 LOG_ERROR("mflash: duration measurement failed: %d", ret
);
287 LOG_ERROR("mflash: timeout occured");
288 return ERROR_MG_TIMEOUT
;
291 static int mg_dsk_srst(uint8_t on
)
293 struct target
*target
= mflash_bank
->target
;
294 uint32_t mg_task_reg
= mflash_bank
->base
+ MG_REG_OFFSET
;
298 if ((ret
= target_read_u8(target
, mg_task_reg
+ MG_REG_DRV_CTRL
, &value
)) != ERROR_OK
)
302 value
|= (mg_io_rbit_devc_srst
);
304 value
&= ~mg_io_rbit_devc_srst
;
307 ret
= target_write_u8(target
, mg_task_reg
+ MG_REG_DRV_CTRL
, value
);
311 static int mg_dsk_io_cmd(uint32_t sect_num
, uint32_t cnt
, uint8_t cmd
)
313 struct target
*target
= mflash_bank
->target
;
314 uint32_t mg_task_reg
= mflash_bank
->base
+ MG_REG_OFFSET
;
318 ret
= mg_dsk_wait(mg_io_wait_rdy_noerr
, MG_OEM_DISK_WAIT_TIME_NORMAL
);
322 value
= mg_io_rval_dev_drv_master
| mg_io_rval_dev_lba_mode
|((sect_num
>> 24) & 0xf);
324 ret
= target_write_u8(target
, mg_task_reg
+ MG_REG_DRV_HEAD
, value
);
325 ret
|= target_write_u8(target
, mg_task_reg
+ MG_REG_SECT_CNT
, (uint8_t)cnt
);
326 ret
|= target_write_u8(target
, mg_task_reg
+ MG_REG_SECT_NUM
, (uint8_t)sect_num
);
327 ret
|= target_write_u8(target
, mg_task_reg
+ MG_REG_CYL_LOW
, (uint8_t)(sect_num
>> 8));
328 ret
|= target_write_u8(target
, mg_task_reg
+ MG_REG_CYL_HIGH
, (uint8_t)(sect_num
>> 16));
333 return target_write_u8(target
, mg_task_reg
+ MG_REG_COMMAND
, cmd
);
336 static int mg_dsk_drv_info(void)
338 struct target
*target
= mflash_bank
->target
;
339 uint32_t mg_buff
= mflash_bank
->base
+ MG_BUFFER_OFFSET
;
342 if ((ret
= mg_dsk_io_cmd(0, 1, mg_io_cmd_identify
)) != ERROR_OK
)
345 ret
= mg_dsk_wait(mg_io_wait_drq
, MG_OEM_DISK_WAIT_TIME_NORMAL
);
349 LOG_INFO("mflash: read drive info");
351 if (! mflash_bank
->drv_info
)
352 mflash_bank
->drv_info
= malloc(sizeof(struct mg_drv_info
));
354 ret
= target_read_memory(target
, mg_buff
, 2,
355 sizeof(mg_io_type_drv_info
) >> 1,
356 (uint8_t *)&mflash_bank
->drv_info
->drv_id
);
360 mflash_bank
->drv_info
->tot_sects
= (uint32_t)(mflash_bank
->drv_info
->drv_id
.total_user_addressable_sectors_hi
<< 16)
361 + mflash_bank
->drv_info
->drv_id
.total_user_addressable_sectors_lo
;
363 return target_write_u8(target
, mflash_bank
->base
+ MG_REG_OFFSET
+ MG_REG_COMMAND
, mg_io_cmd_confirm_read
);
366 static int mg_mflash_rst(void)
370 if ((ret
= mg_init_gpio()) != ERROR_OK
)
373 if ((ret
= mg_hdrst(0)) != ERROR_OK
)
376 if ((ret
= mg_dsk_wait(mg_io_wait_bsy
, MG_OEM_DISK_WAIT_TIME_LONG
)) != ERROR_OK
)
379 if ((ret
= mg_hdrst(1)) != ERROR_OK
)
382 if ((ret
= mg_dsk_wait(mg_io_wait_not_bsy
, MG_OEM_DISK_WAIT_TIME_LONG
)) != ERROR_OK
)
385 if ((ret
= mg_dsk_srst(1)) != ERROR_OK
)
388 if ((ret
= mg_dsk_wait(mg_io_wait_bsy
, MG_OEM_DISK_WAIT_TIME_LONG
)) != ERROR_OK
)
391 if ((ret
= mg_dsk_srst(0)) != ERROR_OK
)
394 if ((ret
= mg_dsk_wait(mg_io_wait_not_bsy
, MG_OEM_DISK_WAIT_TIME_LONG
)) != ERROR_OK
)
397 LOG_INFO("mflash: reset ok");
402 static int mg_mflash_probe(void)
406 if ((ret
= mg_mflash_rst()) != ERROR_OK
)
409 return mg_dsk_drv_info();
412 COMMAND_HANDLER(mg_probe_cmd
)
416 ret
= mg_mflash_probe();
418 if (ret
== ERROR_OK
) {
419 command_print(CMD_CTX
, "mflash (total %" PRIu32
" sectors) found at 0x%8.8" PRIx32
"",
420 mflash_bank
->drv_info
->tot_sects
, mflash_bank
->base
);
426 static int mg_mflash_do_read_sects(void *buff
, uint32_t sect_num
, uint32_t sect_cnt
)
430 struct target
*target
= mflash_bank
->target
;
431 uint8_t *buff_ptr
= buff
;
433 if ((ret
= mg_dsk_io_cmd(sect_num
, sect_cnt
, mg_io_cmd_read
)) != ERROR_OK
)
436 address
= mflash_bank
->base
+ MG_BUFFER_OFFSET
;
438 struct duration bench
;
439 duration_start(&bench
);
441 for (i
= 0; i
< sect_cnt
; i
++) {
442 ret
= mg_dsk_wait(mg_io_wait_drq
, MG_OEM_DISK_WAIT_TIME_NORMAL
);
446 ret
= target_read_memory(target
, address
, 2, MG_MFLASH_SECTOR_SIZE
/ 2, buff_ptr
);
450 buff_ptr
+= MG_MFLASH_SECTOR_SIZE
;
452 ret
= target_write_u8(target
, mflash_bank
->base
+ MG_REG_OFFSET
+ MG_REG_COMMAND
, mg_io_cmd_confirm_read
);
456 LOG_DEBUG("mflash: %" PRIu32
" (0x%8.8" PRIx32
") sector read", sect_num
+ i
, (sect_num
+ i
) * MG_MFLASH_SECTOR_SIZE
);
458 ret
= duration_measure(&bench
);
459 if ((ERROR_OK
== ret
) && (duration_elapsed(&bench
) > 3)) {
460 LOG_INFO("mflash: read %" PRIu32
"'th sectors", sect_num
+ i
);
461 duration_start(&bench
);
465 return mg_dsk_wait(mg_io_wait_rdy
, MG_OEM_DISK_WAIT_TIME_NORMAL
);
468 static int mg_mflash_read_sects(void *buff
, uint32_t sect_num
, uint32_t sect_cnt
)
470 uint32_t quotient
, residue
, i
;
471 uint8_t *buff_ptr
= buff
;
474 quotient
= sect_cnt
>> 8;
475 residue
= sect_cnt
% 256;
477 for (i
= 0; i
< quotient
; i
++) {
478 LOG_DEBUG("mflash: sect num : %" PRIu32
" buff : %p",
480 ret
= mg_mflash_do_read_sects(buff_ptr
, sect_num
, 256);
485 buff_ptr
+= 256 * MG_MFLASH_SECTOR_SIZE
;
489 LOG_DEBUG("mflash: sect num : %" PRIx32
" buff : %p",
491 return mg_mflash_do_read_sects(buff_ptr
, sect_num
, residue
);
497 static int mg_mflash_do_write_sects(void *buff
, uint32_t sect_num
, uint32_t sect_cnt
,
502 struct target
*target
= mflash_bank
->target
;
503 uint8_t *buff_ptr
= buff
;
505 if ((ret
= mg_dsk_io_cmd(sect_num
, sect_cnt
, cmd
)) != ERROR_OK
)
508 address
= mflash_bank
->base
+ MG_BUFFER_OFFSET
;
510 struct duration bench
;
511 duration_start(&bench
);
513 for (i
= 0; i
< sect_cnt
; i
++) {
514 ret
= mg_dsk_wait(mg_io_wait_drq
, MG_OEM_DISK_WAIT_TIME_NORMAL
);
518 ret
= target_write_memory(target
, address
, 2, MG_MFLASH_SECTOR_SIZE
/ 2, buff_ptr
);
522 buff_ptr
+= MG_MFLASH_SECTOR_SIZE
;
524 ret
= target_write_u8(target
, mflash_bank
->base
+ MG_REG_OFFSET
+ MG_REG_COMMAND
, mg_io_cmd_confirm_write
);
528 LOG_DEBUG("mflash: %" PRIu32
" (0x%8.8" PRIx32
") sector write", sect_num
+ i
, (sect_num
+ i
) * MG_MFLASH_SECTOR_SIZE
);
530 ret
= duration_measure(&bench
);
531 if ((ERROR_OK
== ret
) && (duration_elapsed(&bench
) > 3)) {
532 LOG_INFO("mflash: wrote %" PRIu32
"'th sectors", sect_num
+ i
);
533 duration_start(&bench
);
537 if (cmd
== mg_io_cmd_write
)
538 ret
= mg_dsk_wait(mg_io_wait_rdy
, MG_OEM_DISK_WAIT_TIME_NORMAL
);
540 ret
= mg_dsk_wait(mg_io_wait_rdy
, MG_OEM_DISK_WAIT_TIME_LONG
);
545 static int mg_mflash_write_sects(void *buff
, uint32_t sect_num
, uint32_t sect_cnt
)
547 uint32_t quotient
, residue
, i
;
548 uint8_t *buff_ptr
= buff
;
551 quotient
= sect_cnt
>> 8;
552 residue
= sect_cnt
% 256;
554 for (i
= 0; i
< quotient
; i
++) {
555 LOG_DEBUG("mflash: sect num : %" PRIu32
"buff : %p", sect_num
,
557 ret
= mg_mflash_do_write_sects(buff_ptr
, sect_num
, 256, mg_io_cmd_write
);
562 buff_ptr
+= 256 * MG_MFLASH_SECTOR_SIZE
;
566 LOG_DEBUG("mflash: sect num : %" PRIu32
" buff : %p", sect_num
,
568 return mg_mflash_do_write_sects(buff_ptr
, sect_num
, residue
, mg_io_cmd_write
);
574 static int mg_mflash_read (uint32_t addr
, uint8_t *buff
, uint32_t len
)
576 uint8_t *buff_ptr
= buff
;
577 uint8_t sect_buff
[MG_MFLASH_SECTOR_SIZE
];
578 uint32_t cur_addr
, next_sec_addr
, end_addr
, cnt
, sect_num
;
583 end_addr
= addr
+ len
;
585 if (cur_addr
& MG_MFLASH_SECTOR_SIZE_MASK
) {
587 next_sec_addr
= (cur_addr
+ MG_MFLASH_SECTOR_SIZE
) & ~MG_MFLASH_SECTOR_SIZE_MASK
;
588 sect_num
= cur_addr
>> MG_MFLASH_SECTOR_SIZE_SHIFT
;
589 ret
= mg_mflash_read_sects(sect_buff
, sect_num
, 1);
593 if (end_addr
< next_sec_addr
) {
594 memcpy(buff_ptr
, sect_buff
+ (cur_addr
& MG_MFLASH_SECTOR_SIZE_MASK
), end_addr
- cur_addr
);
595 LOG_DEBUG("mflash: copies %" PRIu32
" byte from sector offset 0x%8.8" PRIx32
"", end_addr
- cur_addr
, cur_addr
);
598 memcpy(buff_ptr
, sect_buff
+ (cur_addr
& MG_MFLASH_SECTOR_SIZE_MASK
), next_sec_addr
- cur_addr
);
599 LOG_DEBUG("mflash: copies %" PRIu32
" byte from sector offset 0x%8.8" PRIx32
"", next_sec_addr
- cur_addr
, cur_addr
);
600 buff_ptr
+= (next_sec_addr
- cur_addr
);
601 cur_addr
= next_sec_addr
;
605 if (cur_addr
< end_addr
) {
607 sect_num
= cur_addr
>> MG_MFLASH_SECTOR_SIZE_SHIFT
;
608 next_sec_addr
= cur_addr
+ MG_MFLASH_SECTOR_SIZE
;
610 while (next_sec_addr
<= end_addr
) {
612 next_sec_addr
+= MG_MFLASH_SECTOR_SIZE
;
616 if ((ret
= mg_mflash_read_sects(buff_ptr
, sect_num
, cnt
)) != ERROR_OK
)
619 buff_ptr
+= cnt
* MG_MFLASH_SECTOR_SIZE
;
620 cur_addr
+= cnt
* MG_MFLASH_SECTOR_SIZE
;
622 if (cur_addr
< end_addr
) {
624 sect_num
= cur_addr
>> MG_MFLASH_SECTOR_SIZE_SHIFT
;
625 ret
= mg_mflash_read_sects(sect_buff
, sect_num
, 1);
629 memcpy(buff_ptr
, sect_buff
, end_addr
- cur_addr
);
630 LOG_DEBUG("mflash: copies %u byte", (unsigned)(end_addr
- cur_addr
));
638 static int mg_mflash_write(uint32_t addr
, uint8_t *buff
, uint32_t len
)
640 uint8_t *buff_ptr
= buff
;
641 uint8_t sect_buff
[MG_MFLASH_SECTOR_SIZE
];
642 uint32_t cur_addr
, next_sec_addr
, end_addr
, cnt
, sect_num
;
647 end_addr
= addr
+ len
;
649 if (cur_addr
& MG_MFLASH_SECTOR_SIZE_MASK
) {
651 next_sec_addr
= (cur_addr
+ MG_MFLASH_SECTOR_SIZE
) & ~MG_MFLASH_SECTOR_SIZE_MASK
;
652 sect_num
= cur_addr
>> MG_MFLASH_SECTOR_SIZE_SHIFT
;
653 ret
= mg_mflash_read_sects(sect_buff
, sect_num
, 1);
657 if (end_addr
< next_sec_addr
) {
658 memcpy(sect_buff
+ (cur_addr
& MG_MFLASH_SECTOR_SIZE_MASK
), buff_ptr
, end_addr
- cur_addr
);
659 LOG_DEBUG("mflash: copies %" PRIu32
" byte to sector offset 0x%8.8" PRIx32
"", end_addr
- cur_addr
, cur_addr
);
662 memcpy(sect_buff
+ (cur_addr
& MG_MFLASH_SECTOR_SIZE_MASK
), buff_ptr
, next_sec_addr
- cur_addr
);
663 LOG_DEBUG("mflash: copies %" PRIu32
" byte to sector offset 0x%8.8" PRIx32
"", next_sec_addr
- cur_addr
, cur_addr
);
664 buff_ptr
+= (next_sec_addr
- cur_addr
);
665 cur_addr
= next_sec_addr
;
668 ret
= mg_mflash_write_sects(sect_buff
, sect_num
, 1);
673 if (cur_addr
< end_addr
) {
675 sect_num
= cur_addr
>> MG_MFLASH_SECTOR_SIZE_SHIFT
;
676 next_sec_addr
= cur_addr
+ MG_MFLASH_SECTOR_SIZE
;
678 while (next_sec_addr
<= end_addr
) {
680 next_sec_addr
+= MG_MFLASH_SECTOR_SIZE
;
684 if ((ret
= mg_mflash_write_sects(buff_ptr
, sect_num
, cnt
)) != ERROR_OK
)
687 buff_ptr
+= cnt
* MG_MFLASH_SECTOR_SIZE
;
688 cur_addr
+= cnt
* MG_MFLASH_SECTOR_SIZE
;
690 if (cur_addr
< end_addr
) {
692 sect_num
= cur_addr
>> MG_MFLASH_SECTOR_SIZE_SHIFT
;
693 ret
= mg_mflash_read_sects(sect_buff
, sect_num
, 1);
697 memcpy(sect_buff
, buff_ptr
, end_addr
- cur_addr
);
698 LOG_DEBUG("mflash: copies %" PRIu32
" byte", end_addr
- cur_addr
);
699 ret
= mg_mflash_write_sects(sect_buff
, sect_num
, 1);
706 COMMAND_HANDLER(mg_write_cmd
)
708 uint32_t address
, cnt
, res
, i
;
710 struct fileio fileio
;
714 return ERROR_COMMAND_SYNTAX_ERROR
;
717 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[2], address
);
719 ret
= fileio_open(&fileio
, CMD_ARGV
[1], FILEIO_READ
, FILEIO_BINARY
);
724 buffer
= malloc(MG_FILEIO_CHUNK
);
726 fileio_close(&fileio
);
729 int retval
= fileio_size(&fileio
, &filesize
);
730 if (retval
!= ERROR_OK
) {
731 fileio_close(&fileio
);
735 cnt
= filesize
/ MG_FILEIO_CHUNK
;
736 res
= filesize
% MG_FILEIO_CHUNK
;
738 struct duration bench
;
739 duration_start(&bench
);
742 for (i
= 0; i
< cnt
; i
++) {
743 if ((ret
= fileio_read(&fileio
, MG_FILEIO_CHUNK
, buffer
, &buf_cnt
)) !=
745 goto mg_write_cmd_err
;
746 if ((ret
= mg_mflash_write(address
, buffer
, MG_FILEIO_CHUNK
)) != ERROR_OK
)
747 goto mg_write_cmd_err
;
748 address
+= MG_FILEIO_CHUNK
;
752 if ((ret
= fileio_read(&fileio
, res
, buffer
, &buf_cnt
)) != ERROR_OK
)
753 goto mg_write_cmd_err
;
754 if ((ret
= mg_mflash_write(address
, buffer
, res
)) != ERROR_OK
)
755 goto mg_write_cmd_err
;
758 if (duration_measure(&bench
) == ERROR_OK
)
760 command_print(CMD_CTX
, "wrote %ld bytes from file %s "
761 "in %fs (%0.3f kB/s)", (long)filesize
, CMD_ARGV
[1],
762 duration_elapsed(&bench
), duration_kbps(&bench
, filesize
));
766 fileio_close(&fileio
);
772 fileio_close(&fileio
);
777 COMMAND_HANDLER(mg_dump_cmd
)
779 uint32_t address
, size
, cnt
, res
, i
;
781 struct fileio fileio
;
785 return ERROR_COMMAND_SYNTAX_ERROR
;
788 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[2], address
);
789 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[3], size
);
791 ret
= fileio_open(&fileio
, CMD_ARGV
[1], FILEIO_WRITE
, FILEIO_BINARY
);
795 buffer
= malloc(MG_FILEIO_CHUNK
);
797 fileio_close(&fileio
);
801 cnt
= size
/ MG_FILEIO_CHUNK
;
802 res
= size
% MG_FILEIO_CHUNK
;
804 struct duration bench
;
805 duration_start(&bench
);
808 for (i
= 0; i
< cnt
; i
++) {
809 if ((ret
= mg_mflash_read(address
, buffer
, MG_FILEIO_CHUNK
)) != ERROR_OK
)
810 goto mg_dump_cmd_err
;
811 if ((ret
= fileio_write(&fileio
, MG_FILEIO_CHUNK
, buffer
, &size_written
))
813 goto mg_dump_cmd_err
;
814 address
+= MG_FILEIO_CHUNK
;
818 if ((ret
= mg_mflash_read(address
, buffer
, res
)) != ERROR_OK
)
819 goto mg_dump_cmd_err
;
820 if ((ret
= fileio_write(&fileio
, res
, buffer
, &size_written
)) != ERROR_OK
)
821 goto mg_dump_cmd_err
;
824 if (duration_measure(&bench
) == ERROR_OK
)
826 command_print(CMD_CTX
, "dump image (address 0x%8.8" PRIx32
" "
827 "size %" PRIu32
") to file %s in %fs (%0.3f kB/s)",
828 address
, size
, CMD_ARGV
[1],
829 duration_elapsed(&bench
), duration_kbps(&bench
, size
));
833 fileio_close(&fileio
);
839 fileio_close(&fileio
);
844 static int mg_set_feature(mg_feature_id feature
, mg_feature_val config
)
846 struct target
*target
= mflash_bank
->target
;
847 uint32_t mg_task_reg
= mflash_bank
->base
+ MG_REG_OFFSET
;
850 if ((ret
= mg_dsk_wait(mg_io_wait_rdy_noerr
, MG_OEM_DISK_WAIT_TIME_NORMAL
))
854 ret
= target_write_u8(target
, mg_task_reg
+ MG_REG_FEATURE
, feature
);
855 ret
|= target_write_u8(target
, mg_task_reg
+ MG_REG_SECT_CNT
, config
);
856 ret
|= target_write_u8(target
, mg_task_reg
+ MG_REG_COMMAND
,
857 mg_io_cmd_set_feature
);
862 static int mg_is_valid_pll(double XIN
, int N
, double CLK_OUT
, int NO
)
865 double v2
= CLK_OUT
* NO
;
867 if (v1
<1000000 || v1
> 15000000 || v2
< 100000000 || v2
> 500000000)
868 return ERROR_MG_INVALID_PLL
;
873 static int mg_pll_get_M(unsigned short feedback_div
)
877 for (i
= 1, M
= 0; i
< 512; i
<<= 1, feedback_div
>>= 1)
878 M
+= (feedback_div
& 1) * i
;
883 static int mg_pll_get_N(unsigned char input_div
)
887 for (i
= 1, N
= 0; i
< 32; i
<<= 1, input_div
>>= 1)
888 N
+= (input_div
& 1) * i
;
893 static int mg_pll_get_NO(unsigned char output_div
)
897 for (i
= 0, NO
= 1; i
< 2; ++i
, output_div
>>= 1)
904 static double mg_do_calc_pll(double XIN
, mg_pll_t
* p_pll_val
, int is_approximate
)
913 if (is_approximate
) {
918 for (i
= 0; i
< MG_PLL_MAX_FEEDBACKDIV_VAL
; ++i
) {
921 for (j
= 0; j
< MG_PLL_MAX_INPUTDIV_VAL
; ++j
) {
924 for (k
= 0; k
< MG_PLL_MAX_OUTPUTDIV_VAL
; ++k
) {
925 NO
= mg_pll_get_NO(k
);
927 CLK_OUT
= XIN
* ((double)M
/ N
) / NO
;
929 if ((int)((CLK_OUT
+ ROUND
) / DIV
)
930 == (int)(MG_PLL_CLK_OUT
/ DIV
)) {
931 if (mg_is_valid_pll(XIN
, N
, CLK_OUT
, NO
) == ERROR_OK
)
933 p_pll_val
->lock_cyc
= (int)(XIN
* MG_PLL_STD_LOCKCYCLE
/ MG_PLL_STD_INPUTCLK
);
934 p_pll_val
->feedback_div
= i
;
935 p_pll_val
->input_div
= j
;
936 p_pll_val
->output_div
= k
;
948 static double mg_calc_pll(double XIN
, mg_pll_t
*p_pll_val
)
952 CLK_OUT
= mg_do_calc_pll(XIN
, p_pll_val
, 0);
955 return mg_do_calc_pll(XIN
, p_pll_val
, 1);
960 static int mg_verify_interface(void)
962 uint16_t buff
[MG_MFLASH_SECTOR_SIZE
>> 1];
964 uint32_t address
= mflash_bank
->base
+ MG_BUFFER_OFFSET
;
965 struct target
*target
= mflash_bank
->target
;
968 for (j
= 0; j
< 10; j
++) {
969 for (i
= 0; i
< MG_MFLASH_SECTOR_SIZE
>> 1; i
++)
972 ret
= target_write_memory(target
, address
, 2,
973 MG_MFLASH_SECTOR_SIZE
/ 2, (uint8_t *)buff
);
977 memset(buff
, 0xff, MG_MFLASH_SECTOR_SIZE
);
979 ret
= target_read_memory(target
, address
, 2,
980 MG_MFLASH_SECTOR_SIZE
/ 2, (uint8_t *)buff
);
984 for (i
= 0; i
< MG_MFLASH_SECTOR_SIZE
>> 1; i
++) {
986 LOG_ERROR("mflash: verify interface fail");
987 return ERROR_MG_INTERFACE
;
992 LOG_INFO("mflash: verify interface ok");
996 static const char g_strSEG_SerialNum
[20] = {
997 'G','m','n','i','-','e','e','S','g','a','e','l',
998 0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20
1001 static const char g_strSEG_FWRev
[8] = {
1002 'F','X','L','T','2','v','0','.'
1005 static const char g_strSEG_ModelNum
[40] = {
1006 'F','X','A','L','H','S','2',0x20,'0','0','s','7',
1007 0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,
1008 0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,
1009 0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20
1012 static void mg_gen_ataid(mg_io_type_drv_info
*pSegIdDrvInfo
)
1014 /* b15 is ATA device(0) , b7 is Removable Media Device */
1015 pSegIdDrvInfo
->general_configuration
= 0x045A;
1016 /* 128MB : Cylinder=> 977 , Heads=> 8 , Sectors=> 32
1017 * 256MB : Cylinder=> 980 , Heads=> 16 , Sectors=> 32
1018 * 384MB : Cylinder=> 745 , Heads=> 16 , Sectors=> 63
1020 pSegIdDrvInfo
->number_of_cylinders
= 0x02E9;
1021 pSegIdDrvInfo
->reserved1
= 0x0;
1022 pSegIdDrvInfo
->number_of_heads
= 0x10;
1023 pSegIdDrvInfo
->unformatted_bytes_per_track
= 0x0;
1024 pSegIdDrvInfo
->unformatted_bytes_per_sector
= 0x0;
1025 pSegIdDrvInfo
->sectors_per_track
= 0x3F;
1026 pSegIdDrvInfo
->vendor_unique1
[0] = 0x000B;
1027 pSegIdDrvInfo
->vendor_unique1
[1] = 0x7570;
1028 pSegIdDrvInfo
->vendor_unique1
[2] = 0x8888;
1030 memcpy(pSegIdDrvInfo
->serial_number
, (void *)g_strSEG_SerialNum
,20);
1031 /* 0x2 : dual buffer */
1032 pSegIdDrvInfo
->buffer_type
= 0x2;
1033 /* buffer size : 2KB */
1034 pSegIdDrvInfo
->buffer_sector_size
= 0x800;
1035 pSegIdDrvInfo
->number_of_ecc_bytes
= 0;
1037 memcpy(pSegIdDrvInfo
->firmware_revision
, (void *)g_strSEG_FWRev
,8);
1039 memcpy(pSegIdDrvInfo
->model_number
, (void *)g_strSEG_ModelNum
,40);
1041 pSegIdDrvInfo
->maximum_block_transfer
= 0x4;
1042 pSegIdDrvInfo
->vendor_unique2
= 0x0;
1043 pSegIdDrvInfo
->dword_io
= 0x00;
1044 /* b11 : IORDY support(PIO Mode 4), b10 : Disable/Enbale IORDY
1045 * b9 : LBA support, b8 : DMA mode support
1047 pSegIdDrvInfo
->capabilities
= 0x1 << 9;
1049 pSegIdDrvInfo
->reserved2
= 0x4000;
1050 pSegIdDrvInfo
->vendor_unique3
= 0x00;
1051 /* PIOMode-2 support */
1052 pSegIdDrvInfo
->pio_cycle_timing_mode
= 0x02;
1053 pSegIdDrvInfo
->vendor_unique4
= 0x00;
1054 /* MultiWord-2 support */
1055 pSegIdDrvInfo
->dma_cycle_timing_mode
= 0x00;
1056 /* b1 : word64~70 is valid
1057 * b0 : word54~58 are valid and reflect the current numofcyls,heads,sectors
1058 * b2 : If device supports Ultra DMA , set to one to vaildate word88
1060 pSegIdDrvInfo
->translation_fields_valid
= (0x1 << 1) | (0x1 << 0);
1061 pSegIdDrvInfo
->number_of_current_cylinders
= 0x02E9;
1062 pSegIdDrvInfo
->number_of_current_heads
= 0x10;
1063 pSegIdDrvInfo
->current_sectors_per_track
= 0x3F;
1064 pSegIdDrvInfo
->current_sector_capacity_lo
= 0x7570;
1065 pSegIdDrvInfo
->current_sector_capacity_hi
= 0x000B;
1067 pSegIdDrvInfo
->multi_sector_count
= 0x04;
1068 /* b8 : Multiple secotr setting valid , b[7:0] num of secotrs per block */
1069 pSegIdDrvInfo
->multi_sector_setting_valid
= 0x01;
1070 pSegIdDrvInfo
->total_user_addressable_sectors_lo
= 0x7570;
1071 pSegIdDrvInfo
->total_user_addressable_sectors_hi
= 0x000B;
1072 pSegIdDrvInfo
->single_dma_modes_supported
= 0x00;
1073 pSegIdDrvInfo
->single_dma_transfer_active
= 0x00;
1074 /* b2 :Multi-word DMA mode 2, b1 : Multi-word DMA mode 1 */
1075 pSegIdDrvInfo
->multi_dma_modes_supported
= (0x1 << 0);
1076 /* b2 :Multi-word DMA mode 2, b1 : Multi-word DMA mode 1 */
1077 pSegIdDrvInfo
->multi_dma_transfer_active
= (0x1 << 0);
1078 /* b0 : PIO Mode-3 support, b1 : PIO Mode-4 support */
1079 pSegIdDrvInfo
->adv_pio_mode
= 0x00;
1080 /* 480(0x1E0)nsec for Multi-word DMA mode0
1081 * 150(0x96) nsec for Multi-word DMA mode1
1082 * 120(0x78) nsec for Multi-word DMA mode2
1084 pSegIdDrvInfo
->min_dma_cyc
= 0x1E0;
1085 pSegIdDrvInfo
->recommend_dma_cyc
= 0x1E0;
1086 pSegIdDrvInfo
->min_pio_cyc_no_iordy
= 0x1E0;
1087 pSegIdDrvInfo
->min_pio_cyc_with_iordy
= 0x1E0;
1088 memset((void *)pSegIdDrvInfo
->reserved3
, 0x00, 22);
1089 /* b7 : ATA/ATAPI-7 ,b6 : ATA/ATAPI-6 ,b5 : ATA/ATAPI-5,b4 : ATA/ATAPI-4 */
1090 pSegIdDrvInfo
->major_ver_num
= 0x7E;
1091 /* 0x1C : ATA/ATAPI-6 T13 1532D revision1 */
1092 pSegIdDrvInfo
->minor_ver_num
= 0x19;
1093 /* NOP/READ BUFFER/WRITE BUFFER/Power management feature set support */
1094 pSegIdDrvInfo
->feature_cmd_set_suprt0
= 0x7068;
1095 /* Features/command set is valid/Advanced Pwr management/CFA feature set
1098 pSegIdDrvInfo
->feature_cmd_set_suprt1
= 0x400C;
1099 pSegIdDrvInfo
->feature_cmd_set_suprt2
= 0x4000;
1100 /* READ/WRITE BUFFER/PWR Management enable */
1101 pSegIdDrvInfo
->feature_cmd_set_en0
= 0x7000;
1102 /* CFA feature is disabled / Advancde power management disable */
1103 pSegIdDrvInfo
->feature_cmd_set_en1
= 0x0;
1104 pSegIdDrvInfo
->feature_cmd_set_en2
= 0x4000;
1105 pSegIdDrvInfo
->reserved4
= 0x0;
1106 /* 0x1 * 2minutes */
1107 pSegIdDrvInfo
->req_time_for_security_er_done
= 0x19;
1108 pSegIdDrvInfo
->req_time_for_enhan_security_er_done
= 0x19;
1109 /* Advanced power management level 1 */
1110 pSegIdDrvInfo
->adv_pwr_mgm_lvl_val
= 0x0;
1111 pSegIdDrvInfo
->reserved5
= 0x0;
1112 memset((void *)pSegIdDrvInfo
->reserved6
, 0x00, 68);
1113 /* Security mode feature is disabled */
1114 pSegIdDrvInfo
->security_stas
= 0x0;
1115 memset((void *)pSegIdDrvInfo
->vendor_uniq_bytes
, 0x00, 62);
1116 /* CFA power mode 1 support in maximum 200mA */
1117 pSegIdDrvInfo
->cfa_pwr_mode
= 0x0100;
1118 memset((void *)pSegIdDrvInfo
->reserved7
, 0x00, 190);
1121 static int mg_storage_config(void)
1126 if ((ret
= mg_set_feature(mg_feature_id_transmode
, mg_feature_val_trans_vcmd
))
1130 mg_gen_ataid((mg_io_type_drv_info
*)(void *)buff
);
1132 if ((ret
= mg_mflash_do_write_sects(buff
, 0, 1, mg_vcmd_update_stgdrvinfo
))
1136 if ((ret
= mg_set_feature(mg_feature_id_transmode
, mg_feature_val_trans_default
))
1140 LOG_INFO("mflash: storage config ok");
1144 static int mg_boot_config(void)
1149 if ((ret
= mg_set_feature(mg_feature_id_transmode
, mg_feature_val_trans_vcmd
))
1153 memset(buff
, 0xff, 512);
1155 buff
[0] = mg_op_mode_snd
; /* operation mode */
1156 buff
[1] = MG_UNLOCK_OTP_AREA
;
1157 buff
[2] = 4; /* boot size */
1158 *((uint32_t *)(void *)(buff
+ 4)) = 0; /* XIP size */
1160 if ((ret
= mg_mflash_do_write_sects(buff
, 0, 1, mg_vcmd_update_xipinfo
))
1164 if ((ret
= mg_set_feature(mg_feature_id_transmode
, mg_feature_val_trans_default
))
1168 LOG_INFO("mflash: boot config ok");
1172 static int mg_set_pll(mg_pll_t
*pll
)
1177 memset(buff
, 0xff, 512);
1178 /* PLL Lock cycle and Feedback 9bit Divider */
1179 memcpy(buff
, &pll
->lock_cyc
, sizeof(uint32_t));
1180 memcpy(buff
+ 4, &pll
->feedback_div
, sizeof(uint16_t));
1181 buff
[6] = pll
->input_div
; /* PLL Input 5bit Divider */
1182 buff
[7] = pll
->output_div
; /* PLL Output Divider */
1184 if ((ret
= mg_set_feature(mg_feature_id_transmode
, mg_feature_val_trans_vcmd
))
1188 if ((ret
= mg_mflash_do_write_sects(buff
, 0, 1, mg_vcmd_wr_pll
))
1192 if ((ret
= mg_set_feature(mg_feature_id_transmode
, mg_feature_val_trans_default
))
1196 LOG_INFO("mflash: set pll ok");
1200 static int mg_erase_nand(void)
1204 if ((ret
= mg_set_feature(mg_feature_id_transmode
, mg_feature_val_trans_vcmd
))
1208 if ((ret
= mg_mflash_do_write_sects(NULL
, 0, 0, mg_vcmd_purge_nand
))
1212 if ((ret
= mg_set_feature(mg_feature_id_transmode
, mg_feature_val_trans_default
))
1216 LOG_INFO("mflash: erase nand ok");
1220 COMMAND_HANDLER(mg_config_cmd
)
1226 if ((ret
= mg_verify_interface()) != ERROR_OK
)
1229 if ((ret
= mg_mflash_rst()) != ERROR_OK
)
1234 if (!strcmp(CMD_ARGV
[1], "boot"))
1235 return mg_boot_config();
1236 else if (!strcmp(CMD_ARGV
[1], "storage"))
1237 return mg_storage_config();
1239 return ERROR_COMMAND_NOTFOUND
;
1242 if (!strcmp(CMD_ARGV
[1], "pll")) {
1244 COMMAND_PARSE_NUMBER(ulong
, CMD_ARGV
[2], freq
);
1247 if (fin
> MG_PLL_CLK_OUT
) {
1248 LOG_ERROR("mflash: input freq. is too large");
1249 return ERROR_MG_INVALID_OSC
;
1252 fout
= mg_calc_pll(fin
, &pll
);
1255 LOG_ERROR("mflash: cannot generate valid pll");
1256 return ERROR_MG_INVALID_PLL
;
1259 LOG_INFO("mflash: Fout=%" PRIu32
" Hz, feedback=%u,"
1260 "indiv=%u, outdiv=%u, lock=%u",
1261 (uint32_t)fout
, pll
.feedback_div
,
1262 pll
.input_div
, pll
.output_div
,
1265 if ((ret
= mg_erase_nand()) != ERROR_OK
)
1268 return mg_set_pll(&pll
);
1270 return ERROR_COMMAND_NOTFOUND
;
1273 return ERROR_COMMAND_SYNTAX_ERROR
;
1277 static const struct command_registration mflash_exec_command_handlers
[] = {
1280 .handler
= mg_probe_cmd
,
1281 .mode
= COMMAND_EXEC
,
1282 .help
= "Detect bank configuration information",
1286 .handler
= mg_write_cmd
,
1287 .mode
= COMMAND_EXEC
,
1288 /* FIXME bank_num is unused */
1289 .usage
= "bank_num filename address",
1290 .help
= "Write binary file at the specified address.",
1294 .handler
= mg_dump_cmd
,
1295 .mode
= COMMAND_EXEC
,
1296 /* FIXME bank_num is unused */
1297 .usage
= "bank_num filename address size",
1298 .help
= "Write specified number of bytes from a binary file "
1299 "to the specified, address.",
1303 .handler
= mg_config_cmd
,
1304 .mode
= COMMAND_EXEC
,
1305 .help
= "Configure MFLASH options.",
1306 .usage
= "('boot'|'storage'|'pll' frequency)",
1308 COMMAND_REGISTRATION_DONE
1311 static int mflash_init_drivers(struct command_context
*cmd_ctx
)
1315 return register_commands(cmd_ctx
, NULL
, mflash_exec_command_handlers
);
1318 COMMAND_HANDLER(handle_mflash_init_command
)
1321 return ERROR_COMMAND_SYNTAX_ERROR
;
1323 static bool mflash_initialized
= false;
1324 if (mflash_initialized
)
1326 LOG_INFO("'mflash init' has already been called");
1329 mflash_initialized
= true;
1331 LOG_DEBUG("Initializing mflash devices...");
1332 return mflash_init_drivers(CMD_CTX
);
1335 COMMAND_HANDLER(mg_bank_cmd
)
1337 struct target
*target
;
1342 return ERROR_COMMAND_SYNTAX_ERROR
;
1345 if ((target
= get_target(CMD_ARGV
[3])) == NULL
)
1347 LOG_ERROR("target '%s' not defined", CMD_ARGV
[3]);
1351 mflash_bank
= calloc(sizeof(struct mflash_bank
), 1);
1352 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], mflash_bank
->base
);
1353 /// @todo Verify how this parsing should work, then document it.
1355 mflash_bank
->rst_pin
.num
= strtoul(CMD_ARGV
[2], &str
, 0);
1357 mflash_bank
->rst_pin
.port
[0] = (uint16_t)
1358 tolower((unsigned)str
[0]);
1360 mflash_bank
->target
= target
;
1362 for (i
= 0; mflash_gpio
[i
] ; i
++) {
1363 if (! strcmp(mflash_gpio
[i
]->name
, CMD_ARGV
[0])) {
1364 mflash_bank
->gpio_drv
= mflash_gpio
[i
];
1368 if (! mflash_bank
->gpio_drv
) {
1369 LOG_ERROR("%s is unsupported soc", CMD_ARGV
[0]);
1370 return ERROR_MG_UNSUPPORTED_SOC
;
1376 static const struct command_registration mflash_config_command_handlers
[] = {
1379 .handler
= mg_bank_cmd
,
1380 .mode
= COMMAND_CONFIG
,
1381 .help
= "configure a mflash device bank",
1382 .usage
= "soc_type base_addr pin_id target",
1386 .mode
= COMMAND_CONFIG
,
1387 .handler
= handle_mflash_init_command
,
1388 .help
= "initialize mflash devices",
1390 COMMAND_REGISTRATION_DONE
1392 static const struct command_registration mflash_command_handler
[] = {
1395 .mode
= COMMAND_ANY
,
1396 .help
= "mflash command group",
1397 .chain
= mflash_config_command_handlers
,
1399 COMMAND_REGISTRATION_DONE
1401 int mflash_register_commands(struct command_context
*cmd_ctx
)
1403 return register_commands(cmd_ctx
, NULL
, mflash_command_handler
);