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armv7a: cache ttbcr and ttb0/1 on debug state entry
2018-03-11 Matthias Welwarskyarmv7a: cache ttbcr and ttb0/1 on debug state entry
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
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2017-04-23 Matthias Welwarskyboard: introduce base config for TI BeagleBone family...
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
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2016-02-13 Matthias Welwarskyjtag ftdi: sample TDO on falling edge of TCK
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
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2016-01-22 Matthias Welwarskyam437x: always use highest possible JTAG clock.
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
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2016-01-22 Matthias Welwarskyadiv5: introduce optional dap_sync() function
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
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2016-01-22 Matthias Welwarskyadi_v5_jtag: implement DAP WAIT support
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
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2015-12-29 Matthias Welwarskycortex_a: add 'dacrfixup' to cortex-a command group
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
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2015-12-29 Matthias WelwarskyAM335x: allow simultaneous debugging of A8 and M3 cores
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
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2015-12-29 Matthias Welwarskyarm_debug: optimize DP and AP reads over JTAG
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
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2015-12-29 Matthias Welwarskycortex_a: select APB-AP as the default AP
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
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2015-12-01 Matthias Welwarskycortex_a: fix fast-mode memory reads
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
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2015-11-30 Matthias Welwarskycortex_a: replace cortex_a_check_address function
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
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2015-11-30 Matthias Welwarskycortex_a: rework mmu manipulation
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
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2015-11-30 Matthias Welwarskycortex_a: force cache and tlb bypass when cpu is in...
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
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2015-11-30 Matthias Welwarskyarmv7a: fix-up dcache clean and flush functions inner...
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
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2015-11-30 Matthias Welwarskycortex_a: Update instruction cache after setting a...
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
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2015-11-30 Matthias Welwarskyarmv7a: correctly handle invalidation of inner data...
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
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2015-11-30 Matthias Welwarskyarmv7a: fix debug messages regarding cache on/off state
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
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2015-11-30 Matthias Welwarskyarmv7a: rework automatic flush-on-write handling
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
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2015-11-30 Matthias Welwarskyarmv7a: add d-cache virtual address range flush function
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
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2015-11-30 Matthias Welwarskyarmv7a: remove indirection for cache info handler
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
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2015-11-30 Matthias Welwarskyarmv7a: fix handling of inner caches
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
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2015-11-30 Matthias Welwarskyarmv7a: remove special l2x flush-all and cache-info...
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
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2015-11-30 Matthias Welwarskyarmv7a: rename l2_cache to outer_cache
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
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2015-11-05 Matthias Welwarskyarmv7a: correct calculation of ttbr0_mask
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
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2015-11-05 Matthias Welwarskyarmv7a: re-read ttb information if ttbcr changes
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
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2015-11-04 Matthias WelwarskyRevert "board: don't hardcode interface for ti_beaglebone"
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
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2015-11-03 Matthias Welwarskyboard: don't hardcode interface for ti_beaglebone
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
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