From ba00ef3c404ed816a1880aa1023b2673232b9728 Mon Sep 17 00:00:00 2001 From: Vandra Akos Date: Sun, 27 May 2012 12:36:55 +0200 Subject: [PATCH] lpc1768.cfg abstracted and moved to lpc17xx.cfg - Moved variant-independent code to lpc17xx.cfg, which will be included from lpc17??.cfg files automatically. - lpc1768.cfg filled with variant-dependent code. Change-Id: I7dabe6ed7da7be640ed38c13aaaa096b8796d9a0 Signed-off-by: Vandra Akos Reviewed-on: http://openocd.zylin.com/675 Tested-by: jenkins Reviewed-by: Freddie Chopin Reviewed-by: Spencer Oliver --- tcl/target/lpc1768.cfg | 103 ++++++-------------------------- tcl/target/{lpc1768.cfg => lpc17xx.cfg} | 25 +++++--- 2 files changed, 33 insertions(+), 95 deletions(-) rewrite tcl/target/lpc1768.cfg (83%) copy tcl/target/{lpc1768.cfg => lpc17xx.cfg} (68%) diff --git a/tcl/target/lpc1768.cfg b/tcl/target/lpc1768.cfg dissimilarity index 83% index 8bcab9ba5..a436b30f6 100644 --- a/tcl/target/lpc1768.cfg +++ b/tcl/target/lpc1768.cfg @@ -1,86 +1,17 @@ -# NXP LPC1768 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM, - -# LPC17xx chips support both JTAG and SWD transports. -# Adapt based on what transport is active. -source [find target/swj-dp.tcl] - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME lpc1768 -} - -# After reset the chip is clocked by the ~4MHz internal RC oscillator. -# When board-specific code (reset-init handler or device firmware) -# configures another oscillator and/or PLL0, set CCLK to match; if -# you don't, then flash erase and write operations may misbehave. -# (The ROM code doing those updates cares about core clock speed...) -# -# CCLK is the core clock frequency in KHz -if { [info exists CCLK] } { - set _CCLK $CCLK -} else { - set _CCLK 4000 -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x4ba00477 -} - -if { [info exists CPURAMSIZE] } { - set _CPURAMSIZE $CPURAMSIZE -} else { - set _CPURAMSIZE 0x8000 -} - -if { [info exists CPUROMSIZE] } { - set _CPUROMSIZE $CPUROMSIZE -} else { - set _CPUROMSIZE 0x80000 -} - -#delays on reset lines -adapter_nsrst_delay 200 -jtag_ntrst_delay 200 - -#jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID -swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m3 -chain-position $_TARGETNAME - -# LPC1768 has 32kB of SRAM In the ARMv7-M "Code" area (at 0x10000000) -# and 32K more on AHB, in the ARMv7-M "SRAM" area, (at 0x2007c000). -$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_CPURAMSIZE - -# LPC1768 has 512kB of flash memory, managed by ROM code (including a -# boot loader which verifies the flash exception table's checksum). -# flash bank lpc2000 0 0 [calc checksum] -set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME lpc2000 0x0 $_CPUROMSIZE 0 0 $_TARGETNAME \ - lpc1700 $_CCLK calc_checksum - -# Run with *real slow* clock by default since the -# boot rom could have been playing with the PLL, so -# we have no idea what clock the target is running at. -adapter_khz 10 - -$_TARGETNAME configure -event reset-init { - # Do not remap 0x0000-0x0020 to anything but the flash (i.e. select - # "User Flash Mode" where interrupt vectors are _not_ remapped, - # and reside in flash instead). - # - # See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description - # Bit Symbol Value Description Reset - # value - # 0 MAP Memory map control. 0 - # 0 Boot mode. A portion of the Boot ROM is mapped to address 0. - # 1 User mode. The on-chip Flash memory is mapped to address 0. - # 31:1 - Reserved. The value read from a reserved bit is not defined. NA - # - # http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user - - mww 0x400FC040 0x01 -} +# NXP LPC1768 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM, +set CHIPNAME lpc1768 +set CPUTAPID 0x4ba00477 +set CPURAMSIZE 0x8000 +set CPUROMSIZE 0x80000 + +# After reset the chip is clocked by the ~4MHz internal RC oscillator. +# When board-specific code (reset-init handler or device firmware) +# configures another oscillator and/or PLL0, set CCLK to match; if +# you don't, then flash erase and write operations may misbehave. +# (The ROM code doing those updates cares about core clock speed...) +# +# CCLK is the core clock frequency in KHz +set CCLK 4000 + +#Include the main configuration file. +source [find target/lpc17xx.cfg]; diff --git a/tcl/target/lpc1768.cfg b/tcl/target/lpc17xx.cfg similarity index 68% copy from tcl/target/lpc1768.cfg copy to tcl/target/lpc17xx.cfg index 8bcab9ba5..379bcfb93 100644 --- a/tcl/target/lpc1768.cfg +++ b/tcl/target/lpc17xx.cfg @@ -1,4 +1,12 @@ -# NXP LPC1768 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM, +# Main file for NXP LPC17xx Cortex-M3 +# +# !!!!!! +# +# This file should not be included directly, rather +# by the lpc1751.cfg, lpc1752.cfg, etc. which set the +# needed variables to the appropriate values. +# +# !!!!!! # LPC17xx chips support both JTAG and SWD transports. # Adapt based on what transport is active. @@ -7,7 +15,7 @@ source [find target/swj-dp.tcl] if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME lpc1768 + error "_CHIPNAME not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)." } # After reset the chip is clocked by the ~4MHz internal RC oscillator. @@ -26,19 +34,19 @@ if { [info exists CCLK] } { if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { - set _CPUTAPID 0x4ba00477 + error "_CPUTAPID not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)." } if { [info exists CPURAMSIZE] } { set _CPURAMSIZE $CPURAMSIZE } else { - set _CPURAMSIZE 0x8000 + error "_CPURAMSIZE not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)." } if { [info exists CPUROMSIZE] } { set _CPUROMSIZE $CPUROMSIZE } else { - set _CPUROMSIZE 0x80000 + error "_CPUROMSIZE not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)." } #delays on reset lines @@ -51,12 +59,11 @@ swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME cortex_m3 -chain-position $_TARGETNAME -# LPC1768 has 32kB of SRAM In the ARMv7-M "Code" area (at 0x10000000) -# and 32K more on AHB, in the ARMv7-M "SRAM" area, (at 0x2007c000). +# The LPC17xx devices have 8/16/32kB of SRAM In the ARMv7-M "Code" area (at 0x10000000) $_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_CPURAMSIZE -# LPC1768 has 512kB of flash memory, managed by ROM code (including a -# boot loader which verifies the flash exception table's checksum). +# The LPC17xx devies have 32/64/128/256/512kB of flash memory, managed by ROM code +# (including a boot loader which verifies the flash exception table's checksum). # flash bank lpc2000 0 0 [calc checksum] set _FLASHNAME $_CHIPNAME.flash flash bank $_FLASHNAME lpc2000 0x0 $_CPUROMSIZE 0 0 $_TARGETNAME \ -- 2.11.4.GIT