From 62b526dbbdec073cdcf95bf5cdf622401aa55e78 Mon Sep 17 00:00:00 2001 From: Tobias Diedrich Date: Mon, 1 Aug 2016 20:29:41 +0200 Subject: [PATCH] mips32: MIPS32_OP_SRL was using SRA opcode. The mips opcode macro for the SRL opcode was using the wrong constant value: SRA -- Shift right arithmetic Encoding: 0000 00-- ---t tttt dddd dhhh hh00 0011 SRL -- Shift right logical Encoding: 0000 00-- ---t tttt dddd dhhh hh00 0010 This corrects the opcode constant for SRL and adds the SRA opcode for completeness. There is only one user of MIPS32_OP_SRL in src/flash/nor/cfi.c: Since the mask constant (0x00000080 for the DQ7 mask) shifted in this case would never have the sign bit set, it worked fine even though it was accidentally using the SRA opcode instead of SRL. Change-Id: I0a80746e2075c7df1ce35b9db00d9d0b997a3feb Signed-off-by: Tobias Diedrich Reviewed-on: https://review.openocd.org/c/openocd/+/3613 Tested-by: jenkins Reviewed-by: Antonio Borneo Reviewed-by: Oleksij Rempel --- src/target/mips32.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/target/mips32.h b/src/target/mips32.h index d072eb99a..fc896248b 100644 --- a/src/target/mips32.h +++ b/src/target/mips32.h @@ -380,7 +380,8 @@ struct mips32_algorithm { #define MIPS32_OP_XORI 0x0Eu #define MIPS32_OP_XOR 0x26u #define MIPS32_OP_SLTU 0x2Bu -#define MIPS32_OP_SRL 0x03u +#define MIPS32_OP_SRL 0x02u +#define MIPS32_OP_SRA 0x03u #define MIPS32_OP_SYNCI 0x1Fu #define MIPS32_OP_SLL 0x00u #define MIPS32_OP_SLTI 0x0Au @@ -439,7 +440,8 @@ struct mips32_algorithm { #define MIPS32_ISA_SLL(dst, src, sa) MIPS32_R_INST(MIPS32_OP_SPECIAL, 0, src, dst, sa, MIPS32_OP_SLL) #define MIPS32_ISA_SLTI(tar, src, val) MIPS32_I_INST(MIPS32_OP_SLTI, src, tar, val) #define MIPS32_ISA_SLTU(dst, src, tar) MIPS32_R_INST(MIPS32_OP_SPECIAL, src, tar, dst, 0, MIPS32_OP_SLTU) -#define MIPS32_ISA_SRL(reg, src, off) MIPS32_R_INST(0, 0, src, reg, off, MIPS32_OP_SRL) +#define MIPS32_ISA_SRA(reg, src, off) MIPS32_R_INST(MIPS32_OP_SPECIAL, 0, src, reg, off, MIPS32_OP_SRA) +#define MIPS32_ISA_SRL(reg, src, off) MIPS32_R_INST(MIPS32_OP_SPECIAL, 0, src, reg, off, MIPS32_OP_SRL) #define MIPS32_ISA_SYNC 0xFu #define MIPS32_ISA_SYNCI(off, base) MIPS32_I_INST(MIPS32_OP_REGIMM, base, MIPS32_OP_SYNCI, off) -- 2.11.4.GIT