From 036de3b48217e9c0b5ec0bbf6638e9cad6cae517 Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Sun, 16 May 2021 14:02:53 +0200 Subject: [PATCH] riscv: replace macro DIM() with ARRAY_SIZE() OpenOCD already defines the macro ARRAY_SIZE, while riscv code uses a local macro DIM. Prefer using the macro ARRAY_SIZE() instead of DIM(). Not all the riscv code has been upstreamed, yes; this patch only covers the code already upstreamed. Change-Id: I89a58a6d91916d85c53ba5e4091b558271f8d618 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6258 Reviewed-by: Xiang W Tested-by: jenkins Reviewed-by: Tim Newsome --- src/target/riscv/riscv-011.c | 4 +--- src/target/riscv/riscv-013.c | 4 +--- src/target/riscv/riscv.c | 16 +++++++--------- 3 files changed, 9 insertions(+), 15 deletions(-) diff --git a/src/target/riscv/riscv-011.c b/src/target/riscv/riscv-011.c index 9b5f7491b..7a5e990ca 100644 --- a/src/target/riscv/riscv-011.c +++ b/src/target/riscv/riscv-011.c @@ -70,8 +70,6 @@ #define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1))) #define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask))) -#define DIM(x) (sizeof(x)/sizeof(*x)) - /* Constants for legacy SiFive hardware breakpoints. */ #define CSR_BPCONTROL_X (1<<0) #define CSR_BPCONTROL_W (1<<1) @@ -1634,7 +1632,7 @@ static riscv_error_t handle_halt_routine(struct target *target) /* Read S0 from dscratch */ unsigned int csr[] = {CSR_DSCRATCH0, CSR_DPC, CSR_DCSR}; - for (unsigned int i = 0; i < DIM(csr); i++) { + for (unsigned int i = 0; i < ARRAY_SIZE(csr); i++) { scans_add_write32(scans, 0, csrr(S0, csr[i]), true); scans_add_read(scans, SLOT0, false); } diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 32a7f0248..b70c259dc 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -86,8 +86,6 @@ static int riscv013_test_compliance(struct target *target); #define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1))) #define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask))) -#define DIM(x) (sizeof(x)/sizeof(*x)) - #define CSR_DCSR_CAUSE_SWBP 1 #define CSR_DCSR_CAUSE_TRIGGER 2 #define CSR_DCSR_CAUSE_DEBUGINT 3 @@ -358,7 +356,7 @@ static void decode_dmi(char *text, unsigned address, unsigned data) }; text[0] = 0; - for (unsigned i = 0; i < DIM(description); i++) { + for (unsigned i = 0; i < ARRAY_SIZE(description); i++) { if (description[i].address == address) { uint64_t mask = description[i].mask; unsigned value = get_field(data, mask); diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index 7b7b7284d..fa07fe821 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -23,8 +23,6 @@ #define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1))) #define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask))) -#define DIM(x) (sizeof(x)/sizeof(*x)) - /* Constants for legacy SiFive hardware breakpoints. */ #define CSR_BPCONTROL_X (1<<0) #define CSR_BPCONTROL_W (1<<1) @@ -184,10 +182,10 @@ struct scan_field _bscan_tunnel_nested_tap_select_dmi[] = { } }; struct scan_field *bscan_tunnel_nested_tap_select_dmi = _bscan_tunnel_nested_tap_select_dmi; -uint32_t bscan_tunnel_nested_tap_select_dmi_num_fields = DIM(_bscan_tunnel_nested_tap_select_dmi); +uint32_t bscan_tunnel_nested_tap_select_dmi_num_fields = ARRAY_SIZE(_bscan_tunnel_nested_tap_select_dmi); struct scan_field *bscan_tunnel_data_register_select_dmi = _bscan_tunnel_data_register_select_dmi; -uint32_t bscan_tunnel_data_register_select_dmi_num_fields = DIM(_bscan_tunnel_data_register_select_dmi); +uint32_t bscan_tunnel_data_register_select_dmi_num_fields = ARRAY_SIZE(_bscan_tunnel_data_register_select_dmi); struct trigger { uint64_t address; @@ -348,8 +346,8 @@ uint32_t dtmcontrol_scan_via_bscan(struct target *target, uint32_t out) tunneled_dr[0].in_value = NULL; } jtag_add_ir_scan(target->tap, &select_user4, TAP_IDLE); - jtag_add_dr_scan(target->tap, DIM(tunneled_ir), tunneled_ir, TAP_IDLE); - jtag_add_dr_scan(target->tap, DIM(tunneled_dr), tunneled_dr, TAP_IDLE); + jtag_add_dr_scan(target->tap, ARRAY_SIZE(tunneled_ir), tunneled_ir, TAP_IDLE); + jtag_add_dr_scan(target->tap, ARRAY_SIZE(tunneled_dr), tunneled_dr, TAP_IDLE); select_dmi_via_bscan(target); int retval = jtag_execute_queue(); @@ -1788,7 +1786,7 @@ static int riscv_run_algorithm(struct target *target, int num_mem_params, GDB_REGNO_PC, GDB_REGNO_MSTATUS, GDB_REGNO_MEPC, GDB_REGNO_MCAUSE, }; - for (unsigned i = 0; i < DIM(regnums); i++) { + for (unsigned i = 0; i < ARRAY_SIZE(regnums); i++) { enum gdb_regno regno = regnums[i]; riscv_reg_t reg_value; if (riscv_get_register(target, ®_value, regno) != ERROR_OK) @@ -3768,7 +3766,7 @@ int riscv_init_registers(struct target *target) #undef DECLARE_CSR }; /* encoding.h does not contain the registers in sorted order. */ - qsort(csr_info, DIM(csr_info), sizeof(*csr_info), cmp_csr_info); + qsort(csr_info, ARRAY_SIZE(csr_info), sizeof(*csr_info), cmp_csr_info); unsigned csr_info_index = 0; unsigned custom_range_index = 0; @@ -4028,7 +4026,7 @@ int riscv_init_registers(struct target *target) unsigned csr_number = number - GDB_REGNO_CSR0; while (csr_info[csr_info_index].number < csr_number && - csr_info_index < DIM(csr_info) - 1) { + csr_info_index < ARRAY_SIZE(csr_info) - 1) { csr_info_index++; } if (csr_info[csr_info_index].number == csr_number) { -- 2.11.4.GIT