| commit | cb5c6477f53c352d5997f84fae6d527d9f2557e7 | |
| author | Tomas Vanek <vanekt@fbl.cz> | |
| Fri, 7 Dec 2018 16:00:12 +0000 (7 17:00 +0100) | ||
| committer | Tomas Vanek <vanekt@fbl.cz> | |
| Wed, 19 Dec 2018 13:14:09 +0000 (19 13:14 +0000) | ||
| tree | 163ab32b8ff97cd84de53e73de9f2d6e68e78a7d | treesnapshot (tar.gz zip) |
| parent | 651998e33771bdad56873e3e70bd875104ca1d12 | commitdiff |
target/cortex_m: do not use VECTRESET on Cortex-M0, M0+ and M1
Cortex-M0, M0+ and M1 do not support VECTRESET bit in AIRCR.
Without this change the 'reset' command silently fails if VECTRESET
is requested.
Detect these cores, show warning if VECTRESET is about to use
and use SYSRESETREQ instead.
Change-Id: Ief174373e3ef0e6b287c57911c0aca4dfa8209f2
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4794
Tested-by: jenkins
Reviewed-by: Jean-Christian de Rivaz <jcamdr70@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Cortex-M0, M0+ and M1 do not support VECTRESET bit in AIRCR.
Without this change the 'reset' command silently fails if VECTRESET
is requested.
Detect these cores, show warning if VECTRESET is about to use
and use SYSRESETREQ instead.
Change-Id: Ief174373e3ef0e6b287c57911c0aca4dfa8209f2
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4794
Tested-by: jenkins
Reviewed-by: Jean-Christian de Rivaz <jcamdr70@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
| doc/openocd.texi | diffblobblamehistory | |
| src/target/cortex_m.c | diffblobblamehistory | |
| src/target/cortex_m.h | diffblobblamehistory |